专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20090245257A1 Network On Chip 审中-公开
标题翻译：网络芯片
公开(公告)号：US20090245257A1
公开(公告)日：2009-10-01
申请号：US12060559
申请日：2008-04-01
申请人： Miguel Comparan , Russell D. Hoover
发明人： Miguel Comparan , Russell D. Hoover
IPC分类号： H04L12/28
CPC分类号： H04L45/00 , H04L45/60 , H04L49/109 , H04L49/25
摘要： A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with all communications including a route code specifying a route through the routers of the NOC from a source to a destination, each router including routing logic that directs a communication to one of four ports of the router, the one port identified by the first two bits in the route code. The routing logic in the router shifts the route code to discard the first two bits of the route code before transmitting the communication through the one port.
摘要翻译：包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），所有通信包括指定从源的路由器通过NOC的路由器的路由到目的地，每个路由器包括将通信引导到路由器的四个端口之一的路由逻辑，由路由代码中的前两个比特标识的一个端口。在通过一个端口发送通信之前，路由器中的路由逻辑将移动路由代码以丢弃路由代码的前两位。

12. 发明申请

US20090113181A1 Method and Apparatus for Executing Instructions 有权
标题翻译：执行指令的方法和装置
公开(公告)号：US20090113181A1
公开(公告)日：2009-04-30
申请号：US11877754
申请日：2007-10-24
申请人： Miguel Comparan , Brent Francis Hilgart , Brian Lee Koehler , Eric Oliver Mejdrich , Adam James Muff , Alfred Thomas Watson, III
发明人： Miguel Comparan , Brent Francis Hilgart , Brian Lee Koehler , Eric Oliver Mejdrich , Adam James Muff , Alfred Thomas Watson, III
IPC分类号： G06F9/312
CPC分类号： G06F9/3885 , G06F9/3851
摘要： A method and apparatus for executing instructions in a processor are provided. In one embodiment of the invention, the method includes receiving a plurality of instructions. The plurality of instructions includes first instructions in a first thread and second instructions in a second thread. The method further includes forming a common issue group including an instruction of a first instruction type and an instruction of a second instruction type. The method also includes issuing the common issue group to a first execution unit and a second execution unit. The instruction of the first instruction type is issued to the first execution unit and the instruction of the second instruction type is issued to the second execution unit.
摘要翻译：提供了一种用于在处理器中执行指令的方法和装置。在本发明的一个实施例中，该方法包括接收多个指令。多个指令包括第一线程中的第一指令和第二线程中的第二指令。该方法还包括形成包括第一指令类型的指令和第二指令类型的指令的公共发行组。该方法还包括向第一执行单元和第二执行单元发布公共问题组。向第一执行单元发出第一指令类型的指令，并向第二执行单元发出第二指令类型的指令。

13. 发明申请

US20180211638A1 No Miss Cache Structure for Real-Time Image Transformations 审中-公开
公开(公告)号：US20180211638A1
公开(公告)日：2018-07-26
申请号：US15415569
申请日：2017-01-25
申请人： Tolga Ozguner , Jeffrey Powers Bradford , Miguel Comparan , Gene Leung , Adam James Muff , Ryan Scott Haraden , Christopher Jon Johnson
发明人： Tolga Ozguner , Jeffrey Powers Bradford , Miguel Comparan , Gene Leung , Adam James Muff , Ryan Scott Haraden , Christopher Jon Johnson
IPC分类号： G09G5/395 , G06T1/60 , G06T1/20 , G09G5/00 , G02B27/01 , G03H1/00
CPC分类号： G09G5/395 , G02B27/0103 , G02B27/017 , G02B2027/014 , G02B2027/0178 , G02B2027/0187 , G03H1/0005 , G03H2001/0088 , G06F1/163 , G06F3/011 , G06F12/0207 , G06F12/0862 , G06F12/121 , G06F12/128 , G06F2212/1016 , G06F2212/1028 , G06F2212/1044 , G06F2212/455 , G06F2212/6026 , G06T1/20 , G06T1/60 , G09G3/003 , G09G2360/121 , Y02D10/13
摘要： Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power.

14. 发明授权

US08719507B2 Near neighbor data cache sharing 有权
标题翻译：近邻数据缓存共享
公开(公告)号：US08719507B2
公开(公告)日：2014-05-06
申请号：US13343236
申请日：2012-01-04
申请人： Miguel Comparan , Robert A. Shearer
发明人： Miguel Comparan , Robert A. Shearer
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0811 , G06F12/0817 , G06F12/0893 , G06F12/0895 , G06F12/0897
摘要： Parallel computing environments, where threads executing in neighboring processors may access the same set of data, may be designed and configured to share one or more levels of cache memory. Before a processor forwards a request for data to a higher level of cache memory following a cache miss, the processor may determine whether a neighboring processor has the data stored in a local cache memory. If so, the processor may forward the request to the neighboring processor to retrieve the data. Because access to the cache memories for the two processors is shared, the effective size of the memory is increased. This may advantageously decrease cache misses for each level of shared cache memory without increasing the individual size of the caches on the processor chip.
摘要翻译：在相邻处理器中执行的线程可以访问同一组数据的并行计算环境可被设计和配置为共享一个或多个级别的高速缓冲存储器。在处理器在高速缓存未命中之后将数据请求转发到更高级别的高速缓冲存储器之前，处理器可以确定相邻处理器是否具有存储在本地高速缓冲存储器中的数据。如果是这样，则处理器可以将该请求转发到相邻处理器以检索数据。因为对两个处理器的高速缓冲存储器的访问被共享，所以存储器的有效大小增加。这可以有利地减少每个级别的共享高速缓冲存储器的高速缓存未命中，而不增加处理器芯片上的高速缓存的单独大小。

15. 发明授权

US08560897B2 Hard memory array failure recovery utilizing locking structure 失效
标题翻译：使用锁定结构的硬盘阵列故障恢复
公开(公告)号：US08560897B2
公开(公告)日：2013-10-15
申请号：US12961947
申请日：2010-12-07
申请人： Miguel Comparan , Mark G. Kupferschmidt , Robert A. Shearer
发明人： Miguel Comparan , Mark G. Kupferschmidt , Robert A. Shearer
IPC分类号： G06F11/00
CPC分类号： G06F11/0727 , G06F11/0724 , G06F11/073 , G06F11/0772
摘要： A technique for managing hard failures in a memory system employing a locking is disclosed. An error count is maintained for units of memory within the memory system. When the error count indicates a hard failure, the unit of memory is locked out from further use. An arbitrary set of error counters are assigned to record errors resulting from access to the units of memory. Embodiments of the present invention advantageously enable a system to continue reliable operation even after one or more internal hard memory failures. Other embodiments advantageously enable manufacturers to salvage partially failed devices and deploy the devices as having a lower-performance specification rather than discarding the devices, as would otherwise be indicated by conventional practice.
摘要翻译：公开了一种用于管理采用锁定的存储器系统中的硬故障的技术。内存系统中的内存单元维护错误计数。当错误计数表示硬故障时，内存单元被锁定以供进一步使用。分配一组任意错误计数器来记录访问内存单元所产生的错误。本发明的实施例有利地使得即使在一个或多个内部硬盘存储器故障之后，系统也能够继续可靠的操作。其他实施例有利地使得制造商能够回收部分故障的设备，并且将设备部署为具有较低性能规范而不是丢弃设备，否则将由常规实践指出。

16. 发明授权

US08493398B2 Dynamic data type aligned cache optimized for misaligned packed structures 有权
标题翻译：动态数据类型对齐缓存针对不对齐的打包结构进行了优化
公开(公告)号：US08493398B2
公开(公告)日：2013-07-23
申请号：US12013780
申请日：2008-01-14
申请人： Miguel Comparan , Russell Dean Hoover , Eric Oliver Mejdrich
发明人： Miguel Comparan , Russell Dean Hoover , Eric Oliver Mejdrich
IPC分类号： G09G5/36 , G06T1/20
CPC分类号： G06F12/0862 , G06F12/0886
摘要： A method and apparatus for processing vector data is provided. A processing core may have a data cache and a relatively smaller vector data cache. The vector data cache may be optimally sized to store vector data structures that are smaller than full data cache lines.
摘要翻译：提供了一种用于处理向量数据的方法和装置。处理核心可以具有数据高速缓存和相对较小的向量数据高速缓存。矢量数据高速缓存可以被最优化地大小以存储小于全数据高速缓存行的向量数据结构。

17. 发明申请

US20130159669A1 LOW LATENCY VARIABLE TRANSFER NETWORK FOR FINE GRAINED PARALLELISM OF VIRTUAL THREADS ACROSS MULTIPLE HARDWARE THREADS 有权
标题翻译：低延迟可变传输网络，用于通过多个硬件线程的虚拟螺纹的精细平行平行
公开(公告)号：US20130159669A1
公开(公告)日：2013-06-20
申请号：US13330831
申请日：2011-12-20
申请人： Miguel Comparan , Russell D. Hoover , Robert A. Shearer , Alfred T. Watson, III
发明人： Miguel Comparan , Russell D. Hoover , Robert A. Shearer , Alfred T. Watson, III
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/3824 , G06F9/3828 , G06F9/3851 , G06F9/3891 , G06F9/544 , G06F15/173
摘要： A method and circuit arrangement utilize a low latency variable transfer network between the register files of multiple processing cores in a multi-core processor chip to support fine grained parallelism of virtual threads across multiple hardware threads. The communication of a variable over the variable transfer network may be initiated by a move from a local register in a register file of a source processing core to a variable register that is allocated to a destination hardware thread in a destination processing core, so that the destination hardware thread can then move the variable from the variable register to a local register in the destination processing core.
摘要翻译：一种方法和电路装置利用多核处理器芯片中的多个处理核心的寄存器文件之间的低延迟可变传输网络来支持跨多个硬件线程的虚拟线程的细粒度并行。可变传输网络上的变量的通信可以通过从源处理核心的寄存器文件中的本地寄存器移动到分配给目的地处理核心中的目的地硬件线程的可变寄存器来启动，使得目标硬件线程可以将变量从变量寄存器移动到目标处理核心中的本地寄存器。

18. 发明申请

US20120169755A1 ANISOTROPIC TEXTURE FILTERING WITH TEXTURE DATA PREFETCHING 有权
标题翻译：具有纹理数据预选的各向异性纹理滤波
公开(公告)号：US20120169755A1
公开(公告)日：2012-07-05
申请号：US13421169
申请日：2012-03-15
申请人： Miguel Comparan , Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
发明人： Miguel Comparan , Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
IPC分类号： G09G5/00
CPC分类号： G06T15/04 , G06T2200/12
摘要： A circuit arrangement and method utilize texture data prefetching to prefetch texture data used by an anisotropic filtering algorithm. In particular, stride-based prefetching may be used to prefetch texture data for use in anisotropic filtering, where the value of the stride, or difference between successive accesses, is based upon a distance in a memory address space between sample points taken along the line of anisotropy used in an anisotropic filtering algorithm.
摘要翻译：电路布置和方法利用纹理数据预取来预取由各向异性滤波算法使用的纹理数据。特别地，可以使用基于步幅的预取来预取用于各向异性过滤中的纹理数据，其中步幅的值或连续访问之间的差是基于沿着线所取的采样点之间的存储器地址空间中的距离在各向异性过滤算法中使用各向异性。

19. 发明授权

US07917703B2 Network on chip that maintains cache coherency with invalidate commands 失效
标题翻译：使用无效命令维护高速缓存一致性的片上网络
公开(公告)号：US07917703B2
公开(公告)日：2011-03-29
申请号：US11955553
申请日：2007-12-13
申请人： Miguel Comparan , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich , Alfred T. Watson, III
发明人： Miguel Comparan , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich , Alfred T. Watson, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0837 , G06F15/7825
摘要： A network on chip (‘NOC’) comprising integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block coupled to a router through a memory communications controller and a network interface controller, the NOC also including a port on a router of the network through which is received an invalidate command, the invalidate command including an identification of a cache line, the invalidate command representing an instruction to invalidate the cache line, the router configured to send the invalidate command to an IP block served by the router; the router further configured to send the invalidate command horizontally and vertically to neighboring routers if the port is a vertical port; and the router further configured to send the invalidate command only horizontally to neighboring routers if the port is a horizontal port.
摘要翻译：包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），每个IP块通过存储器通信控制器和网络接口控制器耦合到路由器，NOC 还包括在通过其接收到无效命令的网络的路由器上的端口，包括高速缓存行的标识的无效命令，表示使高速缓存行无效的指令的无效命令，被配置为将无效命令发送到由路由器服务的IP块; 路由器还配置为如果端口是垂直端口，则将无效命令水平和垂直地发送到相邻路由器; 并且该路由器还被配置为仅当该端口是水平端口时才将水平地发送到相邻路由器的invalidate命令。

20. 发明申请

US20090179902A1 Dynamic Data Type Aligned Cache Optimized for Misaligned Packed Structures 有权
标题翻译：动态数据类型对齐缓存针对未对齐的打包结构进行了优化
公开(公告)号：US20090179902A1
公开(公告)日：2009-07-16
申请号：US12013780
申请日：2008-01-14
申请人： Miguel Comparan , Russell Dean Hoover , Eric Oliver Mejdrich
发明人： Miguel Comparan , Russell Dean Hoover , Eric Oliver Mejdrich
IPC分类号： G06F15/16 , G06F13/00
CPC分类号： G06F12/0862 , G06F12/0886
摘要： A method and apparatus for processing vector data is provided. A processing core may have a data cache and a relatively smaller vector data cache. The vector data cache may be optimally sized to store vector data structures that are smaller than full data cache lines.
摘要翻译：提供了一种用于处理向量数据的方法和装置。处理核心可以具有数据高速缓存和相对较小的向量数据高速缓存。矢量数据高速缓存可以被最优化地大小以存储小于全数据高速缓存行的向量数据结构。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式