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11. 发明申请

US20130339821A1 THREE DIMENSIONAL(3D) MEMORY DEVICE SPARING 有权
标题翻译：三维（3D）存储器件分配
公开(公告)号：US20130339821A1
公开(公告)日：2013-12-19
申请号：US13523195
申请日：2012-06-14
申请人： Edgar R. Cordero , Anil B. Lingambudi , Saravanan Sethuraman , Kenneth L. Wright
发明人： Edgar R. Cordero , Anil B. Lingambudi , Saravanan Sethuraman , Kenneth L. Wright
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G11C29/4401 , G06F11/1048 , G06F11/1072 , G06F11/1666 , G06F11/20 , G11C7/24 , G11C29/70 , G11C29/83 , G11C2029/0411 , H03M13/05
摘要： According to one embodiment of the present invention, a method for bank sparing in a 3D memory device that includes detecting, by a memory controller, a first error in the 3D memory device and detecting a second error in a first element in a first rank of the 3D memory device, wherein the first element in the first rank has an associated first chip select. The method also includes sending a command to the 3D memory device to set mode registers in a master logic portion of the 3D memory device that enable a second element to receive communications directed to the first element and wherein the second element is in a second rank of the 3D memory device, wherein the first element and second element are each either a bank or a bank group that comprise a plurality of chips.
摘要翻译：根据本发明的一个实施例，一种用于在三维存储器件中进行库保存的方法，该方法包括由存储器控制器检测3D存储器件中的第一个误差并检测第一个等级的第一个元件中的第二个误差 3D存储器件，其中第一级中的第一元件具有相关联的第一片选。该方法还包括向3D存储器设备发送命令以设置3D存储器件的主逻辑部分中的模式寄存器，其使得第二元件能够接收指向第一元件的通信，并且其中第二元件处于第二等级 3D存储器件，其中第一元件和第二元件各自是包括多个芯片的存储体或存储体组。

12. 发明授权

US08589776B2 Translation between a first communication protocol and a second communication protocol 失效
标题翻译：第一通信协议和第二通信协议之间的转换
公开(公告)号：US08589776B2
公开(公告)日：2013-11-19
申请号：US13150486
申请日：2011-06-01
申请人： Jean L. Calvignac , Daniel G. Eisenhauer , Ashish A. More , Anil Pothireddy , Christoph Raisch , Saravanan Sethuraman , Vibhor K. Srivastava , Jan-Bernd Themann
发明人： Jean L. Calvignac , Daniel G. Eisenhauer , Ashish A. More , Anil Pothireddy , Christoph Raisch , Saravanan Sethuraman , Vibhor K. Srivastava , Jan-Bernd Themann
IPC分类号： G06F11/10
CPC分类号： H04L69/08 , H03M13/09
摘要： Translating between a first communication protocol used by a first network component and a second communication protocol used by a second network, where translating includes: receiving, by a network engine adapter operating independently from the first and second network components, data packets from the first and second network components; and performing, by the network engine, a combined communication protocol based on the first communication protocol and the second communication protocol, including manipulating data packets of at least one of the first communication protocol or the second communication protocol, thereby offloading performance requirements for the combined communication protocol from the first and second network components.
摘要翻译：在由第一网络组件使用的第一通信协议和由第二网络使用的第二通信协议之间进行翻译，其中转换包括：由独立于第一和第二网络组件的网络引擎适配器接收来自第一和第二网络组件的数据分组第二网络组件; 以及由网络引擎执行基于第一通信协议和第二通信协议的组合通信协议，包括操纵第一通信协议或第二通信协议中的至少一个的数据分组，由此卸载组合的性能要求来自第一和第二网络组件的通信协议。

13. 发明授权

US07921404B2 Method of reusing constraints in PCB designs 失效
标题翻译：在PCB设计中重用约束的方法
公开(公告)号：US07921404B2
公开(公告)日：2011-04-05
申请号：US11954092
申请日：2007-12-11
申请人： Anil Bindu Lingambudi , Ankur Kanu Patel , Saravanan Sethuraman , Diyanesh Vidyapoornachary Babu Chinnakkonda
发明人： Anil Bindu Lingambudi , Ankur Kanu Patel , Saravanan Sethuraman , Diyanesh Vidyapoornachary Babu Chinnakkonda
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method is disclosed for electronically processing constraints rules defined in a previously developed first PCB design having a first constraints output file, to facilitate the development of a second PCB design having a second constraints output file. The second design has substantially identical topology to the first design and the second constraints output file comprises constraints for signals with identical attributes. The method includes several steps. Firstly, the board file of the first design is compared with the net list file of the second design to identify respective differences between the designs. On the basis of the established differences, a file attributes change report is generated. At least some data from the file attributes change report is stored into an attributes change file. Finally, the method includes the step of processing the first design constraints output file, the second design constraints output file, and the attribute change file to map constraints associated with changed attributes, thus defining a revised constraints output file for the second design. The revised second constraints output file comprises constraints for at least some signals with changed attributes.
摘要翻译：公开了一种用于电子处理在先前开发的具有第一约束输出文件的第一PCB设计中定义的约束规则的方法，以便于开发具有第二约束输出文件的第二PCB设计。第二设计具有与第一设计基本相同的拓扑，第二约束输出文件包括具有相同属性的信号的约束。该方法包括几个步骤。首先，将第一设计的板文件与第二设计的网表文件进行比较，以识别设计之间的差异。在建立的差异的基础上，生成文件属性变更报告。文件属性更改报告中的至少一些数据将存储到属性更改文件中。最后，该方法包括处理第一设计约束输出文件，第二设计约束输出文件和属性更改文件以映射与改变的属性相关联的约束的步骤，从而为第二设计定义修改的约束输出文件。修改的第二约束输出文件包括至少一些具有变化属性的信号的约束。

14. 发明申请

US20110071800A1 SYSTEM AND METHOD FOR PROVIDING EFFICIENT SCHEMATIC REVIEW 失效
标题翻译：提供有效图形评价的系统和方法
公开(公告)号：US20110071800A1
公开(公告)日：2011-03-24
申请号：US12566509
申请日：2009-09-24
申请人： Saravanan Sethuraman , John Francis Mullen
发明人： Saravanan Sethuraman , John Francis Mullen
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5045
摘要： A system and method for providing schematic reviews is provided. The method includes providing a schematic design, selecting a signal, where the signal is a graphical representation, previewing the signal, obtaining relevant information on components constituting the signal, and controlling the signal to obtain relevant information on the components. Controlling the signal comprises activating a link to a data compilation related to the signal component, and activating the data compilation comprises creating a link to a datasheet. The graphic representation of the signal comprises providing a block diagram overview of connectivity of the signal components and the graphical representation comprises a graphical three dimensional model, and providing a log database that includes review information provided by multiple reviewers and is accessible by the reviewers. A notation medium is provided for the reviewers for communication between the reviewers.
摘要翻译：提供了一种用于提供示意图评估的系统和方法。该方法包括提供示意性设计，选择信号，其中信号是图形表示，预览信号，获得关于组成信号的组件的相关信息，以及控制信号以获得关于组件的相关信息。控制信号包括激活与信号分量相关的数据汇编的链接，并且激活数据编译包括创建到数据表的链接。信号的图形表示包括提供信号分量的连接性的框图，图形表示包括图形三维模型，以及提供包括由多个审阅者提供的审阅信息并且可由审阅者访问的日志数据库。为审阅者提供了一种记录介质，用于审阅者之间的通信。

15. 发明申请

US20100042961A1 IDENTIFICATION OF VOLTAGE REFERENCE ERRORS IN PCB DESIGNS 有权
标题翻译： PCB设计中电压参考误差的识别
公开(公告)号：US20100042961A1
公开(公告)日：2010-02-18
申请号：US12193119
申请日：2008-08-18
申请人： Anil Bindu Lingambudi , Saravanan Sethuraman , Anandavally Sreekala
发明人： Anil Bindu Lingambudi , Saravanan Sethuraman , Anandavally Sreekala
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Disclosed is a computer implemented method for determining a voltage reference error in a PCB design comprising receiving information about said PCB design, identifying a signal associated with said design, receiving one or more user defined voltage references for said signal, and comparing the user defined voltage reference to the voltages of the power planes adjacent to said signal.
摘要翻译：公开了一种用于确定PCB设计中的电压参考误差的计算机实现方法，包括接收关于所述PCB设计的信息，识别与所述设计相关联的信号，接收用于所述信号的一个或多个用户定义的电压参考，以及将用户定义的电压参考与所述信号相邻的电力平面的电压。

16. 发明授权

US09128887B2 Using a buffer to replace failed memory cells in a memory component 有权
标题翻译：使用缓冲区来替换内存组件中的故障内存单元
公开(公告)号：US09128887B2
公开(公告)日：2015-09-08
申请号：US13589487
申请日：2012-08-20
申请人： Manoj Dusanapudi , Prasanna Jayaraman , Anil B. Lingambudi , Girisankar Paulraj , Saravanan Sethuraman , Diyanesh B. Vidyapoornachary
发明人： Manoj Dusanapudi , Prasanna Jayaraman , Anil B. Lingambudi , Girisankar Paulraj , Saravanan Sethuraman , Diyanesh B. Vidyapoornachary
IPC分类号： G06F11/16
CPC分类号： G06F11/16 , G06F11/1666 , G06F11/20
摘要： Methods and data processing systems for using a buffer to replace failed memory cells in a memory component are provided. Embodiments include determining that a first copy of data stored within a plurality of memory cells of a memory component contains one or more errors; in response to determining that the first copy contains one or more errors, determining whether a backup cache within the buffer contains a second copy of the data; and in response to determining that the backup cache contains the second copy of the data, transferring the second copy from the backup cache to a location within an error data queue (EDQ) within the buffer and updating the buffer controller to use the location within the EDQ instead of the plurality of memory cells within the memory component.
摘要翻译：提供了用于使用缓冲器来替换存储器组件中的故障存储器单元的方法和数据处理系统。实施例包括确定存储在存储器组件的多个存储器单元内的数据的第一副本包含一个或多个错误; 响应于确定所述第一副本包含一个或多个错误，确定所述缓冲器内的备份高速缓存是否包含所述数据的第二副本; 并且响应于确定所述备份高速缓存包含所述数据的所述第二副本，将所述第二副本从所述备份高速缓存传送到所述缓冲器内的错误数据队列（EDQ）内的位置，并更新所述缓冲器控制器以使用所述缓冲器控制器内的位置 EDQ而不是存储器组件内的多个存储器单元。

17. 发明授权

US08902750B2 Translating between an ethernet protocol and a converged enhanced ethernet protocol 有权
标题翻译：在以太网协议和融合增强型以太网协议之间进行转换
公开(公告)号：US08902750B2
公开(公告)日：2014-12-02
申请号：US13150507
申请日：2011-06-01
申请人： Claude Basso , Anil Pothireddy , Christoph Raisch , Saravanan Sethuraman , Vibhor K. Srivastava , Jan-Bernd Themann , Fabrice J. Verplanken
发明人： Claude Basso , Anil Pothireddy , Christoph Raisch , Saravanan Sethuraman , Vibhor K. Srivastava , Jan-Bernd Themann , Fabrice J. Verplanken
IPC分类号： H04L12/801 , H04L12/26 , H04L29/06 , H04L12/823 , H04L12/835
CPC分类号： H04L47/10 , H04L47/17 , H04L47/30 , H04L47/32 , H04L47/34 , H04L69/08
摘要： Translating between an Ethernet protocol used by a first network component and a Converged Enhanced Ethernet (CEE) protocol used by a second network component, the first and second components coupled through a CEE Converter that translates by: for data flow from the first network component to the second network component: receiving, by the CEE converter, traffic flow definition parameters for a single CEE protocol data flow; calculating, by a credit manager, available buffer space in an outbound frame buffer of the CEE converter for the data flow; communicating, by the credit manager to a CEE credit driver of the first component, the calculated size of the buffer space together with a start sequence number and a flow identifier; and responding, by the CEE credit driver to the CEE converter, with Ethernet frames comprising a private header that includes the flow identifier and a sequence number.
摘要翻译：在由第一网络组件使用的以太网协议和第二网络组件使用的融合增强以太网（CEE）协议之间进行转换，所述第一和第二组件通过CEE转换器耦合，所述CEE转换器通过以下方式耦合：用于从第一网络组件到第二网络组件：由CEE转换器接收单个CEE协议数据流的业务流定义参数; 由信用管理器计算用于数据流的CEE转换器的出站帧缓冲器中的可用缓冲器空间; 由信用管理器将第一组件的CEE信用驱动程序与计算出的缓冲区空间的大小以及起始序列号和流标识符进行通信; 并由CEE信用驱动程序向CEE转换器响应包括包含流标识符和序列号的专用报头的以太网帧。

18. 发明授权

US08874979B2 Three dimensional(3D) memory device sparing 有权
标题翻译：三维（3D）存储设备备用
公开(公告)号：US08874979B2
公开(公告)日：2014-10-28
申请号：US13523195
申请日：2012-06-14
申请人： Edgar R. Cordero , Anil B. Lingambudi , Saravanan Sethuraman , Kenneth L. Wright
发明人： Edgar R. Cordero , Anil B. Lingambudi , Saravanan Sethuraman , Kenneth L. Wright
IPC分类号： G11C29/00 , G11C29/44 , G06F11/10 , H03M13/05
CPC分类号： G11C29/4401 , G06F11/1048 , G06F11/1072 , G06F11/1666 , G06F11/20 , G11C7/24 , G11C29/70 , G11C29/83 , G11C2029/0411 , H03M13/05
摘要： According to one embodiment of the present invention, a method for bank sparing in a 3D memory device that includes detecting, by a memory controller, a first error in the 3D memory device and detecting a second error in a first element in a first rank of the 3D memory device, wherein the first element in the first rank has an associated first chip select. The method also includes sending a command to the 3D memory device to set mode registers in a master logic portion of the 3D memory device that enable a second element to receive communications directed to the first element and wherein the second element is in a second rank of the 3D memory device, wherein the first element and second element are each either a bank or a bank group that comprise a plurality of chips.
摘要翻译：根据本发明的一个实施例，一种用于在三维存储器件中进行库保存的方法，该方法包括由存储器控制器检测3D存储器件中的第一个误差并检测第一个等级的第一个元件中的第二个误差 3D存储器件，其中第一级中的第一元件具有相关联的第一片选。该方法还包括向3D存储器设备发送命令以设置3D存储器件的主逻辑部分中的模式寄存器，其使得第二元件能够接收指向第一元件的通信，并且其中第二元件处于第二等级 3D存储器件，其中第一元件和第二元件各自是包括多个芯片的存储体或存储体组。

19. 发明申请

US20140053016A1 Using A Buffer To Replace Failed Memory Cells In A Memory Component 有权
标题翻译：使用缓冲区替换存储器组件中的故障存储单元
公开(公告)号：US20140053016A1
公开(公告)日：2014-02-20
申请号：US13589487
申请日：2012-08-20
申请人： Manoj Dusanapudi , Prasanna Jayaraman , Anil B. Lingambudi , Girisankar Paulraj , Saravanan Sethuraman , Diyanesh B. Vidyapoornachary
发明人： Manoj Dusanapudi , Prasanna Jayaraman , Anil B. Lingambudi , Girisankar Paulraj , Saravanan Sethuraman , Diyanesh B. Vidyapoornachary
IPC分类号： G06F11/16
CPC分类号： G06F11/16 , G06F11/1666 , G06F11/20
摘要： Methods and data processing systems for using a buffer to replace failed memory cells in a memory component are provided. Embodiments include determining that a first copy of data stored within a plurality of memory cells of a memory component contains one or more errors; in response to determining that the first copy contains one or more errors, determining whether a backup cache within the buffer contains a second copy of the data; and in response to determining that the backup cache contains the second copy of the data, transferring the second copy from the backup cache to a location within an error data queue (EDQ) within the buffer and updating the buffer controller to use the location within the EDQ instead of the plurality of memory cells within the memory component.
摘要翻译：提供了用于使用缓冲器来替换存储器组件中的故障存储器单元的方法和数据处理系统。实施例包括确定存储在存储器组件的多个存储器单元内的数据的第一副本包含一个或多个错误; 响应于确定所述第一副本包含一个或多个错误，确定所述缓冲器内的备份高速缓存是否包含所述数据的第二副本; 并且响应于确定所述备份高速缓存包含所述数据的所述第二副本，将所述第二副本从所述备份高速缓存传送到所述缓冲器内的错误数据队列（EDQ）内的位置，并更新所述缓冲器控制器以使用所述缓冲器控制器内的位置 EDQ而不是存储器组件内的多个存储器单元。

20. 发明申请

US20130339820A1 THREE DIMENSIONAL (3D) MEMORY DEVICE SPARING 有权
标题翻译：三维（3D）存储器件分配
公开(公告)号：US20130339820A1
公开(公告)日：2013-12-19
申请号：US13523091
申请日：2012-06-14
申请人： Edgar R. Cordero , Anil B. Lingambudi , Saravanan Sethuraman , Kenneth L. Wright
发明人： Edgar R. Cordero , Anil B. Lingambudi , Saravanan Sethuraman , Kenneth L. Wright
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1072 , G06F11/1048 , G11C5/04 , G11C11/40 , G11C29/4401 , G11C29/886 , G11C2029/0409 , H03M13/05
摘要： According to one embodiment of the present invention, a method for operating a three dimensional (“3D”) memory device includes detecting, by a memory controller, a first error on the 3D memory device and detecting, by the memory controller, a second error in a first chip in a first rank of the 3D memory device, wherein the first chip has an associated first chip select. The method also includes powering up a second chip in a second rank, sending a command from the memory controller to the 3D memory device to replace the first chip in the first chip select with the second chip and correcting the first error using an error control code.
摘要翻译：根据本发明的一个实施例，一种用于操作三维（“3D”）存储器件的方法包括由存储器控制器检测3D存储器件上的第一个错误，并由存储器控制器检测第二个错误在3D存储器件的第一级中的第一芯片中，其中第一芯片具有相关的第一芯片选择。该方法还包括对第二级别的第二芯片供电，从存储器控制器向3D存储器件发送命令以将第一芯片中的第一芯片替换为第二芯片，并使用错误控制代码校正第一错误。

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