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11. 发明授权

US08788862B1 Method and system for efficiently transitioning a communication circuit from a low-power state 有权
标题翻译：将通信电路从低功率状态有效地转变的方法和系统
公开(公告)号：US08788862B1
公开(公告)日：2014-07-22
申请号：US13175745
申请日：2011-07-01
申请人： Divya Vijayaraghavan , Chong H. Lee
发明人： Divya Vijayaraghavan , Chong H. Lee
IPC分类号： G06F1/32
CPC分类号： G06F1/3278 , Y02D10/157 , Y02D50/20
摘要： A method and system for efficiently transitioning a communication circuit from a low-power state are disclosed. A first device and second device in a low-power state may be transitioned to an active state to enable the transmission of data over a communication link, where energy consumption of one or more components of the first and/or second devices may be reduced in the low-power state. The transition may be initiated by the first device responsive to a signal and/or an expiration of a timer. Responsive thereto, a scrambler of the first device may be temporarily bypassed to accelerate achieving block lock at the second device, thereby enabling the system to more quickly transition from the low-power state to the active state.
摘要翻译：公开了一种将通信电路从低功率状态有效地转变的方法和系统。处于低功率状态的第一设备和第二设备可以被转换到活动状态，以便能够通过通信链路传输数据，其中可以减少第一和/或第二设备中的一个或多个组件的能量消耗低功耗状态。第一设备可以响应于信号和/或定时器的期满而启动转换。响应于此，第一设备的加扰器可能被暂时旁路以加速实现第二设备处的块锁定，从而使得系统能够更快地从低功率状态转换到活动状态。

12. 发明授权

US08732375B1 Multi-protocol configurable transceiver with independent channel-based PCS in an integrated circuit 有权
标题翻译：集成电路中具有独立通道的PCS的多协议可配置收发器
公开(公告)号：US08732375B1
公开(公告)日：2014-05-20
申请号：US12752641
申请日：2010-04-01
申请人： Divya Vijayaraghavan , Chong H. Lee
发明人： Divya Vijayaraghavan , Chong H. Lee
IPC分类号： G06F13/14
CPC分类号： G06F13/385
摘要： Structures and methods are disclosed relating to a multi-protocol transceiver including lane-based Physical Coding Sublayer (“PCS”) circuitry that is configurable to adapt to one of a plurality of communication protocols. Particular embodiments of the present invention include lane based configurable data paths through PCS transmit and receive circuitry.
摘要翻译：公开了涉及包括基于通道的物理编码子层（“PCS”）电路的多协议收发器的结构和方法，该电路可配置为适应多个通信协议之一。本发明的特定实施例包括通过PCS发送和接收电路的基于通道的可配置数据路径。

13. 发明申请

US20120307878A1 MULTI-PROTOCOL MULTIPLE-DATA-RATE AUTO-SPEED NEGOTIATION ARCHITECTURE FOR A DEVICE 有权
标题翻译：用于设备的多协议多数据速率自动调速架构
公开(公告)号：US20120307878A1
公开(公告)日：2012-12-06
申请号：US12860482
申请日：2010-08-20
申请人： Divya Vijayaraghavan , Chong H. Lee
发明人： Divya Vijayaraghavan , Chong H. Lee
IPC分类号： H04B3/46 , H04L27/00
CPC分类号： H04L5/1446 , H04L1/0002 , H04L1/0025
摘要： An interface for use in a local device includes a transmitter portion programmably configurable to at least three data rates, a receiver portion programmably configurable to those at least three data rates, and an automatic speed negotiation module operatively connected to the transmitter portion and the receiver portion to configure the transmitter portion and the receiver portion for communication with a remote device at a single data rate that is a best available one of those at least three data rates. The date rate can be adjusted by adjusting transmitter data path width and receiver data path width, adjusting a frequency of said transmitter data path and said receiver data path, and oversampling. Byte serialization or deserialization can be enabled or disabled to alter the width of the data, depending on the data rate, for transfer to/from the remainder of the local device.
摘要翻译：用于本地设备的接口包括可编程地配置为至少三个数据速率的发射机部分，可编程地配置为至少三个数据速率的接收机部分，以及可操作地连接到发射机部分和接收机部分的自动速度协商模块配置发射机部分和接收机部分，以与作为这些至少三个数据速率中最好的可用数据速率的单个数据速率与远程设备进行通信。可以通过调整发射机数据路径宽度和接收机数据路径宽度，调整所述发射机数据路径和所述接收机数据路径的频率以及过采样来调整日期速率。可以使能或禁用字节序列化或反序列化，以根据数据速率改变数据的宽度，以传输到/从本地设备的其余部分。

14. 发明授权

US08291255B1 CDR control architecture for robust low-latency exit from the power-saving mode of an embedded CDR in a programmable integrated circuit device 有权
标题翻译： CDR控制架构，用于强大的低延迟退出可编程集成电路设备中嵌入式CDR的省电模式
公开(公告)号：US08291255B1
公开(公告)日：2012-10-16
申请号：US13082162
申请日：2011-04-07
申请人： Divya Vijayaraghavan , Michael Menghui Zheng , Lana May Chan , Chong H. Lee
发明人： Divya Vijayaraghavan , Michael Menghui Zheng , Lana May Chan , Chong H. Lee
IPC分类号： G06F1/00 , H04L7/00 , H04L7/02
CPC分类号： G06F13/4295 , H04L7/0083 , H04L7/033 , H04L7/10 , Y02D10/14 , Y02D10/151
摘要： Clock data recovery (CDR) circuitry of a high-speed serial interface on a programmable integrated circuit device toggles, during the electrical idle period of the receiver of the interface, between its “lock-to-reference” (“LTR”) state and its normal “lock-to-data” (“LTD”) state. Whenever during this toggling mode the CDR circuitry toggles to the LTD state, it remains in that state for a predetermined interval and then returns to the LTR state, unless, while it is in the LTD state, it receives a signal from elsewhere in the receiver that data have been received and byte synchronization has occurred. The predetermined toggling interval preferably is long enough to obtain an LTR lock to minimize frequency drift, but short enough to avoid unnecessary delay in detection of the synchronization signal. Preferably, this interval is programmable by the user within limits determined by the characterization of the programmable device. Unreliable analog signal detection is thereby avoided.
摘要翻译：可编程集成电路设备上的高速串行接口的时钟数据恢复（CDR）电路在接口的接收机的电气空闲周期内切换其锁定参考（LTR）状态与其正常的锁定 - 数据（LTD）状态。无论何时在这个切换模式下，CDR电路切换到LTD状态，它保持在该状态一段预定的间隔，然后返回到LTR状态，除非在它处于LTD状态时，它接收来自接收器中其他地方的信号已经接收到数据并发生字节同步。预定的切换间隔优选地足够长以获得LTR锁定以使频率漂移最小化，但足够短以避免对同步信号的检测的不必要的延迟。优选地，该间隔可由用户在由可编程设备的表征确定的限度内编程。从而避免了不可靠的模拟信号检测。

15. 发明授权

US07684477B1 Multi-protocol low latency automatic speed negotiation architecture for an embedded high speed serial interface in a programmable logic device 有权
标题翻译：用于可编程逻辑器件中嵌入式高速串行接口的多协议低延迟自动速度协商架构
公开(公告)号：US07684477B1
公开(公告)日：2010-03-23
申请号：US11490406
申请日：2006-07-19
申请人： Divya Vijayaraghavan , Chong H. Lee
发明人： Divya Vijayaraghavan , Chong H. Lee
IPC分类号： H04B3/46
CPC分类号： H04L1/0002
摘要： A serial interface for a programmable logic device includes receiver and transmitter portions, and an automatic speed negotiation module to adjust the data rates of both portions. The speed adjustment may be accomplished by adjusting the widths of the data paths in both portions. The speed adjustment occurs on receipt of a control signal generated elsewhere on the programmable logic device, or generated by the module. One reason for generating the control signal is the detection of data errors in the received data, or the detection of a delimiter pattern in the received data signifying that a remote device is about to change its data rate.Similarly, before changing its data rate, the module may insert a delimiter in the data in the transmitter portion. After receipt or transmission of a delimiter pattern, the module may wait for a predetermined delay period to elapse before changing the data rate.
摘要翻译：用于可编程逻辑器件的串行接口包括接收器和发送器部分，以及用于调整两部分的数据速率的自动速度协商模块。速度调整可以通过调整两部分中数据路径的宽度来实现。速度调整发生在接收到可编程逻辑器件其他地方生成的或由模块生成的控制信号。产生控制信号的一个原因是检测接收到的数据中的数据错误，或者检测到接收到的数据中的定界符模式，这意味着远程设备即将改变其数据速率。类似地，在改变其数据速率之前，模块可以在发射机部分的数据中插入定界符。在接收或发送分隔符模式之后，模块可以在改变数据速率之前等待预定的延迟时间段。

16. 发明授权

US07627806B1 Integrated hard-wired or partly hard-wired CRC generation and/or checking architecture for a physical coding sublayer in a programmable logic device 有权
标题翻译：用于可编程逻辑器件中的物理编码子层的集成硬连线或部分硬连线CRC生成和/或检查架构
公开(公告)号：US07627806B1
公开(公告)日：2009-12-01
申请号：US11436463
申请日：2006-05-17
申请人： Divya Vijayaraghavan , Michael Menghui Zheng , Chong H. Lee , Ning Xue , Tam Nguyen
发明人： Divya Vijayaraghavan , Michael Menghui Zheng , Chong H. Lee , Ning Xue , Tam Nguyen
IPC分类号： H03M13/09
CPC分类号： H04L1/0052 , H03M13/09 , H03M13/6516 , H04L1/0061
摘要： A programmable logic integrated circuit device (“PLD”) includes high-speed serial interface (“HSSI”) circuitry that is at least partly hard-wired to perform at least some functional aspects of the HSSI operations. Cyclic redundancy check (CRC) generation and/or checking circuitry is now included in this HSSI circuitry, and again, this CRC circuitry is at least partly hard-wired to perform at least some functional aspects of its operations(s).
摘要翻译：可编程逻辑集成电路器件（“PLD”）包括至少部分硬接线以执行HSSI操作的至少一些功能方面的高速串行接口（“HSSI”）电路。循环冗余校验（CRC）生成和/或检查电路现在包括在该HSSI电路中，并且再次，该CRC电路至少部分地硬接线以执行其操作的至少一些功能方面。

17. 发明授权

US07724598B1 Megafunction block and interface 有权
标题翻译：宏功能块和接口
公开(公告)号：US07724598B1
公开(公告)日：2010-05-25
申请号：US11737654
申请日：2007-04-19
申请人： Vinson Chan , Chong H. Lee , Binh Ton , Thiagaraja Gopalsamy , Marcel A. LeBlanc , Neville Carvalho
发明人： Vinson Chan , Chong H. Lee , Binh Ton , Thiagaraja Gopalsamy , Marcel A. LeBlanc , Neville Carvalho
IPC分类号： G11C7/00
CPC分类号： G06F12/0292 , G06F12/0623 , G06F2212/1048
摘要： A megafunction block is provided that includes a serial interface enabling a user to specify settings of a configurable block of a programmable logic device. The megafunction block includes a register array having the capability of translating address information into actual addresses for a memory of the configurable block. Thus, as future configurations/standards are developed that a programmable logic device with the megafunction block will interfaces with, the settings for interfacing with the standards may be added to the register array. Consequently, the pin count will not need to increase as the megafunction block is scalable through the register map. Control logic verifies that the translated address is a valid address and the control logic will generate a selection signal based on whether a read or write operation is to be performed.
摘要翻译：提供了一种宏功能块，其包括使得用户能够指定可编程逻辑器件的可配置块的设置的串行接口。宏功能块包括具有将地址信息转换成可配置块的存储器的实际地址的能力的寄存器阵列。因此，随着具有宏功能块的可编程逻辑器件将与之相接的未来配置/标准被开发，用于与标准接口的设置可被添加到寄存器阵列中。因此，引脚数不需要增加，因为宏功能块可通过寄存器映射进行扩展。控制逻辑验证翻译的地址是否是有效地址，并且控制逻辑将基于是执行读操作还是写操作来生成选择信号。

18. 发明授权

US06970117B1 Byte alignment for serial data receiver 失效
标题翻译：串行数据接收器的字节对齐
公开(公告)号：US06970117B1
公开(公告)日：2005-11-29
申请号：US10789406
申请日：2004-02-26
申请人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
发明人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
IPC分类号： H03M9/00 , H04L7/02
CPC分类号： H04L7/0054 , H03M9/00
摘要： A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.
摘要翻译：用于可编程逻辑器件的串行数据接口包括使用恢复的时钟信号或相位对准的接收时钟信号对接收的串行数据的多个信道反串行的接收器。字节边界最初可以任意分配，反序列化信号被发送到可编程逻辑器件的可编程逻辑核心。内核中的可编程逻辑基于标准（包括任何用户定义的参数）来监视每个通道上的字节边界，编程到逻辑中。如果检测到边界未对准，则在该接口的该通道上将信号从核心发送到位滑动电路以调整边界。信号可以指示位滑动电路将边界调整校正对准所需的位数。或者，位打滑电路可以迭代地操作，每个周期将边界调整一个位，直到信号停止指示未对准。

19. 发明授权

US07984209B1 Data interface methods and circuitry with reduced latency 有权
标题翻译：具有降低延迟的数据接口方法和电路
公开(公告)号：US07984209B1
公开(公告)日：2011-07-19
申请号：US11638150
申请日：2006-12-12
申请人： Vinson Chan , Michael Menghui Zheng , Chong H. Lee
发明人： Vinson Chan , Michael Menghui Zheng , Chong H. Lee
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F5/12 , G06F2205/126
摘要： Interface circuitry that is used to interface data between two different clock regimes that may have somewhat different speeds includes the ability to determine which of the clock regimes is faster. Depending on which clock regime is found to be faster, the baseline (nominal difference between data write and data read addresses of a FIFO memory in the interface circuitry) is shifted (i.e., toward the full or empty condition of the FIFO, as is appropriate for which of the clock regimes has been found to be faster). Adjustments may also be made to the threshold(s) used for such purposes as character insertion/deletion and overflow/underflow indication. This technique may allow use of a smaller FIFO and reduce latency of the interface circuitry.
摘要翻译：用于在可能具有一些不同速度的两种不同时钟制式之间对数据进行接口的接口电路包括确定哪个时钟方案更快的能力。根据哪个时钟状态被发现更快，基线（数据写入和接口电路中的FIFO存储器的数据读取地址之间的标称差）被移位（即，朝向FIFO的满或空状态，如适用的那样）为什么时钟制度被发现是更快）。还可以对用于诸如字符插入/删除和溢出/下溢指示的目的的阈值进行调整。该技术可以允许使用较小的FIFO并减少接口电路的延迟。

20. 发明授权

US07046174B1 Byte alignment for serial data receiver 有权
标题翻译：串行数据接收器的字节对齐
公开(公告)号：US07046174B1
公开(公告)日：2006-05-16
申请号：US11147757
申请日：2005-06-07
申请人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
发明人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , H03K5/135 , H04L7/0331
摘要： A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.
摘要翻译：用于可编程逻辑器件的串行数据接口包括使用恢复的时钟信号或相位对准的接收时钟信号对接收的串行数据的多个信道反串行的接收器。字节边界最初可以任意分配，反序列化信号被发送到可编程逻辑器件的可编程逻辑核心。内核中的可编程逻辑基于标准（包括任何用户定义的参数）来监视每个通道上的字节边界，编程到逻辑中。如果检测到边界未对准，则在该接口的该通道上将信号从核心发送到位滑动电路以调整边界。信号可以指示位滑动电路将边界调整校正对准所需的位数。或者，位打滑电路可以迭代地操作，每个周期将边界调整一个位，直到信号停止指示未对准。

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