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11. 发明授权

US4466013A Tapped integrated resistor 失效
标题翻译：开关集成电阻
公开(公告)号：US4466013A
公开(公告)日：1984-08-14
申请号：US525350
申请日：1983-08-22
申请人： Rudy J. van de Plassche , Eise C. Dijkmans
发明人： Rudy J. van de Plassche , Eise C. Dijkmans
IPC分类号： H01L27/04 , H01L21/822 , H01L27/08 , H01L29/8605 , H01L27/02
CPC分类号： H01L27/0802 , H01L29/8605
摘要： The invention relates to an integrated resistor formed in an epitaxial layer and provided with at least one tap. In order to reduce field effect action between the resistor and the epitaxial layer, the voltage on the two ends of the epitaxial layer underneath the resistor tracks the voltage on the two ends of the resistor. Moreover, the epitaxial layer is short-circuited by means of buried layers at the locations where the resistance layer also exhibits a short-circuit, such as underneath the contact area of the tap.
摘要翻译：本发明涉及一种形成在外延层中并具有至少一个分接头的集成电阻器。为了减小电阻和外延层之间的场效应，电阻下方的外延层两端的电压跟踪电阻两端的电压。此外，外延层通过掩埋层在电阻层也表现出短路的位置（例如在接头的接触区域下方）短路。

12. 发明授权

US4290025A Amplifier arrangement with variable gain factor 失效
标题翻译：具有可变增益系数的放大器布置
公开(公告)号：US4290025A
公开(公告)日：1981-09-15
申请号：US15547
申请日：1979-02-26
申请人： Rudy J. van de Plassche
发明人： Rudy J. van de Plassche
IPC分类号： H03G3/12 , H03G1/00 , H03G3/00 , H03F3/45 , H03G3/30
CPC分类号： H03G1/0017 , H03G1/0023 , H03G3/00
摘要： An amplifier arrangement with a variable gain factor comprising a first and a second emitter-coupled transistor and a third and a fourth emitter-coupled transistor. The collector electrodes of the first and third transistor are coupled to an output of the amplifier arrangement. Between the interconnected base electrodes of the first and the fourth transistor and the interconnected base electrodes of the second and the third transistor a control signal can be applied. A signal current is applied to the interconnected emitter electrodes of the first and the second transistor and to the interconnected emitter electrodes of the third and the fourth transistor by means of a first and a second voltage-current converter, respectively, at least one of the two converters comprising a signal input and both converters having negative feedback to the output of the amplifier arrangement.
摘要翻译：具有可变增益因子的放大器装置，包括第一和第二发射极耦合晶体管以及第三和第四发射极耦合晶体管。第一和第三晶体管的集电极耦合到放大器装置的输出端。在第一和第四晶体管的互连基极与第二晶体管和第三晶体管的互连基极之间可以施加控制信号。分别通过第一和第二电压 - 电流转换器将信号电流施加到第一和第二晶体管的互连发射极电极和第三和第四晶体管的互连的发射极，至少一个两个转换器包括信号输入和两个转换器，其具有对放大器装置的输出的负反馈。

13. 发明授权

US06324233B1 Reception of modulated carriers having asymmetrical sidebands 失效
标题翻译：接收具有不对称边带的调制载波
公开(公告)号：US06324233B1
公开(公告)日：2001-11-27
申请号：US09120625
申请日：1998-07-22
申请人： Adrianus Sempel , Eduard F. Stikvoort , Alphons A. M. L. Bruekers , Adrianus W. M. van den Enden , Rudy J. van de Plassche , Gerardus C. M. Gielis
发明人： Adrianus Sempel , Eduard F. Stikvoort , Alphons A. M. L. Bruekers , Adrianus W. M. van den Enden , Rudy J. van de Plassche , Gerardus C. M. Gielis
IPC分类号： H04B1400
CPC分类号： H04N5/4446 , H04B1/1036 , H04B1/26 , H04N5/4401 , H04N5/46
摘要： In a receiver for receiving a modulated carrier (MC) having asymmetrical sidebands (USB,LSB), for example, a TV signal, a synchronous demodulator (SDEM) derives a vectorial baseband signal (VB) from the modulated carrier (MC). A filter (FILT) filters the vectorial baseband signal so as to compensate for the sideband asymmetry, for example, by means of a Nyquist slope. Thus, the sideband asymmetry is compensated at baseband frequencies, rather than at an intermediate frequency, which allows a better quality of reception.
摘要翻译：在用于接收具有不对称边带（USB，LSB）的例如TV信号的调制载波（MC）的接收机中，同步解调器（SDEM）从调制载波（MC）导出矢量基带信号（VB）。滤波器（FILT）对矢量基带信号进行滤波，以便例如通过奈奎斯特斜率补偿边带不对称性。因此，边带不对称性在基带频率而不是中频处得到补偿，这允许更好的接收质量。

14. 发明授权

US5557275A Error-tolerant binary encoder 失效
标题翻译：容错二进制编码器
公开(公告)号：US5557275A
公开(公告)日：1996-09-17
申请号：US269812
申请日：1994-06-30
申请人： Christinus J. van Valburg , Rudy J. van de Plassche
发明人： Christinus J. van Valburg , Rudy J. van de Plassche
IPC分类号： H03M1/12 , H03M7/00 , H03M7/16 , H03M1/36
CPC分类号： H03M7/165
摘要： Encoder for the conversion of a signal of thermometric or cyclic type including a set of n Exclusive OR gates (X1, Xi, . . . , Xn) and an encoding matrix with n rows (1 . . . n) and a plurality of pairs of columns for a differential output of one bit of the binary signal, a matrix in which a row/column coupling is produced by a transistor (T). A pair of pseudo-columns of order zero is coupled to the rows in a way comparable to the coupling of the pair of columns of order 1, but by applying a cyclic shift in respect of the rank of the rows (rows of rank i of the pseudo-columns of order zero, coupled like the rows of rank (i modulo n)+1 of the columns of order 1). The bit of order zero [Bo] is obtained at the output of an additional Exclusive OR gate the inputs of which respectively receive the logic signal [Bo*] output by the pair of pseudo-columns of order zero, and the logic signal [B1] output by the pair of columns of order one.
摘要翻译：用于转换包括一组n个异或门（X1，Xi，...，Xn）的温度测量或循环类型的信号的编码器和具有n行（...，）和多对的编码矩阵用于二进制信号的一位的差分输出的列，其中由晶体管（T）产生行/列耦合的矩阵。顺序为零的一对伪列以与订单1的列对的耦合相当的方式耦合到行，但是通过对行的等级（行的等级i应用循环移位）顺序为零的伪列，与秩1的列（i模n）+ +1的行耦合。在其输入分别接收由零对的一对伪列输出的逻辑信号[Bo *]和逻辑信号[B1（B））的附加异或门的输出处获得阶数零[Bo]的位 ]由一对订单列输出。

15. 发明授权

US5189422A Analog-to-digital converter with delay correction 失效
标题翻译：具有延迟校正的模数转数转换器
公开(公告)号：US5189422A
公开(公告)日：1993-02-23
申请号：US788410
申请日：1991-11-06
申请人： Rudy J. van de Plassche , Petrus G. M. Baltus
发明人： Rudy J. van de Plassche , Petrus G. M. Baltus
IPC分类号： H03M1/10 , H03M1/06 , H03M1/36
CPC分类号： H03M1/0602 , H03M1/365
摘要： Analog-to-digital converter operating in parallel having an analog signal input and a number of digital signal outputs, comprising a plurality of comparators having each two inputs and one output, one input being connected to an impedance network for supplying this one input with its own predetermined reference voltage, and the second input being connected to the analog signal input for receiving an analog input signal to be converted, so that each of the comparators processes a predetermined input signal portion. The comparator outputs are coupled to corresponding digital signal outputs, while delay elements are inserted between the comparator outputs and the corresponding digital signal outputs for causing a delay to occur related to the steepness of the slope of the input signal portion of the relevant comparator.

16. 发明授权

US4517525A Balancing compensation in differential amplifiers with a single-ended drive 失效
标题翻译：使用单端驱动器平衡补偿差分放大器
公开(公告)号：US4517525A
公开(公告)日：1985-05-14
申请号：US445334
申请日：1982-11-29
申请人： Eise C. Dijkmans , Rudy J. van de Plassche
发明人： Eise C. Dijkmans , Rudy J. van de Plassche
IPC分类号： H03F1/32 , H03F1/34 , H03F1/48 , H03F3/19 , H03F3/45 , H03F1/14
CPC分类号： H03F3/45071 , H03F1/48
摘要： A differential amplifier with single-ended drive includes a balancing impedance (20) coupled between the base of the transistor (3) connected to the signal input (1) and the common point (9) of the two emitters of the transistors (3,4), which form a differential pair. The capacitance value of the capacitor (20) is substantially equal to the capacitance value of the stray capacitance (19) of the collector-substrate junction of a transistor (10) which forms a current source. This provides a symmetry of the capacitances between the input (1) and the common point (9) and between the common point (9) and ground via the transistor (10). This results in an improved balance in the output signals at the output terminals (5,6) and a flat frequency response of the differential amplifier for higher frequencies.
摘要翻译：具有单端驱动的差分放大器包括耦合在连接到信号输入端（1）的晶体管（3）的基极和晶体管（3）的两个发射极的公共点（9）之间的平衡阻抗（20） 4），其形成差分对。电容器（20）的电容值基本上等于形成电流源的晶体管（10）的集电极 - 衬底结的杂散电容（19）的电容值。这提供了通过晶体管（10）在输入（1）和公共点（9）之间以及公共点（9）和接地之间的电容的对称性。这导致在输出端子（5,6）处的输出信号的平衡得到改善，以及用于较高频率的差分放大器的平坦的频率响应。

17. 发明授权

US4325054A Folding circuit for an analog-to-digital converter 失效
标题翻译：用于模数转换器的折叠电路
公开(公告)号：US4325054A
公开(公告)日：1982-04-13
申请号：US62253
申请日：1979-07-30
申请人： Rudy J. van de Plassche
发明人： Rudy J. van de Plassche
IPC分类号： G06G7/28 , H03K4/06 , H03K6/00 , H03M1/14 , H03M1/34 , H03M1/36 , H03M1/44 , H03K13/02
CPC分类号： H03K6/00 , G06G7/28 , H03K4/06 , H03M1/14 , H03M1/34 , H03M1/365 , H03M1/368
摘要： In a folding circuit of an analog-to-digital converter a chain of emitters of transistors which are interconnected by threshold elements and fed by direct current sources are used to reduce the distortion. The circuit is controlled by a current source which produces the input signal.
摘要翻译：在模数转换器的折叠电路中，使用由阈值元件互连并由直流电源馈送的晶体管的发射极链来减少失真。该电路由产生输入信号的电流源控制。

18. 发明授权

US4280089A Automatic incrementing attenuation arrangement 失效
标题翻译：自动递增衰减布置
公开(公告)号：US4280089A
公开(公告)日：1981-07-21
申请号：US088734
申请日：1979-10-26
申请人： Rudy J. van de Plassche , Eise C. Dijkmans
发明人： Rudy J. van de Plassche , Eise C. Dijkmans
IPC分类号： G01R1/20 , H03G1/00 , H03H7/24 , H03H7/25 , H03H11/24 , G05F3/08
CPC分类号： G01R1/203 , H03G1/0088 , H03H11/24 , H03H7/24 , H03H7/25
摘要： Attenuation arrangement comprising a step attenuator arranged in cascade with a controllable voltage divider via first and second voltage terminals, the step attenuator comprising a series arrangement of attenuation elements for dividing a voltage applied across said series arrangement into a plurality of voltage increments, which voltage increments are individually switchable between the two voltage terminals for varying the output voltage of the controllable voltage divider for the voltage range of the relevant voltage element, the direction of the polarity of the voltage between the two voltage terminals changing at a switch-over from one voltage increment to an adjacent voltage increment.
摘要翻译：衰减布置包括通过第一和第二电压端子与可控分压器级联布置的步进衰减器，所述阶梯衰减器包括用于将施加在所述串联装置上的电压分成多个电压增量的衰减元件的串联布置，所述电压增量可以在两个电压端子之间单独切换，用于在相关电压元件的电压范围内改变可控分压器的输出电压，两个电压端子之间的电压的极性方向从一个电压切换增加到相邻的电压增量。

19. 发明授权

US4897656A Complementary voltage interpolation circuit with transmission delay compensation 失效
标题翻译：具有传输延迟补偿的互补电压内插电路
公开(公告)号：US4897656A
公开(公告)日：1990-01-30
申请号：US127867
申请日：1987-12-02
申请人： Rudy J. van de Plassche , Peter G. Baltus
发明人： Rudy J. van de Plassche , Peter G. Baltus
IPC分类号： H03M1/12 , G06G7/30 , H03H17/00 , H03M1/14 , H03M1/20 , H03M1/36
CPC分类号： H03M1/205 , G06G7/30 , H03M1/141
摘要： The invention centers around a system for interpolating between multiple pairs of complementary main signals to generate further pairs of complementary signals. An input circuit (10) supplies the main signals. The interpolation is a two-step operation. The first step is done with two strings (S and S.sub.N) of impedance elements (R.sub.0 -R.sub.N-1 and R.sub.N0 -R.sub.NN-1). Each pair of main signals is supplied to a corresponding pair of nodes along the strings. Interpolated signals are taken from other pairs of corresponding nodes along the strings. In the second interpolation stage, a delay network (D) formed with additional impedance elements (R.sub.D0 -R.sub.DN-1 and R.sub.DN0 -R.sub.DNN-1) compensates for transmission delays through the impedance elements that make up the strings.
摘要翻译：本发明围绕用于在多对互补主信号之间进行内插以产生另外的互补信号对的系统。输入电路（10）提供主信号。插值是一个两步操作。第一步是用阻抗元件（R0-RN-1和RN0-RNN-1）的两个串（S和SN）完成。每对主信号被提供给沿着串的一对相应的节点。内插信号是沿着串的其他对相应节点取的。在第二插值阶段，形成有附加阻抗元件（RD0-RDN-1和RDN0-RDNN-1）的延迟网络（D）通过构成串的阻抗元件来补偿传输延迟。

20. 发明授权

US4574270A Analog-to-digital current converter 失效
标题翻译：模数转换器
公开(公告)号：US4574270A
公开(公告)日：1986-03-04
申请号：US498617
申请日：1983-05-27
申请人： Rudy J. van de Plassche
发明人： Rudy J. van de Plassche
IPC分类号： H03M1/20 , H03M1/44 , H03K13/09
CPC分类号： H03M1/445
摘要： An analog-to-digital current converter comprises n series-connected stages which each provide one bit of the Gray code. For this purpose each stage m derives a difference current from the input current (i.sub.i/m), which is the output current (i.sub.0/m-1) of the preceding stage, and a reference current (I/2.sup.m-1) from a source (6). This difference current flows to the output (a) of the stage m (i.sub.o/m) either via a diode (3) or via a current (11) depending on its direction. Conduction of the diode (3) or of the current-mirror circuit (11) is used for the bit indication.This results in a very fast analog-to-digital converter with few components and a high accuracy and resolution.
摘要翻译：模数转换器包括n个串联连接的级，每个级提供Gray码的一位。为此，每个级m从与前一级的输出电流（i0 / m-1）和来自a的输入电流（i / 2m-1）的输入电流（I / 2m-1）来源（6）。该差电流通过二极管（3）或根据其方向通过电流（11）流到级m（io / m）的输出（a）。二极管（3）或电流镜电路（11）的导通用于位指示。这导致具有很少组件和高精度和高分辨率的非常快的模数转换器。

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