专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20190044529A1 Method and apparatus for preventing inherent error propagation of successive approximation register analog-to-digital converter through digital correction 审中-公开
公开(公告)号：US20190044529A1
公开(公告)日：2019-02-07
申请号：US16001991
申请日：2018-06-07
申请人： Intel Corporation
发明人： Mario Traeber
IPC分类号： H03M1/10 , H03M1/06
CPC分类号： H03M1/1071 , H03M1/0602 , H03M1/10 , H03M1/462
摘要： A method and apparatus for preventing inherent error propagation of a successive approximation register (SAR)-based analog-to-digital converter (ADC) through digital correction. A sample-and-hold circuit captures an input analog signal and generates a hold sample of the input analog signal. A digital-to-analog converter (DAC) generates an iterative sample corresponding to a digital code for each iteration. A comparator compares the hold sample and the iterative sample and generates a decision signal based on the comparison. A successive approximation register updates the digital code for each iteration based on the decision signal and supplies the updated digital code to the DAC. The SAR ADC includes an error detection circuit to detect an error condition. A controller ceases iteration operation if the error condition is detected and outputs the current digital code as a result.

2. 发明授权

US09954672B1 Digital signal input circuit 有权
公开(公告)号：US09954672B1
公开(公告)日：2018-04-24
申请号：US15727727
申请日：2017-10-09
申请人： Huawei Technologies Co., Ltd.
发明人： Jianzhao Li
IPC分类号： H03M3/00 , G02B27/00 , H04L7/00 , H03K17/18 , G01R15/14 , G01R19/25 , H03M1/06 , H04B10/80 , H03K17/78
CPC分类号： H04L7/0029 , G01R15/144 , G01R19/2506 , H03K17/18 , H03K17/78 , H03K19/017536 , H03M1/0602 , H04B10/802 , H05B33/0812 , H05B37/0254
摘要： A digital signal input circuit including an isolating circuit and a voltage determining circuit is presented, where a first port of an input end of the isolating circuit receives a digital signal, an output end of the isolating circuit outputs the digital signal, and when the isolating circuit is open, the isolating circuit is configured to output a first level, or when the isolating circuit is closed, the isolating circuit is configured to output a second level; and the voltage determining circuit is configured to determine, according to a level of the digital signal, whether the isolating circuit is open or closed. According to the digital signal input circuit, the voltage determining circuit determines a level of a digital signal, thereby correctness of digital signal level conversion is increased.

3. 发明授权

US09900016B1 Compensation of non-linearity at digital to analog converters 有权
公开(公告)号：US09900016B1
公开(公告)日：2018-02-20
申请号：US15588065
申请日：2017-05-05
申请人： INTEL IP CORPORATION
发明人： Stefan Trampitsch , Daniel Gruber
IPC分类号： H03M1/06 , H03M1/66
CPC分类号： H03M1/0602 , H03M1/0845 , H03M1/66
摘要： An apparatus for compensating for nonlinearities in a DAC caused by variabilities of a power supply. The apparatus may include a power supply, a processing component, and a front-end circuit. The power supply may generate power, where the power includes variabilities in a power. The processing component may generate a digital signal. The front-end circuit may be operatively coupled to the power supply and the processing component. The front-end circuit may receive the power from the power supply, identify the nonlinearities in the power, receive the digital signal from the processing component, and adjust the digital signal for the nonlinearities to obtain an input signal to send to a digital to analog converter (DAC).

4. 发明授权

US09722620B1 Non-linearity cancellation in a dual-path ADC 有权
公开(公告)号：US09722620B1
公开(公告)日：2017-08-01
申请号：US15338818
申请日：2016-10-31
申请人： Cirrus Logic, Inc.
发明人： Ramin Zanbaghi , Yousof Mortazavi , John L. Melanson , Aaron Brennan
IPC分类号： H03M1/06 , G10L19/00
CPC分类号： H03M1/0602 , G10L19/00 , H03M1/1004 , H03M1/1038 , H03M1/1042 , H03M1/188 , H03M1/60
摘要： The overall performance of a dual-path ADC system may be improved by using a VCO-based ADC for small-amplitude signals and employing non-linear cancelation to remove nonlinearities in signals output by the VCO-based ADC. In particular, VCO-based dual-path ADC systems of this disclosure may be configured to receive a first digital signal from a first ADC and a second digital signal from a second ADC, wherein the second digital signal is more non-linear than the first digital signal. The dual-path systems may also be configured to determine one or more non-linear coefficients of the second digital signal based, at least in part, on processing of the first and second digital signals. The dual-path systems may be further configured to modify the second digital signal based, at least in part, on the determined one or more non-linear coefficients to generate a more linear second digital signal.

5. 发明授权

US09621181B2 Digital to analog converter with output impedance compensation 有权
公开(公告)号：US09621181B2
公开(公告)日：2017-04-11
申请号：US14676227
申请日：2015-04-01
申请人： NATIONAL CHENG KUNG UNIVERSITY
发明人： Tai-Haur Kuo , Hung-Yi Huang , Wei-Cheng Hong
IPC分类号： H03M1/06 , H03M1/80 , H03M1/66
CPC分类号： H03M1/808 , H03M1/0602 , H03M1/0612 , H03M1/664 , H03M1/747
摘要： A digital to analog converter with output impedance compensation has an encoding unit, a current cell array, a summing unit and a compensation unit. The compensation unit is connected to output terminals of the DAC and provides a nonlinear impedance to compensate an original output impedance of the DAC. With the compensated output impedance, the SFDR performance and the linearity of the DAC are improved to obtain a superior input-to-output transfer curve.

6. 发明申请

US20140266836A1 POLARITY COMPENSATING DUAL-STRING DIGITAL-TO-ANALOG CONVERTERS (DACs), AND RELATED CIRCUITS, SYSTEMS, AND METHODS 有权
标题翻译：极性补偿双字模数转换器（DAC）及相关电路，系统和方法
公开(公告)号：US20140266836A1
公开(公告)日：2014-09-18
申请号：US13834184
申请日：2013-03-15
申请人： QUALCOMM INCORPORATED
发明人： Burt L. Price , Dhaval R. Shah , Yeshwant Nagaraj Kolla
IPC分类号： H03M1/68
CPC分类号： H03M1/68 , H03M1/0602 , H03M1/682 , H03M1/765
摘要： Polarity compensating dual-string digital-to-analog converters (DACs), and related circuits, systems, and methods are disclosed. In embodiments disclosed herein, a secondary voltage divider of a dual-string DAC includes a switch logic unit. The switch logic unit is configured to compensate for polarity changes in the dual-string DAC to maintain monotonicity. Monotonicity means an output voltage of a DAC either increases or stays constant for monotonically increasing functions or either decreases or stays constant for monotonically decreasing functions given an incremental change in a DAC input code. The switch logic unit is configured to compensate for polarity changes in the input voltage from the primary voltage divider to the secondary resistor string. The switch logic unit is configured to select a secondary switch among the plurality of secondary switches in a secondary voltage divider, to divide an input voltage based on a polarity indicator and a DAC input code, to maintain monotonicity.
摘要翻译：公开了极性补偿双串数/模转换器（DAC）以及相关电路，系统和方法。在本文公开的实施例中，双串DAC的次级分压器包括开关逻辑单元。开关逻辑单元被配置为补偿双串DAC中的极性变化以保持单调性。单调性意味着DAC的输出电压对于单调增加的功能而言增加或保持恒定，或者在给定DAC输入代码的增量变化时单调递减的函数减小或保持恒定。开关逻辑单元被配置为补偿从一次分压器到次级电阻器串的输入电压的极性变化。开关逻辑单元被配置为在次级分压器中的多个次级开关中选择次级开关，以基于极性指示器和DAC输入代码来分压输入电压，以保持单调性。

7. 发明授权

US08451158B2 Analog to digital converter with generalized beamformer 有权
标题翻译：具有广义波束形成器的模数转换器
公开(公告)号：US08451158B2
公开(公告)日：2013-05-28
申请号：US13174273
申请日：2011-06-30
申请人： Yu Liao , Hongwei Song
发明人： Yu Liao , Hongwei Song
IPC分类号： H03M1/12
CPC分类号： H03M1/0602 , H03M1/1215
摘要： Various embodiments of the present invention provide systems, apparatuses and methods for performing analog to digital conversion. For example, an analog to digital converter circuit is discussed that includes an analog input, a number of analog to digital converters and a generalized beamformer. The analog to digital converters are operable to receive the analog input and to yield a number of digital streams. Each of the analog to digital converters samples the analog input with different phase offsets. The generalized beamformer is operable to weight and combine the digital streams to yield a digital output.
摘要翻译：本发明的各种实施例提供了用于执行模数转换的系统，装置和方法。例如，讨论了包括模拟输入，多个模数转换器和广义波束形成器的模数转换器电路。模数转换器可操作以接收模拟输入并产生多个数字流。每个模数转换器对具有不同相位偏移的模拟输入进行采样。广义波束形成器可操作以加权并组合数字流以产生数字输出。

8. 发明申请

US20110169678A1 HIGH FIDELITY, RADIATION TOLERANT ANALOG-TO-DIGITAL CONVERTERS 有权
标题翻译：高可靠性，耐辐射模拟数字转换器
公开(公告)号：US20110169678A1
公开(公告)日：2011-07-14
申请号：US12778875
申请日：2010-05-12
申请人： Charles Chang-I Wang , Ivan Richard Linscott , Umran S. Inan
发明人： Charles Chang-I Wang , Ivan Richard Linscott , Umran S. Inan
IPC分类号： H03M1/66 , H03M1/12
CPC分类号： H03M1/0602 , H03M1/0827 , H03M1/1033 , H03M1/164
摘要： Techniques for an analog-to-digital converter (ADC) using pipeline architecture includes a linearization technique for a spurious-free dynamic range (SFDR) over 80 deciBels. In some embodiments, sampling rates exceed a megahertz. According to a second approach, a switched-capacitor circuit is configured for correct operation in a high radiation environment. In one embodiment, the combination yields high fidelity ADC (>88 deciBel SFDR) while sampling at 5 megahertz sampling rates and consuming
摘要翻译：使用流水线架构的模数转换器（ADC）的技术包括一个超过80比特的无杂散动态范围（SFDR）的线性化技术。在一些实施例中，采样速率超过兆赫兹。根据第二种方法，开关电容器电路被配置为在高辐射环境中正确操作。在一个实施例中，组合产生高保真ADC（> 88 deciBel SFDR），同时以5兆赫采样率采样并消耗<60毫瓦。此外，即使采用商业化的0.25-μmCMOS技术（1μm= 12-6米）制造，它在恶劣的辐射环境中保持这种性能。具体来说，所述性能通过最高测试的2兆拉德（Si）总剂量持续，并且ADC在升高的温度（131摄氏度）下显示没有闭锁，达到6300万电子伏特平方厘米/毫升的最高测试线性能量转移。）和电源（2.7伏，相对于2.5伏标称）。

9. 发明授权

US07423571B2 Resistor-string digital/analog converter circuit and semiconductor device including the same circuit 失效
标题翻译：电阻串数字/模拟转换电路和包含相同电路的半导体器件
公开(公告)号：US07423571B2
公开(公告)日：2008-09-09
申请号：US11515384
申请日：2006-09-05
申请人： Asami Saito , Satoshi Sakurai
发明人： Asami Saito , Satoshi Sakurai
IPC分类号： H03M1/68
CPC分类号： H03M1/0602 , H03M1/682 , H03M1/765
摘要： A resistor-string digital/analog converter circuit includes a plurality of resistors configured to divide a predetermined voltage, a plurality of MOS transistors configured to divide a voltage generated across one resistor of the plurality of resistors, a control circuit configured to control a connection between the one resistor and the plurality of MOS transistors so as to supply to the plurality of MOS transistors the voltage generated across the one resistor, and a gate potential generating circuit. The gate potential generating circuit generates a plurality of mutually different gate potentials and supplies the plurality of generated gate voltages, respectively, to a plurality of gates of the plurality of MOS transistors, so that the resistance values of MOS resistance of the plurality of MOS transistors are equal to each other.
摘要翻译：电阻串数字/模拟转换器电路包括被配置为分配预定电压的多个电阻器，多个MOS晶体管，被配置为分割在多个电阻器中的一个电阻器上产生的电压;控制电路，被配置为控制一个电阻器和多个MOS晶体管，以便向多个MOS晶体管提供跨过一个电阻器产生的电压以及栅极电位产生电路。栅极电位产生电路产生多个相互不同的栅极电位，并将多个产生的栅极电压分别提供给多个MOS晶体管的多个栅极，使得多个MOS晶体管的MOS电阻的电阻值彼此相等。

10. 发明授权

US07049872B2 Use of analog-valued floating-gate transistors to match the electrical characteristics of interleaved and pipelined circuits 有权
标题翻译：使用模拟值浮栅晶体管来匹配交错和流水线电路的电气特性
公开(公告)号：US07049872B2
公开(公告)日：2006-05-23
申请号：US10681577
申请日：2003-10-07
申请人： Christopher J. Diorio , Todd E. Humes , Michael Thomas
发明人： Christopher J. Diorio , Todd E. Humes , Michael Thomas
IPC分类号： H03H11/26
CPC分类号： G06F1/10 , G11C27/005 , G11C27/024 , H03K5/135 , H03K5/1502 , H03K5/2481 , H03K5/249 , H03K2005/00026 , H03K2005/00058 , H03K2005/00084 , H03M1/0602 , H03M1/1215 , H03M1/164 , H03M1/442
摘要： Methods of and apparatuses for matching the signal delay, clock timing, frequency response, gain, offset, and/or transfer function of signal pathways in electrical circuits such as, for example, time-interleaved and pipelined circuits using analog-valued floating-gate MOSFETs are disclosed. The methods and apparatuses disclosed are applicable to a variety of circuits, including but not limited to, sample-and-hold or track-and-hold circuits, quadrature mixers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), analog or digital filters, and amplifiers.
摘要翻译：用于使电路中的信号路径的信号延迟，时钟定时，频率响应，增益，偏移和/或传递函数匹配的方法和设备，例如使用模拟值浮动栅极的时间交织和流水线电路公开了MOSFET。所公开的方法和装置适用于各种电路，包括但不限于采样保持或跟踪保持电路，正交混频器，模数转换器（ADC），数模转换器转换器（DAC），模拟或数字滤波器和放大器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式