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11. 发明授权

US08324606B2 Resistance change type memory 有权
标题翻译：电阻变化型存储器
公开(公告)号：US08324606B2
公开(公告)日：2012-12-04
申请号：US12563470
申请日：2009-09-21
申请人： Takayuki Tsukamoto , Reika Ichihara , Hiroshi Kanno , Kenichi Murooka
发明人： Takayuki Tsukamoto , Reika Ichihara , Hiroshi Kanno , Kenichi Murooka
IPC分类号： H01L47/00
CPC分类号： G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C2213/72 , H01L27/101 , H01L27/2409 , H01L27/2481
摘要： A resistance change type memory of an aspect of the present invention including a first wiring configured to extend in a first direction, a second wiring configured to extend in a second direction crossing the first direction, a series circuit configured to connect to the first and second wirings, the series circuit including a non-ohmic element being more conductive in the first to second wiring direction than in the second to first direction and a resistance change type storage element in which data is stored according to a change of a resistance state, an energy supplying circuit configured to connect to the first wiring to supply energy to the first wiring, the energy being used to store the data in the resistance change type storage element, and a capacitance circuit configured to include a capacitive element and being connected to the second wiring.
摘要翻译：本发明的一个方面的电阻变化型存储器包括：构造成沿第一方向延伸的第一布线，沿与第一方向交叉的第二方向延伸的第二布线;串联电路，被配置为连接到第一和第二端布线，包括在第一至第二布线方向上比在第二至第一方向上更加导电的非欧姆元件的串联电路和根据电阻状态的变化存储数据的电阻变化型存储元件，能量供给电路，被配置为连接到所述第一布线以向所述第一布线供应能量，所述能量用于将所述数据存储在所述电阻变化型存储元件中;以及电容电路，被配置为包括电容元件并连接到所述第二布线接线。

12. 发明授权

US08320158B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08320158B2
公开(公告)日：2012-11-27
申请号：US12882685
申请日：2010-09-15
申请人： Hiroshi Kanno , Reika Ichihara , Takayuki Tsukamoto , Kenichi Murooka , Hirofumi Inoue
发明人： Hiroshi Kanno , Reika Ichihara , Takayuki Tsukamoto , Kenichi Murooka , Hirofumi Inoue
IPC分类号： G11C11/00
CPC分类号： G11C7/02 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0064 , G11C13/0097 , G11C2213/31 , G11C2213/71 , G11C2213/72
摘要： Nonvolatile semiconductor memory device of an embodiment includes: a memory cell array including a plurality of first and second lines intersecting each other and plural memory cells provided at intersections of the first and second lines and having data written and erased upon application of voltages of the same polarity; and a writing circuit configured to select first and second lines and supply a set or reset pulse to the memory cell through the selected first and second lines. In an erase operation, the writing circuit repeatedly supplies the reset pulse to a selected memory cell until data is erased, by increasing or decreasing voltage level and voltage application time of the reset pulse within a reset region. The reset region, or an aggregate of combinations of voltage level and voltage application time of the reset pulse, is a region where voltage level and voltage application time are negatively correlated.
摘要翻译：一个实施例的非易失性半导体存储器件包括：存储单元阵列，包括彼此相交的多个第一和第二线，以及设置在第一和第二线的交点处的多个存储单元，并且在施加相同的电压时写入和擦除数据极性; 以及写入电路，被配置为选择第一和第二行，并且通过所选择的第一和第二行向存储器单元提供置位或复位脉冲。在擦除操作中，写入电路通过增加或减小复位区域内的复位脉冲的电压电平和电压施加时间，将复位脉冲重复地提供给所选择的存储单元，直到数据被擦除。复位区域或复位脉冲的电压电平和电压施加时间的组合的总和是电压电平和电压施加时间呈负相关的区域。

13. 发明授权

US08134177B2 Switching element, semiconductor device and method of manufacturing the same 有权
标题翻译：开关元件，半导体器件及其制造方法
公开(公告)号：US08134177B2
公开(公告)日：2012-03-13
申请号：US11566937
申请日：2006-12-05
申请人： Kenichi Murooka
发明人： Kenichi Murooka
IPC分类号： H01L29/74
CPC分类号： H01L29/7613 , B82Y10/00 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/0665 , H01L29/0673 , H01L29/1029 , H01L29/125 , H01L29/127 , H01L29/42332 , H01L29/775 , H01L29/785 , Y10T29/49105
摘要： A switching element includes a first electrode having a first surface; a second electrode having a second surface which stands off from the first surface; and a channel region constituted by a plurality of unit channels, each unit channel having opposite ends thereof being in contact with the first electrode and the second electrode, and including fine particles which are aligned in lines in a first direction from the first surface of the first electrode to the second surface of the second electrode, and the unit channels being separated from one another in a second direction across the first direction.
摘要翻译：开关元件包括具有第一表面的第一电极; 第二电极，具有从第一表面脱离的第二表面; 以及由多个单位通道构成的通道区域，其相对端部的每个单位通道与所述第一电极和所述第二电极接触，并且包括从所述第一电极和所述第二电极的第一表面沿着第一方向以直线排列的细小颗粒第一电极到第二电极的第二表面，并且单位通道在第一方向上沿第二方向彼此分离。

14. 发明申请

US20110205783A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110205783A1
公开(公告)日：2011-08-25
申请号：US13001147
申请日：2009-06-11
申请人： Kenichi Murooka
发明人： Kenichi Murooka
IPC分类号： G11C11/00 , G11C7/00 , G11C7/06
CPC分类号： G11C13/00 , G11C13/0004 , G11C13/0011 , G11C13/0023 , G11C13/004 , G11C2013/0054 , G11C2213/71 , H01L27/115 , H01L27/2463 , H01L27/2481 , H01L45/08 , H01L45/085 , H01L45/10 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1625 , H01L45/1675
摘要： A semiconductor memory device comprises a plurality of first row lines arranged in parallel; a plurality of column lines intersecting the first row lines; a plurality of storage elements arranged at intersections of the first row lines and the column lines; a plurality of second row lines arranged in parallel with the first row lines, from positions opposite to the first row lines via the column lines to a certain portion of the column line, and capacitively coupled with the column lines; and a sense amplifier including a field effect transistor having a lower layer control electrode composed of the certain portion of the column line, and an upper layer control electrode composed of the second row line capacitively coupled in the upper layer with the certain portion of the column line.
摘要翻译：半导体存储器件包括并行布置的多个第一行线; 与第一行线相交的多个列线; 多个存储元件，布置在第一行线和列线的交点处; 多条第二行线，与第一行线平行排列，从与第一列行相对的位置经由列线排列到列线的某一部分，并与列线电容耦合; 以及包括具有由列线的特定部分组成的下层控制电极的场效应晶体管的读出放大器，以及由上层的电容耦合到列的一定部分的第二行线构成的上层控制电极线。

15. 发明申请

US20100238704A1 SEMICONDUCTOR MEMORY DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF SCREENING THE SAME 有权
标题翻译：半导体存储器件，其制造方法及其筛选方法
公开(公告)号：US20100238704A1
公开(公告)日：2010-09-23
申请号：US12618122
申请日：2009-11-13
申请人： Masanori Komura , Mitsuru Sato , Kenichi Murooka , Motoya Kishida
发明人： Masanori Komura , Mitsuru Sato , Kenichi Murooka , Motoya Kishida
IPC分类号： G11C11/00 , H01L45/00 , H01L21/02 , H01L29/12 , G11C29/00
CPC分类号： G11C13/0007 , G11C13/0004 , G11C13/004 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1616 , H01L45/1625 , H01L45/1675
摘要： A memory cell comprises a variable resistance film; a first conductive film having one surface contacted with one surface of the variable resistance film; and a second conductive film having one surface contacted with another surface of the variable resistance film. A width of the first conductive film or the second conductive film in a direction orthogonal to a direction that a current flows in the first conductive film or the second conductive film is smaller than a width of the variable resistance film in a direction orthogonal to a direction that a current flows in the variable resistance film. The width of the first conductive film and the second conductive film is smaller than a width of the first line and the second line in a direction orthogonal to a direction that a current flows in the first line and the second line.
摘要翻译：存储单元包括可变电阻膜; 具有与所述可变电阻膜的一个表面接触的一个表面的第一导电膜; 以及具有与可变电阻膜的另一表面接触的一个表面的第二导电膜。第一导电膜或第二导电膜在与第一导电膜或第二导电膜中的电流方向正交的方向上的宽度小于在与方向正交的方向上的可变电阻膜的宽度电流在可变电阻膜中流动。第一导电膜和第二导电膜的宽度小于与第一线和第二线中的电流方向正交的方向上的第一线和第二线的宽度。

16. 发明申请

US20100237314A1 RESISTANCE CHANGE TYPE MEMORY 有权
标题翻译：电阻变化型存储器
公开(公告)号：US20100237314A1
公开(公告)日：2010-09-23
申请号：US12563470
申请日：2009-09-21
申请人： Takayuki Tsukamoto , Reika Ichihara , Hiroshi Kanno , Kenichi Murooka
发明人： Takayuki Tsukamoto , Reika Ichihara , Hiroshi Kanno , Kenichi Murooka
IPC分类号： H01L27/10 , H01L45/00
CPC分类号： G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C2213/72 , H01L27/101 , H01L27/2409 , H01L27/2481
摘要： A resistance change type memory of an aspect of the present invention including a first wiring configured to extend in a first direction, a second wiring configured to extend in a second direction crossing the first direction, a series circuit configured to connect to the first and second wirings, the series circuit including a non-ohmic element being more conductive in the first to second wiring direction than in the second to first direction and a resistance change type storage element in which data is stored according to a change of a resistance state, an energy supplying circuit configured to connect to the first wiring to supply energy to the first wiring, the energy being used to store the data in the resistance change type storage element, and a capacitance circuit configured to include a capacitive element and being connected to the second wiring.
摘要翻译：本发明的一个方面的电阻变化型存储器包括：构造成沿第一方向延伸的第一布线，沿与第一方向交叉的第二方向延伸的第二布线;串联电路，被配置为连接到第一和第二端布线，包括在第一至第二布线方向上比在第二至第一方向上更加导电的非欧姆元件的串联电路和根据电阻状态的变化存储数据的电阻变化型存储元件，能量供给电路，被配置为连接到所述第一布线以向所述第一布线供应能量，所述能量用于将所述数据存储在所述电阻变化型存储元件中;以及电容电路，被配置为包括电容元件并连接到所述第二布线接线。

17. 发明申请

US20100202186A1 SEMICONDUCTOR MEMORY DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF SCREENING THE SAME 有权
标题翻译：半导体存储器件，其制造方法及其筛选方法
公开(公告)号：US20100202186A1
公开(公告)日：2010-08-12
申请号：US12705010
申请日：2010-02-12
申请人： Mitsuru SATO , Masanori Komura , Hiroshi Kanno , Kenichi Murooka
发明人： Mitsuru SATO , Masanori Komura , Hiroshi Kanno , Kenichi Murooka
IPC分类号： G11C11/00 , G11C29/00 , H01L45/00 , H01L21/20
CPC分类号： H01L27/1021 , G11C29/832 , G11C29/88 , G11C2213/72 , H01L27/24 , H01L29/0657 , H01L29/868
摘要： A semiconductor memory device includes first and second memory cells each including a variable resistance element and a diode and having a pillar shape, and an insulating layer provided between the first memory cell and the second memory cell and including a void. A central portion of the diode has a smaller width than widths of upper and lower portions of the diode.
摘要翻译：半导体存储器件包括第一和第二存储器单元，每个存储器单元包括可变电阻元件和二极管，并具有柱形形状;以及绝缘层，设置在第一存储单元和第二存储单元之间并且包括空隙。二极管的中心部分的宽度比二极管的上部和下部的宽度小。

18. 发明申请

US20070285973A1 STORAGE DEVICE 失效
标题翻译：储存设备
公开(公告)号：US20070285973A1
公开(公告)日：2007-12-13
申请号：US11837097
申请日：2007-08-10
申请人： Kenichi Murooka
发明人： Kenichi Murooka
IPC分类号： G11C11/00
CPC分类号： G11C23/00 , G11C2213/71 , G11C2213/77
摘要： The present invention provides a storage device including a first electrode, a plurality of second electrodes arranged opposite the first electrode across a gap, and a particle which is selectively placed in one of the gaps between the first electrode and the second electrodes and which is movable between the first electrode and the second electrode and between the adjacent second electrodes. A stored state is determined utilizing the presence of the particle.
摘要翻译：本发明提供了一种存储装置，其包括第一电极，跨越间隙与第一电极相对布置的多个第二电极和选择性地放置在第一电极和第二电极之间的间隙之一中并且可移动的在第一电极和第二电极之间以及相邻的第二电极之间。使用颗粒的存在来确定存储状态。

19. 发明授权

US08848418B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08848418B2
公开(公告)日：2014-09-30
申请号：US13327065
申请日：2011-12-15
申请人： Kenichi Murooka
发明人： Kenichi Murooka
IPC分类号： G11C11/00
CPC分类号： H01L45/1233 , G11C8/10 , G11C13/0002 , G11C13/0023 , G11C2213/71 , G11C2213/72 , H01L27/2463 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/1608
摘要： A semiconductor memory device according to an embodiment comprises a memory cell array configured from a plurality of row lines and column lines that intersect one another, and from a plurality of memory cells disposed at each of intersections of the row lines and column lines and each including a variable resistance element. Where a number of the row lines is assumed to be N, a number of the column lines is assumed to be M, and a ratio of a cell current flowing in the one of the memory cells when a voltage that is half of the select voltage is applied to the one of the memory cells to a cell current flowing in the one of the memory cells when the select voltage is applied to the one of the memory cells is assumed to be k, a relationship M2
摘要翻译：根据一个实施例的半导体存储器件包括由多个行线和列线构成的存储单元阵列，所述多个行线和列线彼此相交，并且从布置在行线和列线的每个交点处的多个存储单元组成，并且每个包括可变电阻元件。在假设行数为N的情况下，假设列数为M，当存储单元中存在的一个存储单元中的电池电流为选择电压的一半时的电流比当将选择电压施加到一个存储器单元时，将存储单元中的一个施加到流过该存储单元中的一个存储单元的单元电流，则关系M2 <2×N×k 满意。

20. 发明授权

US08320156B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08320156B2
公开(公告)日：2012-11-27
申请号：US12695512
申请日：2010-01-28
申请人： Kenichi Murooka
发明人： Kenichi Murooka
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： G11C13/0007 , G11C8/08 , G11C8/12 , G11C13/0004 , G11C13/0023 , G11C2213/71
摘要： A semiconductor memory device includes a plurality of first wirings; a plurality of second wirings; a plurality of memory cells positioned at respective intersections of the first wirings and the second wirings, each of the memory cells having a variable resistance element and a selective element connected to the variable resistance element in series; a first selection portion selecting the first wiring; a second selection portion selecting the second wiring; and a power source portion applying predetermined selected-wiring-voltages to a selected first wiring being selected by the first selection portion and a selected second wiring being selected by the second selection portion, respectively, and applying predetermined unselected-wiring-voltages to unselected first wirings other than the selected first wiring and unselected second wirings other than the selected second wiring, respectively. A resistance element having a predetermined resistance value is provided between the power source portion and the unselected first and second wirings.
摘要翻译：半导体存储器件包括多个第一配线; 多个第二布线; 多个存储单元，位于第一布线和第二布线的相应交点处，每个存储单元具有可变电阻元件和与可变电阻元件串联连接的选择元件; 选择第一布线的第一选择部分; 选择第二布线的第二选择部分; 以及电源部，分别对由所述第一选择部选择的所选择的第一布线和由所述第二选择部选择的所选择的第二布线分别施加预定的选择布线电压，并将预定的未选择布线电压施加到未选择的第一布线电压除了所选择的第一布线以外的布线和除所选择的第二布线以外的未选择的第二布线。在电源部分和未选择的第一和第二布线之间设置具有预定电阻值的电阻元件。

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