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11. 发明授权

US07659745B1 Variable external interface circuitry on programmable logic device integrated circuits 失效
标题翻译：可编程逻辑器件集成电路上的可变外部接口电路
公开(公告)号：US07659745B1
公开(公告)日：2010-02-09
申请号：US12218688
申请日：2008-07-16
申请人： Wilson Wong , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang
发明人： Wilson Wong , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H03K19/0175 , H03K5/00 , G06F7/38
CPC分类号： H03K19/17744
摘要： A programmable logic device (“PLD”) includes circuitry for optionally and variably modifying characteristics of an input signal in any of several respects. Examples of such modifications include AC coupling the signal into the PLD, low pass filtering the signal (with selectable low-pass filter corner frequency), shifting the common voltage of the input signal, and/or subjecting the input signal to a selectable amount of attenuation.
摘要翻译：可编程逻辑器件（“PLD”）包括用于在几个方面中的任何一个中可选地且可变地修改输入信号的特性的电路。这样的修改的示例包括将信号AC耦合到PLD中，对信号进行低通滤波（具有可选择的低通滤波器转角频率），移位输入信号的公共电压，和/或使输入信号经受可选择量的衰减。

12. 发明授权

US07417462B1 Variable external interface circuitry on programmable logic device integrated circuits 失效
标题翻译：可编程逻辑器件集成电路上的可变外部接口电路
公开(公告)号：US07417462B1
公开(公告)日：2008-08-26
申请号：US11726174
申请日：2007-03-20
申请人： Wilson Wong , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang
发明人： Wilson Wong , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H03K19/0175 , H03K5/00 , G06F7/38
CPC分类号： H03K19/17744
摘要： A programmable logic device (“PLD”) includes circuitry for optionally and variably modifying characteristics of an input signal in any of several respects. Examples of such modifications include AC coupling the signal into the PLD, low pass filtering the signal (with selectable low-pass filter corner frequency), shifting the common voltage of the input signal, and/or subjecting the input signal to a selectable amount of attenuation.
摘要翻译：可编程逻辑器件（“PLD”）包括用于在几个方面中的任何一个中可选地且可变地修改输入信号的特性的电路。这样的修改的示例包括将信号AC耦合到PLD中，对信号进行低通滤波（具有可选择的低通滤波器转角频率），移位输入信号的公共电压，和/或使输入信号经受可选择量的衰减。

13. 发明授权

US08976804B1 Power supply filtering for programmable logic device having heterogeneous serial interface architecture 有权
标题翻译：具有异构串行接口架构的可编程逻辑器件的电源滤波
公开(公告)号：US08976804B1
公开(公告)日：2015-03-10
申请号：US13041764
申请日：2011-03-07
申请人： Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
发明人： Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H04L12/66
CPC分类号： H03K19/17744
摘要： In a programmable logic device with a number of different types of serial interfaces, different power supply filtering schemes are applied to different interfaces. For interfaces operating at the lowest data rates—e.g., 1 Gbps—circuit-board level filtering including one or more decoupling capacitors may be provided. For interfaces operating at somewhat higher data rates—e.g., 3 Gbps—modest on-package filtering also may be provided, which may include power-island decoupling. For interfaces operating at still higher data rates—e.g., 6 Gbps—more substantial on-package filtering, including one or more on-package decoupling capacitors, also may be provided. For interfaces operating at the highest data rates—e.g., 10 Gbps—on-die filtering, which may include one or more on-die filtering or regulating networks, may be provided. The on-die regulators may be programmably bypassable allowing a user to trade off performance for power savings.
摘要翻译：在具有多种不同类型的串行接口的可编程逻辑器件中，不同的电源滤波方案被应用于不同的接口。对于以最低数据速率操作的接口，例如，可以提供包括一个或多个去耦电容器的1Gbps电路板电平滤波器。对于以较高数据速率工作的接口，例如，也可以提供3 Gbps适度的封装内滤波，这可能包括功率岛解耦。对于以更高的数据速率运行的接口，例如，也可以提供包括一个或多个封装内去耦电容器的6Gbps更实质的封装内滤波。对于以最高数据速率工作的接口，例如，可以提供10Gbps片上滤波，其可以包括一个或多个片上滤波或调节网络。片上调节器可以可编程地旁路，允许用户权衡功能以节省功率。

14. 发明授权

US08208523B2 Digital adaptation circuitry and methods for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的数字适配电路和方法
公开(公告)号：US08208523B2
公开(公告)日：2012-06-26
申请号：US13079420
申请日：2011-04-04
申请人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
发明人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
IPC分类号： H03H7/30
CPC分类号： H04L25/03885
摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.
摘要翻译：输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

15. 发明授权

US07996749B2 Signal loss detector for high-speed serial interface of a programmable logic device 有权
标题翻译：用于可编程逻辑器件的高速串行接口的信号丢失检测器
公开(公告)号：US07996749B2
公开(公告)日：2011-08-09
申请号：US11773234
申请日：2007-07-03
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H03M13/03
CPC分类号： H04L25/45
摘要： A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.
摘要翻译：信号丢失检测器包括对输入数据进行数字和模拟监测。输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

16. 发明申请

US20110188564A1 DIGITAL ADAPTATION CIRCUITRY AND METHODS FOR PROGRAMMABLE LOGIC DEVICES 有权
标题翻译：数字适配电路和可编程逻辑器件的方法
公开(公告)号：US20110188564A1
公开(公告)日：2011-08-04
申请号：US13079420
申请日：2011-04-04
申请人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
发明人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
IPC分类号： H03K5/125 , H03K5/19
CPC分类号： H04L25/03885
摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.
摘要翻译：输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

17. 发明授权

US07750674B2 Low-power transceiver architectures for programmable logic integrated circuit devices 有权
标题翻译：用于可编程逻辑集成电路器件的低功耗收发器架构
公开(公告)号：US07750674B2
公开(公告)日：2010-07-06
申请号：US12214466
申请日：2008-06-18
申请人： Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Thungoc M. Tran , Richard G. Cliff
发明人： Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Thungoc M. Tran , Richard G. Cliff
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/17744 , H03K19/17784
摘要： High-speed serial interface or transceiver circuitry on a programmable logic device integrated circuit (“PLD”) includes features that permit the PLD to satisfy a wide range of possible user needs or applications. This range includes both high-performance applications and applications in which reduced power consumption by the PLD is important. In the latter case, any one or more of various features can be used to help reduce power consumption.
摘要翻译：可编程逻辑器件集成电路（“PLD”）上的高速串行接口或收发器电路包括允许PLD满足广泛可能的用户需求或应用的功能。该范围包括高性能应用和PLD降低功耗很重要的应用。在后一种情况下，可以使用任何一种或多种各种特征来帮助降低功耗。

18. 发明授权

US07586983B1 Systems and methods for offset cancellation in integrated transceivers 有权
标题翻译：集成收发器偏移消除的系统和方法
公开(公告)号：US07586983B1
公开(公告)日：2009-09-08
申请号：US11510446
申请日：2006-08-24
申请人： Sergey Shumarayev , Wilson Wong , Simardeep Maangat , Thungoc M. Tran , Tim Tri Hoang
发明人： Sergey Shumarayev , Wilson Wong , Simardeep Maangat , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H03K5/159 , H04B1/10
CPC分类号： H04L25/03057
摘要： In high speed receiver circuitry (e.g., on a programmable logic device (PLD) or the like), decision feedback equalization (DFE) circuitry is used to at least partly cancel unwanted offset (e.g., from other elements of the receiver). The data input to the receiver is tristated; and then each DFE tap coefficient is varied in turn to find coefficient values that are associated with transitions between oscillation and non-oscillation of the receiver output signal. The coefficient values found in this way are used to select trial values. If the output signal of the receiver does not oscillate when these trial values are used, the process is repeated starting from these (or subsequent) trial values until a final set of trial values does allow oscillation of the receiver output signal.
摘要翻译：在高速接收机电路（例如，在可编程逻辑器件（PLD）等上）中，使用判决反馈均衡（DFE）电路来至少部分地消除不期望的偏移（例如，从接收机的其他元件）。输入到接收机的数据被三态化; 然后依次改变每个DFE抽头系数，以找到与接收机输出信号的振荡和非振荡之间的转换相关联的系数值。以这种方式找到的系数值用于选择试验值。如果接收机的输出信号在使用这些试验值时不振荡，则从这些（或后续）试验值开始重复该过程，直到最终的试验值确定允许接收器输出信号的振荡。

19. 发明授权

US07403035B1 Low-power transceiver architectures for programmable logic integrated circuit devices 有权
公开(公告)号：US07403035B1
公开(公告)日：2008-07-22
申请号：US11788561
申请日：2007-04-19
申请人： Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Thungoc M. Tran , Richard G. Cliff
发明人： Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Thungoc M. Tran , Richard G. Cliff
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/17744 , H03K19/17784
摘要： High-speed serial interface or transceiver circuitry on a programmable logic device integrated circuit (“PLD”) includes features that permit the PLD to satisfy a wide range of possible user needs or applications. This range includes both high-performance applications and applications in which reduced power consumption by the PLD is important. In the latter case, any one or more of various features can be used to help reduce power consumption.

20. 发明授权

US08126079B1 High-speed serial data signal interface circuitry with multi-data-rate switching capability 有权
标题翻译：具有多数据速率切换功能的高速串行数据信号接口电路
公开(公告)号：US08126079B1
公开(公告)日：2012-02-28
申请号：US11824862
申请日：2007-07-03
申请人： Thungoc M. Tran , Sergey Shumarayev , Tim Tri Hoang , Weiqi Ding , Wilson Wong , Allen Chan
发明人： Thungoc M. Tran , Sergey Shumarayev , Tim Tri Hoang , Weiqi Ding , Wilson Wong , Allen Chan
IPC分类号： H04L27/00
CPC分类号： H04L7/033 , H03L7/22 , H04L7/0008
摘要： High-speed serial data signal transmitter and/or receiver circuitry is able to dynamically switch between handling data at two (or more) different data rates. Such a switch can be made very rapidly and with no requirement for reprogramming or reconfiguring the circuitry. Circuitry for glitchlessly switching between clock signals having different frequencies is also provided and may be used in the above-mentioned transmitter and/or receiver circuitry.
摘要翻译：高速串行数据信号发射机和/或接收机电路能够以两种（或多种）不同的数据速率在处理数据之间动态切换。这样的开关可以非常快速地进行，并且不需要重新编程或重新配置电路。还提供了用于在具有不同频率的时钟信号之间无差错地切换的电路，并且可以在上述发射机和/或接收机电路中使用。

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