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11. 发明授权

US07355462B1 Phase lock loop and method for operating the same 有权
标题翻译：锁相环及其操作方法
公开(公告)号：US07355462B1
公开(公告)日：2008-04-08
申请号：US11456484
申请日：2006-07-10
申请人： Wilson Wong , Rakesh H. Patel , Sergey Shumarayev
发明人： Wilson Wong , Rakesh H. Patel , Sergey Shumarayev
IPC分类号： H03L7/06
CPC分类号： H03L7/089 , H03L7/093 , H03L7/18
摘要： A digital controller for a voltage controlled oscillator (VCO) is provided within a phase lock loop (PLL). The digital controller includes a digital filter having first and second inputs for receiving upward and downward adjustment signals, respectively. The digital filter generates an increment signal and a decrement signal in response to the upward and downward adjustment signals, respectively. The digital controller includes a digital counter having first and second inputs for receiving the increment and decrement signals, respectively. The digital counter generates a multi-bit output signal that represents a running sum of the increment and decrement signals. The digital controller further includes a digital-to-analog converter (DAC) having an input for receiving the running sum output signal generated by the digital counter. The DAC is defined to generate a control voltage for the VCO in response to receipt of the running sum output signal from the digital counter.
摘要翻译：在锁相环（PLL）内提供压控振荡器（VCO）的数字控制器。数字控制器包括具有分别用于接收上下调节信号的第一和第二输入的数字滤波器。数字滤波器分别响应于上下调节信号产生增量信号和减量信号。数字控制器包括一个数字计数器，它具有分别用于接收增量和减量信号的第一和第二输入端。数字计数器产生一个多位输出信号，表示增量和减量信号的运行和。数字控制器还包括具有用于接收由数字计数器产生的运行和输出信号的输入的数模转换器（DAC）。 DAC被定义为响应于来自数字计数器的运行和输出信号的接收而产生用于VCO的控制电压。

12. 发明授权

US08175143B1 Adaptive equalization using data level detection 有权
标题翻译：使用数据级检测的自适应均衡
公开(公告)号：US08175143B1
公开(公告)日：2012-05-08
申请号：US12037284
申请日：2008-02-26
申请人： Wilson Wong , Tin H. Lai , Allen Chan , Tim Tri Hoang , Sergey Shumarayev
发明人： Wilson Wong , Tin H. Lai , Allen Chan , Tim Tri Hoang , Sergey Shumarayev
IPC分类号： H03H7/30
CPC分类号： H04L25/03057 , H04L25/03885 , H04L2025/03356 , H04L2025/03745 , H04L2025/03783
摘要： A method, and circuitry, for choosing the correct equalization curve in adaptive equalization uses a feedback loop in which the incoming high-speed serial data are digitized and deserialized for use in the remainder of the device, and also are used by an adaptive state machine to both extract the reference levels for digitization and to control the equalization curve. Detection of the reference level and selection of the equalization curve may be performed at a different rates to avoid interfering with one another. The state machine preferably is programmable. This is useful in any device, but is particularly well-suited for a programmable device, such as a PLD or other programmable integrated circuit device, where conditions may vary according a user logic design.
摘要翻译：用于在自适应均衡中选择正确的均衡曲线的方法和电路使用反馈回路，其中输入的高速串行数据被数字化和反序列化以用于设备的其余部分，并且还被自适应状态机以提取用于数字化的参考电平并控制均衡曲线。参考电平的检测和均衡曲线的选择可以以不同的速率进行，以避免彼此干扰。状态机优选是可编程的。这在任何设备中是有用的，但是特别适用于诸如PLD或其他可编程集成电路设备的可编程设备，其中条件可以根据用户逻辑设计而变化。

13. 发明授权

US07920621B2 Digital adaptation circuitry and methods for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的数字适配电路和方法
公开(公告)号：US07920621B2
公开(公告)日：2011-04-05
申请号：US11522284
申请日：2006-09-14
申请人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
发明人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
IPC分类号： H03H7/30
CPC分类号： H04L25/03885
摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.
摘要翻译：输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

14. 发明授权

US07760799B2 Programmable digital equalization control circuitry and methods 失效
标题翻译：可编程数字均衡控制电路和方法
公开(公告)号：US07760799B2
公开(公告)日：2010-07-20
申请号：US11238365
申请日：2005-09-28
申请人： Tin H. Lai , Sergey Shumarayev , Simardeep Maangat , Wilson Wong
发明人： Tin H. Lai , Sergey Shumarayev , Simardeep Maangat , Wilson Wong
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H03G3/3089 , H04L25/03885
摘要： Equalization circuitry may be used to compensate for the attenuation of a data signal caused by a transmission medium. The control circuitry for the equalization circuitry may generate control inputs for equalization stages that control the amount of gain provided to the data signal. A comparator may determine whether the gain from the equalization circuitry is less than or more than the desired amount of gain. A programmable up/down counter may adjust the counter value based on the output of the comparator. The counter value may be converted into one or more analog voltages using one or more digital-to-analog converters. These analog voltages may be provided to the equalization stages as control inputs. The control circuitry may also include hysteresis circuitry that prevents the counter value from being adjusted when the gain produced by the equalization stages is close to the desired amount of gain.
摘要翻译：均衡电路可用于补偿由传输介质引起的数据信号的衰减。用于均衡电路的控制电路可以产生用于控制提供给数据信号的增益量的均衡级的控制输入。比较器可以确定来自均衡电路的增益是否小于或大于期望的增益量。可编程上/下计数器可以根据比较器的输出来调整计数器值。可以使用一个或多个数模转换器将计数器值转换成一个或多个模拟电压。这些模拟电压可以作为控制输入提供给均衡级。控制电路还可以包括滞后电路，当由均衡级产生的增益接近期望的增益量时，阻止计数器值被调整。

15. 发明授权

US08208523B2 Digital adaptation circuitry and methods for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的数字适配电路和方法
公开(公告)号：US08208523B2
公开(公告)日：2012-06-26
申请号：US13079420
申请日：2011-04-04
申请人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
发明人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
IPC分类号： H03H7/30
CPC分类号： H04L25/03885
摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.
摘要翻译：输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

16. 发明申请

US20110188564A1 DIGITAL ADAPTATION CIRCUITRY AND METHODS FOR PROGRAMMABLE LOGIC DEVICES 有权
标题翻译：数字适配电路和可编程逻辑器件的方法
公开(公告)号：US20110188564A1
公开(公告)日：2011-08-04
申请号：US13079420
申请日：2011-04-04
申请人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
发明人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
IPC分类号： H03K5/125 , H03K5/19
CPC分类号： H04L25/03885
摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.
摘要翻译：输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

17. 发明授权

US07514968B1 H-tree driver circuitry 有权
标题翻译： H树驱动电路
公开(公告)号：US07514968B1
公开(公告)日：2009-04-07
申请号：US11786295
申请日：2007-04-10
申请人： Tin H. Lai , Wilson Wong , Sergey Shumarayev , Tim Tri Hoang
发明人： Tin H. Lai , Wilson Wong , Sergey Shumarayev , Tim Tri Hoang
IPC分类号： H03K3/00
CPC分类号： H03K19/018528 , H04L25/0272
摘要： An H-tree driver circuit has pull-up and pull-down current sources, each of which is implemented using a low-voltage-cascode topology.
摘要翻译： H-tree驱动电路具有上拉和下拉电流源，每个都使用低压共源共栅拓扑来实现。

18. 发明申请

US20110211621A1 HETEROGENEOUS TRANSCEIVER ARCHITECTURE FOR WIDE RANGE PROGRAMMABILITY OF PROGRAMMABLE LOGIC DEVICES 有权
标题翻译：用于可编程逻辑器件的宽范围可编程性的异构收发器架构
公开(公告)号：US20110211621A1
公开(公告)日：2011-09-01
申请号：US13103132
申请日：2011-05-09
申请人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
发明人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
IPC分类号： H04L5/14 , H04L27/00
CPC分类号： H04L5/14 , H03K19/17744 , H04L27/00
摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.
摘要翻译：可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道达到第二个相对较高的最大数据速率。相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

19. 发明申请

US20100058099A1 HETEROGENEOUS TRANSCEIVER ARCHITECTURE FOR WIDE RANGE PROGRAMMABILITY OF PROGRAMMABLE LOGIC DEVICES 有权
标题翻译：用于可编程逻辑器件的宽范围可编程性的异构收发器架构
公开(公告)号：US20100058099A1
公开(公告)日：2010-03-04
申请号：US12576507
申请日：2009-10-09
申请人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
发明人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
IPC分类号： G06F1/04 , G06F1/12
CPC分类号： H04L5/14 , H03K19/17744 , H04L27/00
摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.
摘要翻译：可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道达到第二个相对较高的最大数据速率。相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

20. 发明授权

US08098087B1 Method and apparatus for standby voltage offset cancellation 失效
标题翻译：待机电压失调消除的方法和装置
公开(公告)号：US08098087B1
公开(公告)日：2012-01-17
申请号：US11682282
申请日：2007-03-05
申请人： John Dung-Ngoc Lam , Arch Zaliznyak , Wilson Wong , Tin H. Lai , Chong H. Lee , Sergey Shumarayev
发明人： John Dung-Ngoc Lam , Arch Zaliznyak , Wilson Wong , Tin H. Lai , Chong H. Lee , Sergey Shumarayev
IPC分类号： H03K5/08
CPC分类号： H04L25/03878 , H03K5/249
摘要： A method and apparatus is provided for standby voltage offset cancellation at inputs to a comparator within a receiver channel. Each of a first comparator input and second comparator input is isolated from an input signal such that each of the first and second comparator inputs attains a respective standby voltage level. A voltage level on one of the first and second comparator inputs is incrementally changed, while the output signal of the comparator is monitored. Upon detecting a state transition in the output signal of the comparator, the incremental changing of the voltage level on the one comparator input is stopped at a final voltage level setting. The final voltage level setting is stored in a computer memory for reference in setting of the voltage level at the one comparator input so as to compensate for the standby voltage offset at the inputs to the comparator.
摘要翻译：提供了一种方法和装置，用于在接收器通道内的比较器的输入处的待机电压偏移消除。第一比较器输入和第二比较器输入中的每一个与输入信号隔离，使得第一和第二比较器输入中的每一个达到相应的待机电压电平。在第一和第二比较器输入之一上的电压电平递增地改变，同时监视比较器的输出信号。在检测到比较器的输出信号中的状态转变时，一个比较器输入端的电压电平的增量变化在最终电压电平设置下停止。最后的电压电平设置存储在计算机存储器中，用于参考在一个比较器输入处的电压电平的设置，以便补偿在比较器的输入处的待机电压偏移。

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