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21. 发明申请

US20070007459A1 Radioactive ray detector 失效
标题翻译：放射线检测器
公开(公告)号：US20070007459A1
公开(公告)日：2007-01-11
申请号：US10552705
申请日：2004-04-09
申请人： Katsumi Shibayama , Yutaka Kusuyama , Masahiro Hayashi
发明人： Katsumi Shibayama , Yutaka Kusuyama , Masahiro Hayashi
IPC分类号： G01T1/20
CPC分类号： H01L27/14661 , G01T1/2018 , H01L27/14634 , H01L31/02322
摘要： A wiring substrate section 2 is provided between a radiation detecting section 1, which is formed of a scintillator 10 and a PD array 15, and signal processing elements 30 and 32 for processing a detected signal outputted from the PD array 15, and the wiring substrate section 2 has a wiring substrate 20 which is formed of a glass material having a radiation shielding function and in which a conductive member 21 serving as a conduction path for guiding the detected signal therethrough is provided in a through hole 20c. Relative to the through hole 20c of the wiring substrate 20, the signal processing elements 30 and 32 of the signal processing section 3, located downstream of the wiring substrate 20, are each disposed in an area excluding those areas on the extension of the through holes 20c, and this allows the signal processing elements 30 and 32 not to be seen through the through holes 20c. This arrangement realizes a radiation detector which suppresses radiation made incident on the signal processing means located downstream of the wiring substrate.
摘要翻译：布线基板部分2设置在由闪烁体10和PD阵列15形成的辐射检测部分1和用于处理从PD阵列15输出的检测信号的信号处理元件30和32之间，以及布线基板部分2具有布线基板20，该布线基板20由具有辐射屏蔽功能的玻璃材料形成，并且其中用作引导检测信号的导电路径的导电部件21设置在通孔20c中。相对于布线基板20的通孔20c，位于布线基板20下游的信号处理部3的信号处理元件30,32分别设置在除了贯通孔20的延伸部分以外的区域的区域孔20c，并且这允许信号处理元件30和32不被通过通孔20c看到。这种布置实现了辐射检测器，其抑制入射到位于布线基板下游的信号处理装置的辐射。

22. 发明授权

US07141862B2 Semiconductor device and method for manufacturing the same 有权
公开(公告)号：US07141862B2
公开(公告)日：2006-11-28
申请号：US10890403
申请日：2004-07-13
申请人： Takafumi Noda , Masahiro Hayashi , Akihiko Ebina , Masahiko Tsuyuki
发明人： Takafumi Noda , Masahiro Hayashi , Akihiko Ebina , Masahiko Tsuyuki
IPC分类号： H01L29/00
CPC分类号： H01L21/823418 , H01L21/823462
摘要： A semiconductor device is provided in which high breakdown voltage transistors and low voltage driving transistors are formed on the same substrate. The device includes a semiconductor layer, first element isolation regions for defining a high breakdown voltage transistor forming region in the semiconductor layer, second element isolation regions including trench dielectric layers for defining a low voltage driving transistor forming region in the semiconductor layer, high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, low voltage driving transistors formed in the low voltage driving transistor forming region, and offset dielectric layers for alleviating the electric field of the high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, wherein upper ends of the offset dielectric layers are beak shaped.

23. 发明授权

US07020084B1 Communication system, a communication method and communication terminal 失效
标题翻译：通信系统，通信方式和通信终端
公开(公告)号：US07020084B1
公开(公告)日：2006-03-28
申请号：US09642013
申请日：2000-08-21
申请人： Koji Tanaka , Masahiro Hayashi , Koji Hirayama , Haruo Shibata
发明人： Koji Tanaka , Masahiro Hayashi , Koji Hirayama , Haruo Shibata
IPC分类号： H04L12/56 , G06F15/16
CPC分类号： H04L12/14 , H04L12/1432 , H04L12/2856 , H04L12/2865 , H04L12/4633 , H04L67/14 , Y02D50/30
摘要： A service of reducing the number of tunnels in exchange for a specified service fee. A communication system, which generates tunnels in physical lines and multiplexes a plurality of sessions on the physical lines, comprises a monitor unit for monitoring the state of use of tunnels and sessions used by the user when the user using a plurality of tunnels is a customer who requires service of reserving sessions in a smaller number of tunnels in exchange for a specified service fee; a tunnel/session control unit performs control so as to gather the plurality of sessions of said user in a specified tunnel when the sessions currently used by the user can be reserved in a smaller number of tunnels; and a charging unit for charging a usage rate according to the number of tunnels or the number of physical lines used.
摘要翻译：减少隧道数量以换取指定服务费的服务。一种在物理线路上生成隧道并在物理线路上复用多个会话的通信系统包括监视单元，用于在使用多个隧道的用户是客户时监视用户使用的隧道和会话的使用状态谁要求在较少数量的隧道中预约会议的服务，以换取指定的服务费; 隧道/会话控制单元执行控制，以便当用户当前使用的会话可以保留在较少数量的隧道中时，在指定的隧道中收集所述用户的多个会话; 以及用于根据隧道数量或所使用的物理线路数量对使用率进行计费的计费单元。

24. 发明授权

US06924535B2 Semiconductor device with high and low breakdown voltage transistors 有权
标题翻译：具有高和低击穿电压晶体管的半导体器件
公开(公告)号：US06924535B2
公开(公告)日：2005-08-02
申请号：US10382112
申请日：2003-03-05
申请人： Masahiro Hayashi
发明人： Masahiro Hayashi
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/94
CPC分类号： H01L27/0928
摘要： A semiconductor device, having a high breakdown voltage transistor and a low breakdown voltage transistor in a common substrate with different driving voltages, includes a semiconductor substrate of a first conductivity type, a first triple well formed in the semiconductor substrate and having a first well of a second conductivity type and a second well of the first conductivity type formed within the first well, a second triple well formed in the semiconductor substrate and having a third well of the second conductivity type and a fourth well of the first conductivity type formed within the third well, a low breakdown voltage transistor of the second conductivity type formed at the second well, and a high breakdown voltage transistor of the second conductivity type formed at the fourth well. The first well of the first triple well can have an impurity concentration higher than an impurity concentration of the third well of the second triple well.
摘要翻译：具有不同驱动电压的公共衬底中的具有高击穿电压晶体管和低击穿电压晶体管的半导体器件包括：第一导电类型的半导体衬底，形成在半导体衬底中的第一三阱，在第一阱内形成的第一导电类型的第二导电类型和第二阱，形成在半导体衬底中并具有第二导电类型的第三阱的第二三阱和形成在第一阱内的第一导电类型的第四阱第三阱，形成在第二阱的第二导电类型的低击穿电压晶体管，以及形成在第四阱的第二导电类型的高击穿电压晶体管。第一个三重阱的第一个阱可以具有高于第二个三重阱的第三个阱的杂质浓度的杂质浓度。

25. 发明申请

US20050087835A1 Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US20050087835A1
公开(公告)日：2005-04-28
申请号：US10961769
申请日：2004-10-07
申请人： Masahiro Hayashi , Takafumi Noda , Yoshinobu Yusa
发明人： Masahiro Hayashi , Takafumi Noda , Yoshinobu Yusa
IPC分类号： H01L21/316 , H01L21/76 , H01L21/762 , H01L21/8234 , H01L27/08 , H01L27/088 , H01L29/78 , H01L29/00
CPC分类号： H01L21/823456 , H01L21/76202 , H01L21/76224 , H01L21/823418 , H01L21/823462 , H01L27/088
摘要： A semiconductor device of the present invention is provided with a high breakdown voltage transistor 100 and a low voltage driving transistor 200 on a same semiconductor layer 10 comprising: the semiconductor layer 10; an offset insulating layer 20 comprising a LOCOS layer for an electric field relaxation of the high breakdown voltage transistor 100 provided on the semiconductor layer 10; and a trench insulating layer 28 for defining a forming region of the low voltage driving transistor 200 provided on the semiconductor layer 10, wherein at least a part of the upper surface of the offset insulating layer 20 is nearly as high as the surface of the semiconductor layer 10.
摘要翻译：本发明的半导体器件在同一半导体层10上设置有高耐压晶体管100和低电压驱动晶体管200，该半导体层10包括：半导体层10; 偏移绝缘层20，包括用于设置在半导体层10上的高击穿电压晶体管100的电场弛豫的LOCOS层; 以及用于限定设置在半导体层10上的低电压驱动晶体管200的形成区域的沟槽绝缘层28，其中，偏移绝缘层20的上表面的至少一部分几乎与半导体的表面一样高第10层。

26. 发明申请

US20050059196A1 Method for manufacturing semiconductor devices 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20050059196A1
公开(公告)日：2005-03-17
申请号：US10902699
申请日：2004-07-29
申请人： Takafumi Noda , Masahiro Hayashi , Akihiko-Ebina , Masahiko Tsuyuki
发明人： Takafumi Noda , Masahiro Hayashi , Akihiko-Ebina , Masahiko Tsuyuki
IPC分类号： H01L21/76 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L27/08 , H01L27/088 , H01L27/092
CPC分类号： H01L21/823892 , H01L21/823814 , H01L21/823857 , H01L27/0922 , H01L27/0928
摘要： A semiconductor device manufacturing method is provided including: forming a first impurity layer that becomes first wells in a high breakdown voltage transistor forming region in a semiconductor layer; forming a second impurity layer that becomes offset regions in the high breakdown voltage transistor forming region; forming the first wells and the offset regions by diffusing impurities of the first and second impurity layers by heat treating the semiconductor layer; forming element isolation regions by a trench element isolation method in the semiconductor layer, after forming the first wells and the offset regions; forming first gate dielectric layers in the high breakdown voltage transistor forming region; forming second wells in a low voltage driving transistor forming region in the semiconductor layer; forming second gate dielectric layers in the low voltage driving transistor forming region; and forming gate electrodes in the high breakdown voltage transistor forming region and the low voltage driving transistor forming region.
摘要翻译：提供一种半导体器件制造方法，包括：在半导体层中形成在高击穿电压晶体管形成区域中成为第一阱的第一杂质层; 形成成为所述高击穿电压晶体管形成区域的偏移区域的第二杂质层; 通过热处理所述半导体层来扩散所述第一和第二杂质层的杂质来形成所述第一阱和所述偏移区域; 在形成第一阱和偏移区之后，通过沟槽元件隔离方法在半导体层中形成元件隔离区; 在高击穿电压晶体管形成区域中形成第一栅极电介质层; 在半导体层中的低电压驱动晶体管形成区域中形成第二阱; 在所述低电压驱动晶体管形成区域中形成第二栅极电介质层; 以及在高击穿电压晶体管形成区域和低电压驱动晶体管形成区域中形成栅电极。

27. 发明申请

US20050029616A1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050029616A1
公开(公告)日：2005-02-10
申请号：US10890403
申请日：2004-07-13
申请人： Takafumi Noda , Masahiro Hayashi , Akihiko Ebina , Masahiko Tsuyuki
发明人： Takafumi Noda , Masahiro Hayashi , Akihiko Ebina , Masahiko Tsuyuki
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/78 , H01L21/336 , H01L29/00
CPC分类号： H01L21/823418 , H01L21/823462
摘要： A semiconductor device is provided in which high breakdown voltage transistors and low voltage driving transistors are formed on the same substrate. The device includes a semiconductor layer, first element isolation regions for defining a high breakdown voltage transistor forming region in the semiconductor layer, second element isolation regions including trench dielectric layers for defining a low voltage driving transistor forming region in the semiconductor layer, high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, low voltage driving transistors formed in the low voltage driving transistor forming region, and offset dielectric layers for alleviating the electric field of the high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, wherein upper ends of the offset dielectric layers are beak shaped.
摘要翻译：提供了一种半导体器件，其中在相同的衬底上形成有高的击穿电压晶体管和低电压驱动晶体管。所述器件包括半导体层，用于限定半导体层中的高击穿电压晶体管形成区域的第一元件隔离区域，包括用于限定半导体层中的低电压驱动晶体管形成区域的沟槽电介质层的第二元件隔离区域，高击穿电压形成在高击穿电压晶体管形成区域中的晶体管，形成在低电压驱动晶体管形成区域中的低电压驱动晶体管，以及用于减轻形成在高击穿电压晶体管形成区域中的高击穿电压晶体管的电场的偏移电介质层，其中偏移电介质层的上端为喙状。

28. 发明授权

US06296698B1 Cement admixture and cement composition 失效
标题翻译：水泥外加剂和水泥组成
公开(公告)号：US06296698B1
公开(公告)日：2001-10-02
申请号：US09385138
申请日：1999-08-30
申请人： Satoru Naramoto , Masahiro Hayashi , Kazuhiko Hiromoto
发明人： Satoru Naramoto , Masahiro Hayashi , Kazuhiko Hiromoto
IPC分类号： C04B2426
CPC分类号： C08F290/062 , C04B24/165 , C04B24/2658 , C04B24/2694 , C04B2103/0082 , C04B2103/30 , C08F220/06 , C08F220/28 , C08F226/02
摘要： A cement admixture that includes a copolymer obtained by polymerizing (A) 10 to 85% by weight of N-vinylacetamide or a monomer derived therefrom, (B) 10 to 90% by weight of an (alkoxy)polyethylene glycol (meth)acrylate or (alkoxy)polyethylene glycol (meth)allyl ether monomer, (C) 5 to 50% by weight of a vinyl monomer containing one carboxylic acid group, at least one sulfonic acid group or salt thereof in a molecule, and (D) 0 to 40% by weight of a vinyl monomer other than (A), (B) and (C), provided that the sum of monomers (A), (B), (C) and (D) is 100% by weight. The cement admixture by itself can impart a cement composition with flowability, flowability maintenance ability, packing property and resistance to segregation in good balance, and is effective in improvement of workability, operability, and quality of hardened article.
摘要翻译：一种水泥混合物，其包括通过聚合（A）10-85重量％的N-乙烯基乙酰胺或由其衍生的单体获得的共聚物，（B）10-90重量％的（烷氧基）聚乙二醇（甲基）丙烯酸酯或（烷氧基）聚乙二醇（甲基）烯丙基醚单体，（C）5〜50重量％的含有1个羧酸基的乙烯基单体，分子中至少1个磺酸基或其盐，（D）0〜 40重量％的（A），（B）和（C）以外的乙烯基单体，条件是单体（A），（B），（C）和（D）的总和为100重量％。水泥外加剂本身可赋予水泥组合物具有流动性，流动性维持能力，包装性能和耐偏析性良好的平衡性，并且有效地提高了硬化制品的加工性，可操作性和质量。

29. 发明授权

US5684602A Facsimile apparatus with coding/decoding interrupt 失效
标题翻译：具有编码/解码中断的传真机
公开(公告)号：US5684602A
公开(公告)日：1997-11-04
申请号：US267363
申请日：1994-06-29
申请人： Suguru Tsuchiya , Mitsutoshi Tsukamoto , Tadanori Ipponyari , Takafumi Higuchi , Katsuya Okamoto , Masahiro Hayashi
发明人： Suguru Tsuchiya , Mitsutoshi Tsukamoto , Tadanori Ipponyari , Takafumi Higuchi , Katsuya Okamoto , Masahiro Hayashi
IPC分类号： H04N1/32 , H04N1/00 , G06K9/36 , H04N1/36
CPC分类号： H04N1/32379 , H04N1/00915 , H04N1/32358 , H04N1/32448 , H04N1/32502 , H04N1/32512 , H04N1/32518 , H04N2201/0081 , H04N2201/0082 , H04N2201/0086 , H04N2201/3288 , H04N2201/3297
摘要： A facsimile apparatus comprises a receiving buffer for receiving video data, a scanner for reading an image, a VRAM for storing a coded data, a single coding/decoding (C/D) IC for MR-coding, MR-to-MMR coding, decoding, and error-checking, and a page printer, and a control circuit, when an event requiring more than two operations of the C/D IC at the same time, the control circuit permits only one operation and force the other operations to wait in some condition. In another condition, the control circuit permits one of the other operation and force the other operations to wait. For example, when the scanner reads an image to produce read data and the C/D IC codes the read data to store the read data in the VRAM and there is a call, the control means connects the line but keeps the coding if the receiving buffer has a space. In the presence of the space the control circuit interrupt the coding and starts the decoding. Another event requiring operation of C/D IC of the MMR coding from MR coded data and operation of MR coding, decoding, or error-checking may be occur. Various events requiring combination of operations of the single C/D IC at the same time and various adaptable controllings are considered.
摘要翻译：传真装置包括用于接收视频数据的接收缓冲器，用于读取图像的扫描器，用于存储编码数据的VRAM，用于MR编码的单个编码/解码（C / D）IC，MR到MMR编码，解码和错误检查，以及页面打印机和控制电路，当同时需要C / D IC多于两个操作的事件时，控制电路仅允许一个操作并迫使其他操作等待在某种情况下。在另一种情况下，控制电路允许其他操作之一并且迫使其他操作等待。例如，当扫描仪读取图像以产生读取数据，并且C / D IC对读取的数据进行编码以将读取的数据存储在VRAM中并且存在呼叫时，控制装置连接线路，但是如果接收到缓冲区有空格。在存在空间的情况下，控制电路中断编码并开始解码。可能会发生需要从MR编码数据操作MMR编码的C / D IC和进行MR编码，解码或错误检查的另一事件。考虑到同时需要组合单个C / D IC的各种事件和各种适应性控制。

30. 发明授权

US5606101A Substitute amic acid derivatives 失效
标题翻译：取代酰胺酸衍生物
公开(公告)号：US5606101A
公开(公告)日：1997-02-25
申请号：US540329
申请日：1995-10-06
申请人： Takashi Nomoto , Masahiro Hayashi , Jun Shibata , Yoshikazu Iwasawa , Morihiro Mitsuya , Yoshiaki IIda , Katsumasa Nonoshita , Yasufumi Nagata
发明人： Takashi Nomoto , Masahiro Hayashi , Jun Shibata , Yoshikazu Iwasawa , Morihiro Mitsuya , Yoshiaki IIda , Katsumasa Nonoshita , Yasufumi Nagata
IPC分类号： C07C69/34 , C07C211/27 , C07C211/29 , C07C215/52 , C07C217/60 , C07C233/05 , C07C233/13 , C07C233/18 , C07C235/06 , C07D213/38 , C07D213/40 , C07D215/12 , C07D215/48 , C07D263/32 , C07D307/14 , C07D307/52 , C07D307/81 , C07D317/58 , C07D333/20 , C07D333/28 , C07D333/54 , C07D333/58 , C07C69/353
CPC分类号： C07D213/40 , C07C211/27 , C07C211/29 , C07C215/52 , C07C217/60 , C07C233/05 , C07C233/13 , C07C233/18 , C07C235/06 , C07C69/34 , C07D213/38 , C07D215/12 , C07D215/48 , C07D263/32 , C07D307/14 , C07D307/52 , C07D307/81 , C07D317/58 , C07D333/20 , C07D333/28 , C07D333/54 , C07D333/58
摘要： A compound of the formula (I) or its pharmaceutically acceptable salt or ester: ##STR1## and intermediates thereof.
摘要翻译：式（I）化合物或其药学上可接受的盐或酯：其中和（I）及其中间体。

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