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21. 发明申请

US20110284273A1 POWER CORE FOR USE IN CIRCUITIZED SUBSTRATE AND METHOD OF MAKING SAME 有权
标题翻译：在电路基板中使用的电源芯及其制造方法
公开(公告)号：US20110284273A1
公开(公告)日：2011-11-24
申请号：US12782187
申请日：2010-05-18
申请人： Robert M. Japp , Kostas Papathomas , John S. Kresge , Timothy Antesberger
发明人： Robert M. Japp , Kostas Papathomas , John S. Kresge , Timothy Antesberger
IPC分类号： H05K1/09 , H05K1/00 , H01R43/00 , H05K1/11
CPC分类号： H05K3/4641 , H05K3/4617 , H05K2201/068 , Y10T29/49117
摘要： A power core adapted for use as part of a circuitized substrate, e.g., a PCB or LCC. The core includes a first layer of low expansion dielectric and two added layers of a different low expansion dielectric bonded thereto, with two conductive layers positioned on the two added low expansion dielectric layers. At least one of the conductive layers serves as a power plane for the power core, which in turn is usable within a circuitized substrate, also provided. Methods of making the power core and circuitized substrate are also provided. The use of different low expansion dielectric materials for the power core enables the use of support enhancing fiberglass in one layer while such use is precluded in the other two dielectric layers, thus preventing CAF shorting problems in highly precisely defined thru holes formed within the power core.
摘要翻译：适于用作电路化基板（例如PCB或LCC）的一部分的电源核心。芯包括第一层低膨胀电介质和两个相邻的不同的低膨胀电介质结合的层，其中两个导电层位于两个添加的低膨胀介电层上。导电层中的至少一个用作功率芯的功率平面，而功率芯也可以在电路化的衬底内使用。还提供了制造电源芯和电路化基板的方法。使用不同的低膨胀电介质材料用于电源芯可以在一层中使用支撑增强玻璃纤维，而在其他两个电介质层中排除这种用途，从而防止形成在功率芯内的高度精确定义的通孔中的CAF短路问题。

22. 发明授权

US07931830B2 Dielectric composition for use in circuitized substrates and circuitized substrate including same 有权
标题翻译：用于电路化基板和包括其的电路化基板的介电组合物
公开(公告)号：US07931830B2
公开(公告)日：2011-04-26
申请号：US11265287
申请日：2005-11-03
申请人： Robert M. Japp , Voya R. Markovich , Kostas I. Papathomas
发明人： Robert M. Japp , Voya R. Markovich , Kostas I. Papathomas
IPC分类号： H01B3/24 , H01L29/51
CPC分类号： H05K1/0373 , C08J5/24 , C08J2363/04 , H01B3/00 , H01B3/40 , H05K3/4602 , H05K2201/0209 , H05K2201/0239
摘要： A dielectric composition which is adapted for combining with a supporting material ( e.g., fiber-glass cloth) to form a dielectric layer usable in circuitized such as PCBs, chip carriers and the like. As such a layer, it includes a resin, a predetermined percentage by weight of a filler, and, significantly, only a minor amount of bromine. A circuitized substrate comprised of one or more of these dielectric layers and one or more conductive layers is also provided.
摘要翻译：一种电介质组合物，其适于与支撑材料（例如玻璃纤维布）组合以形成可用于诸如PCB，芯片载体等的电路化的电介质层。作为这样的层，其包括树脂，预定重量百分比的填料，以及明显仅少量的溴。还提供了由这些电介质层中的一个或多个以及一个或多个导电层构成的电路化衬底。

23. 发明授权

US07329446B2 Drill stack formation 有权
标题翻译：钻垛堆积
公开(公告)号：US07329446B2
公开(公告)日：2008-02-12
申请号：US10691882
申请日：2003-10-23
申请人： Robert M. Japp , Gregory A. Kevern , Francis S. Poch
发明人： Robert M. Japp , Gregory A. Kevern , Francis S. Poch
IPC分类号： B32B38/04 , B32B9/00 , B32B3/10 , B32B15/04
CPC分类号： B32B7/12 , B23B35/00 , B23B2222/21 , B23B2222/41 , B23B2222/64 , B23B2240/21 , B32B7/06 , B32B15/01 , B32B15/04 , B32B15/20 , H05K3/0047 , H05K3/44 , H05K2203/1536 , Y10T83/0476 , Y10T156/1057 , Y10T156/1184 , Y10T408/03 , Y10T428/12569 , Y10T428/14 , Y10T428/1495 , Y10T428/24273 , Y10T428/24322 , Y10T428/28 , Y10T428/2804
摘要： The present invention provides a structure. The structure includes a stack of sheets. Successive sheets in each pair of successive sheets of the stack are coupled to each other by a removable adhesive. The removable adhesive is also disposed on top and bottom surfaces of the stack so as to respectively couple first and second layers to the cop and bottom surfaces of the stack.
摘要翻译：本发明提供一种结构。该结构包括一叠纸。堆叠的每对连续片中的连续片材通过可移除的粘合剂彼此连接。可拆卸粘合剂也设置在堆叠的顶表面和底表面上，以便将第一层和第二层分别耦合到堆叠的掩模和底表面。

24. 发明授权

US06955849B2 Method and structure for small pitch z-axis electrical interconnections 失效
标题翻译：小间距z轴电气互连的方法和结构
公开(公告)号：US06955849B2
公开(公告)日：2005-10-18
申请号：US10854598
申请日：2004-05-26
申请人： Brian E. Curcio , Frank D. Egitto , Robert M. Japp , Thomas R. Miller , Manh-Quan T. Nguyen , Douglas O. Powell
发明人： Brian E. Curcio , Frank D. Egitto , Robert M. Japp , Thomas R. Miller , Manh-Quan T. Nguyen , Douglas O. Powell
IPC分类号： H01L21/48 , H05K3/40 , H05K3/46 , B32B3/00 , B32B7/12
CPC分类号： H01L21/486 , H05K3/4069 , H05K3/4614 , H05K3/462 , H05K2201/09536 , H05K2201/096 , H05K2203/0191 , H05K2203/0264 , H05K2203/061 , H05K2203/1152 , Y10S438/976 , Y10T29/49165 , Y10T428/24917 , Y10T428/28 , Y10T428/2804 , Y10T428/2839 , Y10T428/2848
摘要： A method for producing small pitch z-axis electrical interconnections in layers of dielectric materials which are applied to printed wiring boards and diverse electronic packages. A method for parallel fabrication of intermediate structures which are subsequently jointed to form a final structure. In addition there is provided a z-interconnected electrical structure, employing dielectric materials such as resin coated copper, employable in the manufacture of diverse type of electronic packages, including printed wiring boards (PWBs), substrates, multi-chip modules and the like.
摘要翻译：一种用于在印刷电路板和各种电子封装上施加介电材料层的小间距z轴电互连的方法。一种用于平行制造中间结构的方法，其随后连接以形成最终结构。此外，提供了一种采用诸如树脂涂覆铜之类的介电材料的z互连电结构，可用于制造包括印刷线路板（PWB），基板，多芯片模块等的各种类型的电子封装。

25. 发明授权

US06944946B2 Porous power and ground planes for reduced PCB delamination and better reliability 失效
标题翻译：多功能电源和接地平面可降低PCB分层和更好的可靠性
公开(公告)号：US06944946B2
公开(公告)日：2005-09-20
申请号：US10430989
申请日：2003-05-06
申请人： Robert M. Japp , Mark D. Poliks
发明人： Robert M. Japp , Mark D. Poliks
IPC分类号： H05K1/02 , H05K3/38 , H05K3/42 , H05K3/46 , H01K3/10
CPC分类号： H05K3/38 , H05K3/429 , H05K3/4641 , H05K2201/0116 , H05K2201/0281 , H05K2201/029 , H05K2201/0769 , H05K2201/09309 , H05K2201/09681 , H05K2203/1131 , Y10S428/901 , Y10T29/49002 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , Y10T156/1052 , Y10T428/24273 , Y10T428/24917
摘要： Power and ground planes that are used in Printed Circuit Boards (PCBs) and that comprise porous, conductive materials are disclosed. Using porous power and ground plane materials in PCBs allows liquids (e.g., water and/or other solvents) to pass through the power and ground planes, thus decreasing failures in PCBs (or PCBs used as laminate chip carriers) caused by cathodic/anodic filament growth and delamination of insulators. Porous conductive materials suitable for use in PCBs may be formed by using metal-coated organic cloths (such as polyester or liquid crystal polymers) or fabrics (such as those made from carbon/graphite or glass fibers), using metal wire mesh instead of metal sheets, using sintered metal, or making metal sheets porous by forming an array of holes in the metal sheets. Fabrics and mesh may be woven or random. If an array of holes is formed in a metal sheet, such an array may be formed with no additional processing steps than are performed using conventional PCB assembly methods.
摘要翻译：公开了在印刷电路板（PCB）中使用并且包含多孔导电材料的电源和接地层。在PCB中使用多孔电源和接地平面材料可以使液体（例如水和/或其他溶剂）通过电源和接地层，从而减少由阴极/阳极细丝引起的PCB（或PCBs用作层压芯片载体）的故障绝缘子的生长和分层。适用于PCB的多孔导电材料可以通过使用金属涂布的有机布（例如聚酯或液晶聚合物）或织物（例如由碳/石墨或玻璃纤维制成的那些）形成，使用金属丝网代替金属使用烧结金属，或者通过在金属板中形成孔阵列来制造多孔的金属片。织物和网可以编织或随机。如果在金属板中形成孔阵列，则可以形成这样的阵列，而不需要使用常规PCB组装方法执行的附加处理步骤。

26. 发明授权

US06496356B2 Multilayer capacitance structure and circuit board containing the same and method of forming the same 有权
标题翻译：多层电容结构和电路板含有相同的方法和其形成方法
公开(公告)号：US06496356B2
公开(公告)日：2002-12-17
申请号：US10026873
申请日：2001-12-21
申请人： Robert M. Japp , John M. Lauffer , Konstantinos I. Papathomas
发明人： Robert M. Japp , John M. Lauffer , Konstantinos I. Papathomas
IPC分类号： H01G4228
CPC分类号： H05K1/162 , H05K3/429 , H05K3/4611 , H05K3/4641 , H05K2201/0209 , H05K2201/0355 , H05K2201/09309 , H05K2203/0759
摘要： A method of forming a capacitive core structure and of forming a circuitized printed wiring board from the core structure and the resulting structures are provided. The capacitive core structure is formed by providing a central conducting plane of a sheet of conductive material and forming at least one clearance hole in the central conducting plane. First and second external conducting planes are laminated to opposite sides of the ground plane with a film of dielectric material between each of the first and second external planes and the central conducting plane. At least one clearance hole is formed in each of the first and second external planes. A circuitized wiring board structure can be formed by laminating a capacitive core structure between two circuitized structures. The invention also relates to the structures formed by these methods.
摘要翻译：提供了一种从芯结构形成电容性芯结构和形成电路化印刷线路板的方法及其结构。通过提供导电材料片的中心导电平面并在中心导电平面中形成至少一个间隙孔来形成电容芯结构。第一和第二外部导电平面在第一和第二外部平面之间的介电材料膜和中心导电平面之间层压到接地平面的相对侧。在第一和第二外部平面的每一个中形成至少一个间隙孔。可以通过在两个电路化结构之间层叠电容性芯结构来形成电路化布线板结构。本发明还涉及通过这些方法形成的结构。

27. 发明授权

US06373717B1 Electronic package with high density interconnect layer 有权
公开(公告)号：US06373717B1
公开(公告)日：2002-04-16
申请号：US09540172
申请日：2000-03-31
申请人： Francis J. Downes, Jr. , Donald S. Farquhar , Elizabeth Foster , Robert M. Japp , Gerald W. Jones , John S. Kresge , Robert D. Sebesta , David B. Stone , James R. Wilcox
发明人： Francis J. Downes, Jr. , Donald S. Farquhar , Elizabeth Foster , Robert M. Japp , Gerald W. Jones , John S. Kresge , Robert D. Sebesta , David B. Stone , James R. Wilcox
IPC分类号： H05K118
CPC分类号： H05K3/4641 , H01L21/4853 , H01L23/3735 , H01L23/49822 , H01L2224/16225 , H01L2924/00014 , H01L2924/01004 , H01L2924/01019 , H01L2924/01046 , H01L2924/01068 , H01L2924/01078 , H01L2924/01322 , H01L2924/12044 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H05K1/114 , H05K3/429 , H05K3/4602 , H05K3/4608 , H05K3/4623 , H05K3/4626 , H05K3/4632 , H05K3/4688 , H05K2201/0141 , H05K2201/0191 , H05K2201/068 , H05K2201/09509 , H05K2201/09536 , H05K2201/09554 , H05K2201/0959 , H05K2201/096 , H05K2201/10378 , Y10T29/49155 , Y10T29/49165 , H01L2224/0401
摘要： An electronic package, and method of making the electronic package, is provided. The package includes a semiconductor chip and an multi-layered interconnect structure having a high density interconnect layer such as an allylated surface layer. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip. The electronic package further includes a dielectric material having an effective modulus to assure sufficient compliancy of the multi-layered interconnect structure during operation. The allylated surface layer has the property of being able to withstand thermal stresses that arise during thermal cycling operation of the electronic package.

28. 发明授权

US07416972B2 Method of making same low moisture absorptive circuitized substrave with reduced thermal expansion 有权
标题翻译：制造具有降低的热膨胀的相同的低吸湿电路化子串的方法
公开(公告)号：US07416972B2
公开(公告)日：2008-08-26
申请号：US11730942
申请日：2007-04-05
申请人： Robert M. Japp , Irving Memis , Kostas I. Papathomas
发明人： Robert M. Japp , Irving Memis , Kostas I. Papathomas
IPC分类号： H01L21/4763
CPC分类号： H01L23/3735 , H01L23/145 , H01L23/3733 , H01L23/4922 , H01L23/49822 , H01L23/49827 , H01L23/564 , H01L2224/16225 , H01L2924/15311 , H05K1/0366 , H05K1/0373 , H05K3/4602 , H05K3/4626 , H05K3/4652 , H05K3/4655 , H05K3/4688 , H05K2201/0209 , H05K2201/0278 , H05K2201/068
摘要： A method of making a circuitized substrate including a composite layer including a first dielectric sub-layer including a plurality of fibers having a low coefficient of thermal expansion and a second dielectric sub-layer of a low moisture absorptivity resin, the second dielectric sub-layer not including continuous or semi-continuous fibers or the like as part thereof. The substrate further includes at least one electrically conductive layer as part thereof.
摘要翻译：一种制造电路化基板的方法，所述电路化基板包括复合层，所述复合层包括具有低热膨胀系数的多个纤维的第一介电子层和低吸湿性树脂的第二介电子层，所述第二介电子层不包括连续或半连续纤维等作为其一部分。衬底还包括至少一个作为其一部分的导电层。

29. 发明申请

US20080191353A1 Multilayered circuitized substrate with p-aramid dielectric layers and method of making same 失效
标题翻译：具有对芳族聚酰胺介电层的多层电路基板及其制造方法
公开(公告)号：US20080191353A1
公开(公告)日：2008-08-14
申请号：US12081042
申请日：2008-04-10
申请人： Robert M. Japp , Voya R. Markovich , Kostas I. Papathomas , Mark D. Poliks
发明人： Robert M. Japp , Voya R. Markovich , Kostas I. Papathomas , Mark D. Poliks
IPC分类号： H01L23/485 , H05K3/30
CPC分类号： H01L23/145 , H01L23/3733 , H01L23/3735 , H01L23/4922 , H01L23/49822 , H01L23/49827 , H01L23/564 , H01L2924/0002 , H01L2924/12044 , H05K1/0366 , H05K1/0373 , H05K3/4602 , H05K3/4626 , H05K3/4652 , H05K3/4655 , H05K3/4688 , H05K2201/0209 , H05K2201/0278 , H05K2201/068 , Y10T29/4913 , Y10T156/10 , H01L2924/00
摘要： A multilayered circuitized substrate including a plurality of dielectric layers each comprised of a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin including an inorganic filler but not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on a first of the dielectric layers. A method of making this substrate is also provided.
摘要翻译：一种多层电路化基板，包括多个介电层，每个电介质层由浸渍有不含卤素的低吸湿性树脂的对芳族聚酰胺纸构成，所述不含卤素的低吸湿性树脂包括无机填料，但不包括连续或半连续的玻璃纤维作为其一部分，电路层位于第一介电层上。还提供了制造该基板的方法。

30. 发明授权

US06722031B2 Method for making printed circuit board having low coefficient of thermal expansion power/ground plane 有权
标题翻译：制造具有低热膨胀系数/印刷电路板的方法
公开(公告)号：US06722031B2
公开(公告)日：2004-04-20
申请号：US10012426
申请日：2001-12-07
申请人： Robert M. Japp , Mark D. Poliks
发明人： Robert M. Japp , Mark D. Poliks
IPC分类号： H01K310
CPC分类号： H05K3/4641 , H05K1/0366 , H05K2201/0141 , H05K2201/0158 , H05K2201/0278 , H05K2201/0281 , H05K2201/029 , H05K2201/0323 , H05K2201/068 , H05K2201/09309 , Y10S428/901 , Y10T29/49126 , Y10T29/49165
摘要： Conductive materials that have low coefficients of thermal expansion (CTEs) and that are used for power and ground planes are disclosed. Fibrous materials (such as carbon, graphite, glass, quartz, polyethylene, and liquid crystal polymer fibers) with low CTEs are metallized to provide a resultant conductive material with a low CTE. Such fibers may be metallized in their individual state and then formed into a fabric, or these materials may be formed into a fabric and then metallized or a combination of both metallizations may be used. In addition, a graphite or carbon sheet may be metallized on one or both sides to provide a material that has a low CTE and high conductivity. These metallized, low CTE power and ground planes may be laminated with other planes/cores into a composite, or laminated into a core which is then laminated with other planes/cores into a composite. The resultant composite may be used for printed circuit boards (PCBs) or PCBs used as laminate chip carriers.
摘要翻译：公开了具有低热膨胀系数（CTE）并且用于电力和接地平面的导电材料。具有低CTE的纤维材料（例如碳，石墨，玻璃，石英，聚乙烯和液晶聚合物纤维）被金属化以提供具有低CTE的所得导电材料。这样的纤维可以以其单独状态进行金属化，然后形成织物，或者这些材料可以形成织物，然后金属化，或者可以使用两种金属化的组合。此外，石墨或碳片可以在一侧或两侧金属化，以提供具有低CTE和高导电性的材料。这些金属化的低CTE功率和接地层可以与其它平面/芯层压成复合材料，或者层压成芯，然后将其与其它平面/芯层叠合成复合材料。所得的复合材料可用于印刷电路板（PCB）或用作层压芯片载体的PCB。

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