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21. 发明授权

US09269896B2 Confined defect profiling within resistive random memory access cells 有权
标题翻译：电阻式随机存储器存取单元中的限制缺陷分析
公开(公告)号：US09269896B2
公开(公告)日：2016-02-23
申请号：US14519376
申请日：2014-10-21
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Yun Wang , Vidyut Gopal , Chien-Lan Hsueh
IPC分类号： H01L45/00 , G11C13/00
CPC分类号： H01L45/10 , G11C13/0002 , G11C13/0007 , G11C2213/15 , G11C2213/51 , G11C2213/56 , G11C2213/71 , G11C2213/77 , H01L45/08 , H01L45/1253 , H01L45/1266 , H01L45/145 , H01L45/146 , H01L45/1616 , H01L45/1625 , H01L45/1641
摘要： Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A stack including a defect source layer, a defect blocking layer, and a defect acceptor layer disposed between the defect source layer and the defect blocking layer may be subjected to annealing. During the annealing, defects are transferred in a controllable manner from the defect source layer to the defect acceptor layer. At the same time, the defects are not transferred into the defect blocking layer thereby creating a lowest concentration zone within the defect acceptor layer. This zone is responsible for resistive switching. The precise control over the size of the zone and the defect concentration within the zone allows substantially improvement of resistive switching characteristics of the ReRAM cell. In some embodiments, the defect source layer includes aluminum oxynitride, the defect blocking layer includes titanium nitride, and the defect acceptor layer includes aluminum oxide.
摘要翻译：提供了电阻随机存取存储器（ReRAM）单元及其制造方法。可以对包括缺陷源层，缺陷阻挡层和设置在缺陷源层和缺陷阻挡层之间的缺陷受主层的堆叠进行退火。在退火过程中，缺陷以可控方式从缺陷源层转移到缺陷受体层。同时，缺陷不会转移到缺陷阻挡层中，从而在缺陷受体层内形成最低浓度区。该区域负责电阻交换。精确控制区域的尺寸和区域内的缺陷浓度允许ReRAM单元的电阻开关特性得到显着改善。在一些实施例中，缺陷源层包括氮氧化铝，缺陷阻挡层包括氮化钛，缺陷受主层包括氧化铝。

22. 发明申请

US20160019960A1 OPERATION MODES FOR ADJUSTABLE RESISTANCE BIT LINE STRUCTURES 审中-公开
标题翻译：可调阻力位线结构的运行模式
公开(公告)号：US20160019960A1
公开(公告)日：2016-01-21
申请号：US14715575
申请日：2015-05-18
申请人： SANDISK 3D LLC
发明人： Perumal Ratnam , Christopher Petti , Tianhong Yan
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G06F11/1048 , G11C7/12 , G11C7/18 , G11C13/0002 , G11C13/0007 , G11C13/0021 , G11C13/0026 , G11C13/0028 , G11C13/0033 , G11C13/0069 , G11C13/0097 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/26 , G11C29/025 , G11C29/028 , G11C2029/1204 , G11C2213/71 , G11C2216/10 , H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L29/786 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/122 , H01L45/1226 , H01L45/1246 , H01L45/146
摘要： Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.
摘要翻译：描述了在存储器操作期间通过存储器阵列的未选择的存储单元减少泄漏电流的方法。在一些情况下，可以通过将连接到未选择的存储器单元的可调电阻位线结构设置为非导通状态来减小通过存储器阵列的未选择存储单元的漏电流。可调电阻位线结构可以包括位线结构，其中可以通过向位线结构的选择栅极部分施加电压来调整位线结构的本征（或近固有）多晶硅部分的电阻其不直接连接到本征多晶硅部分。本征多晶硅部分可以基于施加到选择栅极部分的电压而被设置为导通状态或非导通状态。

23. 发明申请

US20160019953A1 SETTING CHANNEL VOLTAGES USING A DUMMY WORD LINE 有权
标题翻译：使用DUMMY WORD LINE设置信道电压
公开(公告)号：US20160019953A1
公开(公告)日：2016-01-21
申请号：US14715579
申请日：2015-05-18
申请人： SANDISK 3D LLC
发明人： Perumal Ratnam , Christopher Petti , Tianhong Yan
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G06F11/1048 , G11C7/12 , G11C7/18 , G11C13/0002 , G11C13/0007 , G11C13/0021 , G11C13/0026 , G11C13/0028 , G11C13/0033 , G11C13/0069 , G11C13/0097 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/26 , G11C29/025 , G11C29/028 , G11C2029/1204 , G11C2213/71 , G11C2216/10 , H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L29/786 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/122 , H01L45/1226 , H01L45/1246 , H01L45/146
摘要： Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.
摘要翻译：描述了在存储器操作期间通过存储器阵列的未选择的存储单元减少泄漏电流的方法。在一些情况下，可以通过将连接到未选择的存储器单元的可调电阻位线结构设置为非导通状态来减小通过存储器阵列的未选择存储单元的漏电流。可调电阻位线结构可以包括位线结构，其中可以通过向位线结构的选择栅极部分施加电压来调整位线结构的本征（或近固有）多晶硅部分的电阻其不直接连接到本征多晶硅部分。本征多晶硅部分可以基于施加到选择栅极部分的电压而被设置为导通状态或非导通状态。

24. 发明授权

US09230985B1 Vertical TFT with tunnel barrier 有权
标题翻译：带隧道屏障的垂直TFT
公开(公告)号：US09230985B1
公开(公告)日：2016-01-05
申请号：US14515054
申请日：2014-10-15
申请人： SanDisk 3D LLC
发明人： Ming-Che Wu , Peter Rabkin , Tim Chen
IPC分类号： H01L21/336 , H01L27/115 , H01L29/786 , H01L29/08 , H01L29/66 , H01L21/02
CPC分类号： H01L27/11582 , H01L29/0895 , H01L29/66742 , H01L29/78618 , H01L29/78642
摘要： A vertically oriented thin film transistor (TFT) having a tunnel barrier is disclosed. The tunnel barrier may be formed from a dielectric such as silicon oxide or hafnium oxide. The vertically oriented TFT selection device with tunnel barrier may serve as a selection device in a 3D memory array. The vertically oriented TFT may be used to connect/disconnect a global bit line to/from a vertical bit line in a 3D memory array. The vertically oriented TFT may be used to connect/disconnect a source line to/from a channel of a vertical NAND string in a 3D memory array. A vertical TFT with tunnel barrier has a high breakdown voltage, low leakage current, and high on current. The tunnel barrier can be at the top junction or bottom junction of the TFT.
摘要翻译：公开了一种具有隧道势垒的垂直取向薄膜晶体管（TFT）。隧道势垒可以由诸如氧化硅或氧化铪的电介质形成。具有隧道势垒的垂直取向的TFT选择装置可以用作3D存储器阵列中的选择装置。可以使用垂直取向的TFT来连接/断开与3D存储器阵列中的垂直位线的全局位线。垂直取向的TFT可以用于将源极线连接到/离开3D存储器阵列中的垂直NAND串的通道。具有隧道势垒的垂直TFT具有高击穿电压，低漏电流和高导通电流。隧道势垒可以在TFT的顶部结或底部结。

25. 发明授权

US09214243B2 Three-dimensional nonvolatile memory and method of fabrication 有权
标题翻译：三维非易失性存储器及其制造方法
公开(公告)号：US09214243B2
公开(公告)日：2015-12-15
申请号：US14270409
申请日：2014-05-06
申请人： SanDisk 3D LLC
发明人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , Paul Michael Farmwald , James M. Cleeves
IPC分类号： G11C11/36 , G11C17/06 , G11C11/56 , G11C13/00 , G11C17/14 , G11C17/16 , H01L27/10 , H01L27/102 , H01L45/00 , H01L27/24
CPC分类号： G11C17/06 , G11C11/5692 , G11C13/003 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2481 , H01L45/1233 , H01L45/16
摘要： A three-dimensional memory is provided that includes a first memory level and a second memory level monolithically formed above the first memory level. The first memory level includes a first steering element coupled in series with and vertically stacked above or below a first non-volatile state change element. The second memory level includes a second steering element coupled in series with and vertically stacked above or below a second non-volatile state change element. Other aspects are also provided.
摘要翻译：提供三维存储器，其包括在第一存储器级上方单片地形成的第一存储器级和第二存储器级。第一存储器级包括与第一非易失性状态改变元件串联并垂直堆叠的第一操作元件。第二存储器级包括与第二非易失性状态改变元件串联并且垂直地堆叠在第二非易失性状态改变元件上方或下方的第二操作元件。还提供其他方面。

26. 发明授权

US09196362B2 Multiple layer forming scheme for vertical cross point reram 有权
标题翻译：垂直交叉点多层形成方案
公开(公告)号：US09196362B2
公开(公告)日：2015-11-24
申请号：US14246053
申请日：2014-04-05
申请人： SanDisk 3D LLC
发明人： Chang Siau , Tianhong Yan
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/77
摘要： Methods for forming non-volatile storage elements in a non-volatile storage system are described. In some embodiments, during a forming operation, a cross-point memory array may be biased such that waste currents are minimized or eliminated. In one example, the memory array may be biased such that a first word line comb is set to a first voltage, a second word line comb interdigitated with the first word line comb is set to the first voltage, and selected vertical bit lines are set to a second voltage such that a forming voltage is applied across non-volatile storage elements to be formed. In some embodiments, a memory array may include a plurality of word line comb layers and a forming operation may be concurrently performed on non-volatile storage elements on all of the plurality of word line comb layers or a subset of the plurality of word line comb layers.
摘要翻译：描述了在非易失性存储系统中形成非易失性存储元件的方法。在一些实施例中，在成形操作期间，可以偏置交叉点存储器阵列，使得浪费电流被最小化或消除。在一个示例中，存储器阵列可以被偏置，使得第一字线梳被设置为第一电压，与第一字线梳交织的第二字线梳被设置为第一电压，并且选择的垂直位线被设置到第二电压，使得在要形成的非易失性存储元件上施加形成电压。在一些实施例中，存储器阵列可以包括多个字线梳状层，并且可以在所有多个字线梳状层上的非易失性存储元件上同时执行形成操作，或者多个字线梳的子集层。

27. 发明申请

US20150325310A1 DIELECTRIC-BASED MEMORY CELLS HAVING MULTI-LEVEL ONE-TIME PROGRAMMABLE AND BI-LEVEL REWRITEABLE OPERATING MODES AND METHODS OF FORMING THE SAME 有权
标题翻译：具有多级一次可编程和双层可操作操作模式的基于介质的存储器单元及其形成方法
公开(公告)号：US20150325310A1
公开(公告)日：2015-11-12
申请号：US14804126
申请日：2015-07-20
申请人： SanDisk 3D LLC
发明人： Abhijit Bandyopadhyay , Tanmay Kumar , Scott Brad Herner , Christopher J. Petti , Roy E. Scheuerlein
IPC分类号： G11C17/16 , G11C17/18 , G11C11/56
CPC分类号： G11C17/165 , G11C11/5692 , G11C17/18 , H01L27/1021 , H01L27/11206 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L29/8615 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/1675
摘要： A method of programming a memory cell is provided. The memory cell includes a memory element having a first conductive material layer, a first dielectric material layer above the first conductive material layer, a second conductive material layer above the first dielectric material layer, a second dielectric material layer above the second conductive material layer, and a third conductive material layer above the second dielectric material layer. One or both of the first and second conductive material layers comprises a stack of a metal material layer and a highly doped semiconductor material layer. The memory cell has a first memory state upon fabrication corresponding to a first read current. The method includes applying a first programming pulse to the memory cell with a first current limit. The first programming pulse programs the memory cell to a second memory state that corresponds to a second read current greater than the first read current.
摘要翻译：提供了一种编程存储器单元的方法。存储单元包括具有第一导电材料层，在第一导电材料层上方的第一介电材料层，第一介电材料层上方的第二导电材料层，第二导电材料层上方的第二介电材料层的存储元件，以及在第二介电材料层上方的第三导电材料层。第一和第二导电材料层中的一个或两个包括金属材料层和高掺杂半导体材料层的叠层。存储单元在制造时具有对应于第一读取电流的第一存储器状态。该方法包括以第一电流限制对存储器单元施加第一编程脉冲。第一编程脉冲将存储器单元编程为对应于大于第一读取电流的第二读取电流的第二存储器状态。

28. 发明申请

US20150325292A1 THREE DIMENSIONAL NON-VOLATILE STORAGE WITH CONNECTED WORD LINES 有权
标题翻译：具有连接字线的三维非易失性存储
公开(公告)号：US20150325292A1
公开(公告)日：2015-11-12
申请号：US14746003
申请日：2015-06-22
申请人： SanDisk 3D LLC
发明人： Roy E. Scheuerlein
IPC分类号： G11C13/00
CPC分类号： G11C13/0033 , G11C5/025 , G11C8/08 , G11C13/0002 , G11C13/0026 , G11C13/0028 , G11C13/0069 , H01L27/0688 , H01L27/115 , H01L27/2454 , H01L27/2463 , H01L27/2481 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/165 , H01L45/1683
摘要： A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.
摘要翻译：适用于响应于在其上施加电压差而可逆地改变电导水平的存储器元件的三维阵列。存储元件跨越位于半导体衬底上方不同距离的多个平面形成。所有平面的存储元件所连接的位线从衬底垂直定向并穿过多个平面。

29. 发明授权

US09178151B2 Work function tailoring for nonvolatile memory applications 有权
标题翻译：非易失性存储器应用的工作功能定制
公开(公告)号：US09178151B2
公开(公告)日：2015-11-03
申请号：US14078838
申请日：2013-11-13
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Yun Wang , Tony P. Chiang , Imran Hashim
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/1608 , H01L27/2463 , H01L45/04 , H01L45/065 , H01L45/10 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1616 , H01L45/1633 , H01L45/1641
摘要： Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.
摘要翻译：本发明的实施例一般涉及具有设置在至少一个电极和形成在非易失性存储器件中的可变电阻层之间的界面层结构的电阻式开关非易失性存储器件及其形成方法。通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。在电阻式开关非易失性存储器件的一种结构中，界面层结构包括钝化区域，界面耦合区域和/或可变电阻层接口区域，其被配置为调整非易失性存储器件的性能，例如降低形成器件的开关电流并降低器件的成型电压，并降低从一个成形器件到另一个器件的性能变化。

30. 发明申请

US20150255619A1 Vertical Thin Film Transistor Selection Devices And Methods Of Fabrication 有权
标题翻译：垂直薄膜晶体管选择器件及其制作方法
公开(公告)号：US20150255619A1
公开(公告)日：2015-09-10
申请号：US14197985
申请日：2014-03-05
申请人： SanDisk 3D LLC
发明人： Seiji Shimabukuro
IPC分类号： H01L29/786 , H01L29/66 , H01L27/115
CPC分类号： H01L29/78642 , G11C13/0002 , G11C13/0023 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/77 , H01L23/535 , H01L27/115 , H01L27/2454 , H01L27/249 , H01L29/42392 , H01L29/66666 , H01L29/66742 , H01L45/04 , H01L45/1226 , H01L45/142 , H01L45/143 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/16
摘要： Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and method of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. Beneath each gate, a single gap fill dielectric layer extends vertically from a lower surface of the gate, at least partially separating the gate from the underlying global bit line. Between horizontally adjacent pillars, this same dielectric layer extends from its same lower level beneath the gates vertically to a level of the upper source/drain region.
摘要翻译：描述了具有垂直取向薄膜晶体管（TFT）选择器件的三维（3D）非易失性存储器阵列及其制造方法。垂直取向的TFT可以用作垂直位线选择装置，以将全局位线耦合到垂直位线。选择器件柱包括主体和上部和下部源极/漏极区域。至少一个栅极通过栅极电介质与选择器件柱水平分离。在每个栅极下方，单个间隙填充介电层从栅极的下表面垂直延伸，至少部分地将栅极与下面的全局位线分开。在水平相邻的柱之间，该相同的电介质层从栅极下方的相同较低电平垂直延伸到上部源极/漏极区的一个电平。

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