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21. 发明授权

US08327228B2 Home agent data and memory management 失效
标题翻译：家庭代理数据和内存管理
公开(公告)号：US08327228B2
公开(公告)日：2012-12-04
申请号：US12571381
申请日：2009-09-30
申请人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
发明人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
IPC分类号： G11C29/00
CPC分类号： G06F12/0817
摘要： Methods and apparatus relating to home agent data and memory management are described. In one embodiment, a scrubber logic corrects an error at a location in a memory corresponding to a target address by writing back the corrected version of data to the target location. In an embodiment, a map out logic maps out an index or way of a directory cache in response to a number of errors, corresponding to the directory cache, exceeding a threshold value. Other embodiments are also disclosed.
摘要翻译：描述与归属代理数据和存储器管理有关的方法和装置。在一个实施例中，洗涤器逻辑通过将校正的数据版本写回到目标位置来校正与目标地址相对应的存储器中的位置处的错误。在一个实施例中，映射逻辑响应于对应于目录高速缓存的多个错误超过阈值来映射目录高速缓存的索引或方式。还公开了其他实施例。

22. 发明申请

US20110078384A1 MEMORY MIRRORING AND MIGRATION AT HOME AGENT 有权
标题翻译：在家庭代理记忆转移和移动
公开(公告)号：US20110078384A1
公开(公告)日：2011-03-31
申请号：US12571382
申请日：2009-09-30
申请人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
发明人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
IPC分类号： G06F12/08 , G06F12/00 , G06F12/16
CPC分类号： G06F12/0817
摘要： Methods and apparatus relating to memory mirroring and migration at a Home Agent (HA) are described. In one embodiment, a home agent may mirror its data at a slave agent. In some embodiments, a bit in a directory may indicate status of cache lines. Other embodiments are also disclosed.
摘要翻译：描述了与归属代理（HA）的内存镜像和迁移有关的方法和设备。在一个实施例中，归属代理可以在从属代理处镜像其数据。在一些实施例中，目录中的位可以指示高速缓存行的状态。还公开了其他实施例。

23. 发明申请

US20100332767A1 Controllably Exiting An Unknown State Of A Cache Coherency Directory 有权
标题翻译：可控地退出高速缓存一致性目录的未知状态
公开(公告)号：US20100332767A1
公开(公告)日：2010-12-30
申请号：US12492280
申请日：2009-06-26
申请人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
发明人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0817 , G06F9/5033 , G06F2212/1032
摘要： In one embodiment, a method includes receiving a read request from a first caching agent and if a directory entry associated with the request is in an unknown state, an invalidating snoop message is sent to at least one other caching agent to invalidate information in a cache location of the other caching agent corresponding to the location of the read request, to enable setting of the directory entry into a known state. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，一种方法包括从第一高速缓存代理接收读取请求，并且如果与请求相关联的目录条目处于未知状态，则向至少一个其他高速缓存代理发送无效侦听消息以使高速缓存中的信息无效与读取请求的位置相对应的其他高速缓存代理的位置，以使目录项进入已知状态。描述和要求保护其他实施例。

24. 发明授权

US5603004A Method for decreasing time penalty resulting from a cache miss in a multi-level cache system 失效
标题翻译：用于减少由多级缓存系统中的高速缓存未命中引起的时间损失的方法
公开(公告)号：US5603004A
公开(公告)日：1997-02-11
申请号：US196042
申请日：1994-02-14
申请人： Gordon Kurpanek , Eric Delano , Michael A. Buckley , William R. Bryg
发明人： Gordon Kurpanek , Eric Delano , Michael A. Buckley , William R. Bryg
IPC分类号： G06F12/08 , G06F12/12 , G06F12/00
CPC分类号： G06F12/0897 , G06F12/0864 , G06F12/12 , G06F12/0862
摘要： A cache system buffers data stored in a main memory and utilized by a processor. The cache system includes a first cache, a second cache, a first transfer channel, a second transfer channel and a third transfer channel. The first cache is fully associative. The second cache is directly mapped. The first transfer channel transfers data lines from the main memory to the first cache. The second transfer channel transfers data lines from the first cache to the second cache. The third transfer channel transfers data lines from the second cache to the main memory. Accesses of data lines from the first cache and the second cache are performed in parallel.
摘要翻译：缓存系统缓冲存储在主存储器中并由处理器使用的数据。高速缓存系统包括第一高速缓存，第二高速缓存，第一传送通道，第二传送通道和第三传送通道。第一个缓存是完全关联的。第二个缓存直接映射。第一个传输通道将数据线从主存储器传输到第一个缓存。第二传输信道将数据线从第一高速缓存传送到第二高速缓存。第三传送通道将数据线从第二高速缓存传送到主存储器。并行执行来自第一高速缓存和第二高速缓存的数据线的访问。

25. 发明申请

US20110078492A1 HOME AGENT DATA AND MEMORY MANAGEMENT 失效
标题翻译：家庭代理数据和内存管理
公开(公告)号：US20110078492A1
公开(公告)日：2011-03-31
申请号：US12571381
申请日：2009-09-30
申请人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
发明人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
IPC分类号： G06F11/00 , G06F12/08 , G06F12/00
CPC分类号： G06F12/0817
摘要： Methods and apparatus relating to home agent data and memory management are described. In one embodiment, a scrubber logic corrects an error at a location in a memory corresponding to a target address by writing back the corrected version of data to the target location. In an embodiment, a map out logic maps out an index or way of a directory cache in response to a number of errors, corresponding to the directory cache, exceeding a threshold value. Other embodiments are also disclosed.
摘要翻译：描述与归属代理数据和存储器管理有关的方法和装置。在一个实施例中，洗涤器逻辑通过将校正的数据版本写回到目标位置来校正与目标地址相对应的存储器中的位置处的错误。在一个实施例中，映射逻辑响应于对应于目录高速缓存的多个错误超过阈值来映射目录高速缓存的索引或方式。还公开了其他实施例。

26. 发明授权

US07421689B2 Processor-architecture for facilitating a virtual machine monitor 失效
标题翻译：处理器架构，便于虚拟机监控
公开(公告)号：US07421689B2
公开(公告)日：2008-09-02
申请号：US10695267
申请日：2003-10-28
申请人： Jonathan K. Ross , Dale Morris , Donald C. Soltis, Jr. , Rohit Bhatia , Eric Delano
发明人： Jonathan K. Ross , Dale Morris , Donald C. Soltis, Jr. , Rohit Bhatia , Eric Delano
IPC分类号： G06F9/455
CPC分类号： G06F9/45533
摘要： Virtual-machine-monitor operation and implementation is facilitated by number of easily implemented features and extensions added to the features of a processor architecture. These features, one or more of which are used in various embodiments of the present invention, include a vmsw instruction that provides a means for transitioning between virtualization mode and non-virtualization mode without an interruption, a virtualization fault that faults on an attempt by a priority-0 routine in virtualization mode attempting to execute a privileged instruction, and a flexible highest-implemented-address mechanism to partition virtual address space into a virtualization address space and a non-virtualization address space.
摘要翻译：虚拟机监视器的操作和实现通过添加到处理器架构的特征中的容易实现的特征和扩展的数量来实现。这些特征，其中一个或多个在本发明的各种实施例中使用，包括提供用于在不中断的情况下在虚拟化模式和非虚拟化模式之间转换的手段的vmsw指令，虚拟化故障，尝试执行特权指令的虚拟化模式中的优先级0例程，以及将虚拟地址空间划分为虚拟化地址空间和非虚拟化地址空间的灵活的最高实现地址机制。

27. 发明授权

US07310751B2 Timeout event trigger generation 有权
标题翻译：超时事件触发器生成
公开(公告)号：US07310751B2
公开(公告)日：2007-12-18
申请号：US10783112
申请日：2004-02-20
申请人： Michael Tayler , Eric Delano
发明人： Michael Tayler , Eric Delano
IPC分类号： G06F11/00
CPC分类号： G06F11/076
摘要： A system is disclosed for generating a plurality of timeout event triggers in response to a plurality of kinds of timeout events. The system includes an overflow generator, which generates a plurality of overflow signals having a plurality of periods. The system also includes a plurality of trigger generators corresponding to the plurality of kinds of timeout events. Each of the plurality of trigger generators is associated with a corresponding timeout threshold value representing the minimum amount of time that must elapse for the trigger generator to generate a timeout event trigger. For each of the plurality of timeout triggers, a corresponding selection signal selects one of the plurality of periodic overflow signals. The timeout threshold corresponding to each timeout trigger is equal to the period of the corresponding selected overflow signal multiplied by the value of the corresponding control signal.
摘要翻译：公开了用于响应于多种超时事件而产生多个超时事件触发的系统。该系统包括溢出发生器，其产生具有多个周期的多个溢出信号。该系统还包括与多种超时事件对应的多个触发发生器。多个触发发生器中的每一个与相应的超时阈值相关联，该阈值表示触发器产生器必须经过的生成超时事件触发的最小时间量。对于多个超时触发中的每一个，相应的选择信号选择多个周期性溢出信号中的一个。对应于每个超时触发的超时阈值等于对应的所选溢出信号乘以相应控制信号的值的周期。

28. 发明申请

US20050240810A1 Off-chip lockstep checking 有权
标题翻译：片外锁定检查
公开(公告)号：US20050240810A1
公开(公告)日：2005-10-27
申请号：US10818994
申请日：2004-04-06
申请人： Kevin Safford , Donald Soltis , Eric Delano
发明人： Kevin Safford , Donald Soltis , Eric Delano
IPC分类号： G06F11/00 , G06F11/16 , G06K19/067
CPC分类号： G06F11/1641 , G06F11/1625 , G06F2201/845
摘要： A system is provided which includes a microprocessor comprising a first processing unit to generate a first output signal and a second processing unit to generate a second output signal, and comparison means, coupled to the microprocessor, to detect whether the first output signal differs from the second output signal.
摘要翻译：提供了一种系统，其包括微处理器，该微处理器包括产生第一输出信号的第一处理单元和用于产生第二输出信号的第二处理单元，以及耦合到微处理器的比较装置，以检测第一输出信号是否与第二输出信号。

29. 发明申请

US20050108509A1 Error detection method and system for processors that employs lockstepped concurrent threads 审中-公开
标题翻译：使用锁定并发线程的处理器的错误检测方法和系统
公开(公告)号：US20050108509A1
公开(公告)日：2005-05-19
申请号：US10714093
申请日：2003-11-13
申请人： Kevin Safford , Donald Soltis , Stephen Undy , James Gibson , Eric Delano
发明人： Kevin Safford , Donald Soltis , Stephen Undy , James Gibson , Eric Delano
IPC分类号： G06F9/318 , G06F9/38 , G06F11/16 , G06F15/00
CPC分类号： G06F9/3885 , G06F9/30181 , G06F9/3863
摘要： A processor that includes an in-order execution architecture for executing at least two instructions per cycle (e.g., 2n instructions are processed per cycle, where n is an integer greater than or equal to one) and at least two symmetric execution units. The processor includes an instruction fetch unit for fetching n instructions (where n is an integer greater than or equal to one) and an instruction decoder for decoding the n instruction. The error detection mechanism includes duplication hardware for duplicating the n instructions into a first bundle of n instructions and a second bundle of n instructions. A first execution unit for executing the first bundle of instructions in a first execution cycle, and a second symmetric execution unit for executing the second bundle of instructions in the first execution cycle are provided. The error detection mechanism also includes comparison hardware for comparing the results of the first execution unit and the results of the second execution unit. The comparison hardware can have an exception unit for generating an exception (e.g., raising a fault) when the results are not the same. A commit unit is provided for committing one of the results when the results are the same.
摘要翻译：一种处理器，其包括用于每个周期执行至少两个指令的按顺序执行架构（例如，每个周期处理2n个指令，其中n是大于或等于1的整数）和至少两个对称执行单元。处理器包括用于取出n个指令（其中n是大于或等于1的整数）的指令获取单元和用于对n指令进行解码的指令解码器。错误检测机制包括用于将n个指令复制到n个指令的第一束和第n个n个指令束中的复制硬件。提供了用于在第一执行周期中执行第一指令集的第一执行单元和用于在第一执行周期中执行第二指令集的第二对称执行单元。错误检测机构还包括用于比较第一执行单元的结果和第二执行单元的结果的比较硬件。当结果不相同时，比较硬件可以具有用于产生异常（例如，引起故障）的异常单元。当结果相同时，提交提交单元用于提交结果之一。

30. 发明申请

US20050091652A1 Processor-architecture for facilitating a virtual machine monitor 失效
标题翻译：处理器架构，便于虚拟机监控
公开(公告)号：US20050091652A1
公开(公告)日：2005-04-28
申请号：US10695267
申请日：2003-10-28
申请人： Jonathan Ross , Dale Morris , Donald Soltis , Rohit Bhatia , Eric Delano
发明人： Jonathan Ross , Dale Morris , Donald Soltis , Rohit Bhatia , Eric Delano
IPC分类号： G06F9/455
CPC分类号： G06F9/45533
摘要： Virtual-machine-monitor operation and implementation is facilitated by number of easily implemented features and extensions added to the features of a processor architecture. These features, one or more of which are used in various embodiments of the present invention, include a vmsw instruction that provides a means for transitioning between virtualization mode and non-virtualization mode without an interruption, a virtualization fault that faults on an attempt by a priority-0 routine in virtualization mode attempting to execute a privileged instruction, and a flexible highest-implemented-address mechanism to partition virtual address space into a virtualization address space and a non-virtualization address space.
摘要翻译：虚拟机监视器的操作和实现通过添加到处理器架构的特征中的容易实现的特征和扩展的数量来实现。这些特征，其中一个或多个在本发明的各种实施例中使用，包括提供用于在不中断的情况下在虚拟化模式和非虚拟化模式之间转换的手段的vmsw指令，虚拟化故障，尝试执行特权指令的虚拟化模式中的优先级0例程，以及将虚拟地址空间划分为虚拟化地址空间和非虚拟化地址空间的灵活的最高实现地址机制。

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