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21. 发明授权

US09640262B2 Highly scalable single-poly non-volatile memory cell 有权
公开(公告)号：US09640262B2
公开(公告)日：2017-05-02
申请号：US14719342
申请日：2015-05-22
申请人： eMemory Technology Inc.
发明人： Te-Hsun Hsu , Chun-Hsiao Li , Hsuen-Wei Chen
IPC分类号： H01L29/788 , G11C16/08 , G11C17/16 , G11C17/18 , H01L27/112 , G11C16/10 , G11C16/26 , G11C17/04 , G11C17/08 , H01L23/528 , H01L27/06 , H01L29/10 , H01L29/49 , H01L29/93 , H01L27/11524 , H03K3/356 , G11C17/14 , G11C29/00 , H01L23/525
CPC分类号： G11C16/08 , G11C16/10 , G11C16/26 , G11C17/04 , G11C17/08 , G11C17/146 , G11C17/16 , G11C17/18 , G11C29/76 , H01L23/5252 , H01L23/528 , H01L27/0629 , H01L27/11206 , H01L27/11524 , H01L29/1079 , H01L29/4916 , H01L29/93 , H01L2924/0002 , H03K3/356182 , H01L2924/00
摘要： A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region, an isolation region separating the first OD region from the second OD region, a PMOS select transistor disposed on the first OD region, and a PMOS floating gate transistor serially connected to the select transistor and disposed on the first OD region. The PMOS floating gate transistor includes a floating gate overlying the first OD region. A memory P well is disposed in the semiconductor substrate. A memory N well is disposed in the memory P well. The memory P well overlaps with the first OD region and the second OD region. The memory P well has a junction depth that is deeper than a trench depth of the isolation region. The memory N well has a junction depth that is shallower than the trench depth of the isolation region.

22. 发明授权

US09601499B2 One-time programmable memory cell capable of reducing leakage current and preventing slow bit response, and method for programming a memory array comprising the same 有权
公开(公告)号：US09601499B2
公开(公告)日：2017-03-21
申请号：US15005012
申请日：2016-01-25
申请人： eMemory Technology Inc.
发明人： Meng-Yi Wu , Wei-Zhe Wong , Hsin-Ming Chen
IPC分类号： G11C17/14 , H01L27/112 , G11C17/16 , H01L29/78 , H01L27/10 , G11C17/18 , H01L23/525
CPC分类号： H01L27/11206 , G11C17/16 , G11C17/18 , H01L23/5252 , H01L27/101 , H01L27/11286 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A one time programmable (OTP) memory cell includes a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal and a first source terminal. The following gate transistor has a second gate terminal, a second drain terminal and a second source terminal coupled to the first drain terminal. The antifuse varactor has a third gate terminal, a third drain terminal, and a third source terminal coupled to the second drain terminal. The select gate transistor, the following gate transistor, and the antifuse varactor are formed on a substrate structure.

23. 发明授权

US09362339B2 Semiconductor elements stacked and bonded with an anisotropic conductive adhesive 有权
标题翻译：用各向异性导电粘合剂堆叠和结合的半导体元件
公开(公告)号：US09362339B2
公开(公告)日：2016-06-07
申请号：US14614961
申请日：2015-02-05
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Shunpei Yamazaki , Hiroko Abe , Yukie Nemoto , Ryoji Nomura , Mikio Yukawa
IPC分类号： H01L27/24 , B82Y10/00 , G11C13/00 , G11C17/14 , G11C17/16 , G11C17/18 , H01L21/822 , H01L27/06 , H01L45/00 , H01L23/66 , H01L27/28 , H01L51/00 , H01L27/12
CPC分类号： H01L27/2463 , B82Y10/00 , G11C13/00 , G11C13/0004 , G11C13/0014 , G11C13/0016 , G11C13/0069 , G11C17/143 , G11C17/16 , G11C17/18 , G11C2013/009 , G11C2213/77 , G11C2213/79 , H01L21/8221 , H01L23/66 , H01L27/0688 , H01L27/1266 , H01L27/2409 , H01L27/2436 , H01L27/283 , H01L45/06 , H01L45/065 , H01L45/1213 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L51/0098 , H01L2223/6677 , H01L2224/48091 , H01L2224/48137 , H01L2224/49107 , H01L2224/73265 , H01L2924/12044 , H01L2924/00014 , H01L2924/00
摘要： The invention provides a semiconductor device which is non-volatile, easily manufactured, and can be additionally written. A semiconductor device of the invention includes a plurality of transistors, a conductive layer which functions as a source wiring or a drain wiring of the transistors, and a memory element which overlaps one of the plurality of transistors, and a conductive layer which functions as an antenna. The memory element includes a first conductive layer, an organic compound layer and a phase change layer, and a second conductive layer stacked in this order. The conductive layer which functions as an antenna and a conductive layer which functions as a source wiring or a drain wiring of the plurality of transistors are provided on the same layer.
摘要翻译：本发明提供了一种非易失性，易于制造并且可另外写入的半导体器件。本发明的半导体器件包括多个晶体管，用作晶体管的源极布线或漏极布线的导电层，以及与多个晶体管之一重叠的存储元件，以及用作天线。存储元件包括第一导电层，有机化合物层和相变层，以及依次层叠的第二导电层。用作天线的导电层和用作多个晶体管的源极布线或漏极布线的导电层设置在同一层上。

24. 发明授权

US09355740B2 Semiconductor nonvolatile memory device with one-time programmable memories 有权
标题翻译：具有一次可编程存储器的半导体非易失性存储器件
公开(公告)号：US09355740B2
公开(公告)日：2016-05-31
申请号：US14491074
申请日：2014-09-19
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Koichiro Zaitsu , Kosuke Tatsumura
IPC分类号： G11C16/04 , G11C17/18 , G11C5/06 , G11C17/14
CPC分类号： G11C17/18 , G11C5/063 , G11C17/146
摘要： A semiconductor nonvolatile memory device of an embodiment includes: a plurality of transistors arranged in a matrix, the transistors in the same row being connected in series to form a transistor string having a first terminal and a second terminal; a plurality of first wiring lines each corresponding to one of the columns, and being connected to the gates of the transistors of the corresponding column; a common first electrode connected to each semiconductor region in which each transistor is disposed; and a write unit that selects one of the first wiring lines and one of the transistor strings, and applies a first voltage to the first electrode, a first write voltage to the selected first wiring line, a second voltage to the other first wiring lines, and a second write voltage to the first terminal and the second terminal of the selected transistor string in a write operation.
摘要翻译：实施例的半导体非易失性存储器件包括：以矩阵形式布置的多个晶体管，同一行中的晶体管串联连接以形成具有第一端子和第二端子的晶体管串; 多个第一布线，每一个对应于一列之一，并连接到相应列的晶体管的栅极; 连接到其中设置每个晶体管的每个半导体区域的公共第一电极; 以及写入单元，其选择所述第一布线和所述晶体管串中的一个，并将第一电压施加到所述第一电极，对所选择的第一布线施加第一写入电压，向所述其它第一布线施加第二电压，以及在写入操作中第二写入电压到所选择的晶体管串的第一端子和第二端子。

25. 发明授权

US09214243B2 Three-dimensional nonvolatile memory and method of fabrication 有权
标题翻译：三维非易失性存储器及其制造方法
公开(公告)号：US09214243B2
公开(公告)日：2015-12-15
申请号：US14270409
申请日：2014-05-06
申请人： SanDisk 3D LLC
发明人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , Paul Michael Farmwald , James M. Cleeves
IPC分类号： G11C11/36 , G11C17/06 , G11C11/56 , G11C13/00 , G11C17/14 , G11C17/16 , H01L27/10 , H01L27/102 , H01L45/00 , H01L27/24
CPC分类号： G11C17/06 , G11C11/5692 , G11C13/003 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2481 , H01L45/1233 , H01L45/16
摘要： A three-dimensional memory is provided that includes a first memory level and a second memory level monolithically formed above the first memory level. The first memory level includes a first steering element coupled in series with and vertically stacked above or below a first non-volatile state change element. The second memory level includes a second steering element coupled in series with and vertically stacked above or below a second non-volatile state change element. Other aspects are also provided.
摘要翻译：提供三维存储器，其包括在第一存储器级上方单片地形成的第一存储器级和第二存储器级。第一存储器级包括与第一非易失性状态改变元件串联并垂直堆叠的第一操作元件。第二存储器级包括与第二非易失性状态改变元件串联并且垂直地堆叠在第二非易失性状态改变元件上方或下方的第二操作元件。还提供其他方面。

26. 发明授权

US09165631B2 OTP scheme with multiple magnetic tunnel junction devices in a cell 有权
标题翻译： OTP方案在单元中具有多个磁性隧道结装置
公开(公告)号：US09165631B2
公开(公告)日：2015-10-20
申请号：US13613125
申请日：2012-09-13
申请人： Jung Pill Kim , Taehyun Kim , Sungryul Kim , Kangho Lee
发明人： Jung Pill Kim , Taehyun Kim , Sungryul Kim , Kangho Lee
IPC分类号： G11C11/16 , G11C17/00 , G11C17/02 , G11C17/16 , G11C17/14
CPC分类号： G11C11/1675 , G11C11/161 , G11C11/1673 , G11C17/02 , G11C17/146 , G11C17/165 , G11C2213/78
摘要： A one time programming (OTP) apparatus unit cell includes multiple magnetic tunnel junctions (MTJs) and a shared access transistor coupled between the multiple MTJs and a fixed potential. Each of the multiple MTJs in a unit cell can be coupled to separate programming circuitry and/or separate sense amplifier circuitry so that they can be individually programmed and/or individually sensed. A logical combination from the separate sense amplifiers can be generated as an output of the unit cell.
摘要翻译：一次编程（OTP）装置单元包括多个磁隧道结（MTJ）和耦合在多个MTJ之间的共享存取晶体管和固定电位。单位单元中的多个MTJ中的每一个可以耦合到单独的编程电路和/或单独的读出放大器电路，使得它们可以被单独编程和/或单独感测。可以产生来自单独读出放大器的逻辑组合作为单位单元的输出。

27. 发明授权

US09093149B2 Low cost programmable multi-state device 有权
标题翻译：低成本可编程多态器件
公开(公告)号：US09093149B2
公开(公告)日：2015-07-28
申请号：US13602666
申请日：2012-09-04
申请人： Xia Li , Seung H. Kang
发明人： Xia Li , Seung H. Kang
IPC分类号： G11C7/00 , G11C17/02 , G11C17/00 , H01L27/22 , H01L23/525 , H01L43/08 , H01L43/12 , G11C11/56 , G11C17/14 , G11C17/16
CPC分类号： G11C17/02 , G11C11/005 , G11C11/5607 , G11C11/5692 , G11C17/00 , G11C17/14 , G11C17/16 , G11C17/165 , H01L23/5252 , H01L23/5256 , H01L27/22 , H01L27/224 , H01L43/08 , H01L43/12 , H01L2924/0002 , H01L2924/00
摘要： A one time programmable (OPT) and multiple time programmable (MTP) structure is constructed in a back end of line (BEOL) process using only one, two or three masks. The OTP/MTP structure can be programmed in one of three states, a pre-programmed high resistance state, and a programmable low resistance state and a programmable very high resistance state. In the programmable low resistance state, a barrier layer is broken down during an anti-fuse programming so that the OTP/MTP structure exhibits resistance in the hundred ohm order of magnitude. In the very high resistance state a conductive fuse is blown open during programming so that the OTP/MTP structure exhibits resistance in the mega-ohm order of magnitude. The OTP/MTP structure may include a magnetic tunnel junction (MTJ) structure or a metal-insulator-metal (MIM) capacitor structure.
摘要翻译：仅使用一个，两个或三个掩模，在后端（BEOL）过程中构造了一次性可编程（OPT）和多时间可编程（MTP）结构。 OTP / MTP结构可以编程为三种状态之一，预编程的高电阻状态，可编程低电阻状态和可编程非常高的电阻状态。在可编程低电阻状态下，在抗熔丝编程期间阻挡层被分解，使得OTP / MTP结构呈现出百欧姆量级的电阻。在非常高的电阻状态下，在编程期间导通熔丝被断开，使得OTP / MTP结构呈现以兆欧姆数量级的电阻。 OTP / MTP结构可以包括磁隧道结（MTJ）结构或金属 - 绝缘体 - 金属（MIM）电容器结构。

28. 发明授权

US08803282B2 Electronic device including a nonvolatile memory structure having an antifuse component 有权
标题翻译：电子设备包括具有反熔丝部件的非易失性存储器结构
公开(公告)号：US08803282B2
公开(公告)日：2014-08-12
申请号：US13953874
申请日：2013-07-30
申请人： Moshe Agam , Thierry Coffi Herve Yao
发明人： Moshe Agam , Thierry Coffi Herve Yao
IPC分类号： H01L23/525 , H01L29/78 , H01L29/788 , H01L27/088 , H01L27/112 , H01L21/76 , G11C17/14 , H01L27/02
CPC分类号： H01L23/5252 , G11C17/14 , G11C17/16 , G11C17/18 , H01L21/76 , H01L27/0207 , H01L27/088 , H01L27/11206 , H01L29/7831 , H01L29/788 , H01L2924/0002 , H01L2924/00
摘要： An electronic device can include a nonvolatile memory cell, wherein the nonvolatile memory cell can include an access transistor, a read transistor, and an antifuse component coupled to the access transistor and the read transistor. In an embodiment, the read transistor can include a gate electrode, and the antifuse component can include a first electrode and a second electrode overlying the first electrode. The gate electrode and the first electrode can be parts of the same gate member. In another embodiment, the access transistor can include a gate electrode, and the antifuse component can include a first electrode, an antifuse dielectric layer, and a second electrode. The electronic device can further include a conductive member overlying the antifuse dielectric layer and the gate electrode of the access transistor, wherein the conductive member is configured to electrically float. Processes for making the same are also disclosed.
摘要翻译：电子设备可以包括非易失性存储单元，其中非易失性存储单元可以包括存取晶体管，读晶体管和耦合到存取晶体管和读晶体管的反熔丝元件。在一个实施例中，读取晶体管可以包括栅电极，并且反熔丝部件可以包括覆盖第一电极的第一电极和第二电极。栅电极和第一电极可以是同一栅极部件的部件。在另一实施例中，存取晶体管可以包括栅电极，反熔丝元件可以包括第一电极，反熔丝电介质层和第二电极。电子器件还可以包括覆盖反熔介电介质层和存取晶体管的栅电极的导电部件，其中导电部件构造成电浮动。还公开了制备它们的方法。

29. 发明授权

US08750069B2 Semiconductor device and method for forming the same 有权
标题翻译：半导体装置及其形成方法
公开(公告)号：US08750069B2
公开(公告)日：2014-06-10
申请号：US14155289
申请日：2014-01-14
申请人： SK Hynix Inc.
发明人： Jung Sam Kim
IPC分类号： G11C17/18 , G11C17/14 , G11C17/16 , H01L21/768 , H01L27/06
CPC分类号： G11C17/14 , G11C17/12 , G11C17/16 , G11C29/789 , H01L21/768 , H01L21/76897 , H01L23/5252 , H01L27/0688 , H01L27/1052 , H01L27/10876 , H01L27/10885 , H01L27/11206 , H01L2224/321
摘要： A method for forming a semiconductor device is disclosed. An anti-fuse is formed at a buried bit line such that the area occupied by the anti-fuse is smaller than that of a conventional planar-gate-type anti-fuse, and a breakdown efficiency of an insulation film is increased. This results in an increase in reliability and stability of the semiconductor device. A semiconductor device includes a line pattern formed over a semiconductor substrate, a device isolation film formed at a center part of the line pattern, a contact part formed at both sides of the line pattern, configured to include an oxide film formed over the line pattern, and a bit line formed at a bottom part between the line patterns, and connected to the contact part.
摘要翻译：公开了一种用于形成半导体器件的方法。在掩埋位线处形成反熔丝，使得由反熔丝占据的面积小于常规平面栅型反熔丝的面积，并且提高绝缘膜的击穿效率。这导致半导体器件的可靠性和稳定性的增加。半导体器件包括形成在半导体衬底上的线图案，形成在线图案的中心部分处的器件隔离膜，形成在线图案的两侧的接触部分，被配置为包括形成在线图案上的氧化膜以及形成在线图案之间的底部处并且连接到接触部分的位线。

30. 发明申请

US20120262223A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120262223A1
公开(公告)日：2012-10-18
申请号：US13529421
申请日：2012-06-21
申请人： Hiroaki OHKUBO , Yasutaka NAKASHIBA
发明人： Hiroaki OHKUBO , Yasutaka NAKASHIBA
IPC分类号： G11C17/14
CPC分类号： H01L23/5252 , G11C17/143 , G11C17/16 , G11C29/027 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a signal output unit, and a decision unit. The signal output unit includes m (≧2) pieces of fuses, a NAND gate, resistance elements, and an output terminal. The decision unit decides whether n or more pieces (m≧n≧2) of fuses are disconnected out of the m pieces of fuses included in the signal output unit, and outputs the result of a decision. When m=n=2, the decision unit is constituted of a NOR gate having two input terminals connected to a respective end of the fuses. Thus, a H-level potential signal is output at an output terminal of the NOR gate when the decision result is affirmative. On the other hand, when the decision result is negative, a L-level potential signal is output at the output terminal.
摘要翻译：半导体器件包括信号输出单元和判定单元。信号输出单元包括m（≥2）个保险丝，NAND门，电阻元件和输出端。决定单元判定在信号输出单元中包括的m个熔丝中是否断开n个以上的熔丝（m≥n≥2），并输出判定结果。当m = n = 2时，判定单元由具有连接到保险丝的相应端的两个输入端的NOR门构成。因此，当判定结果为肯定时，在或非门的输出端输出H电平电位信号。另一方面，当判定结果为负时，在输出端输出L电平电位信号。

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