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21. 发明授权

US07876128B1 Voltage sequence output circuit 失效
标题翻译：电压序列输出电路
公开(公告)号：US07876128B1
公开(公告)日：2011-01-25
申请号：US12813475
申请日：2010-06-10
申请人： Chuan-Tsai Hou
发明人： Chuan-Tsai Hou
IPC分类号： H03K19/02 , H02J1/00 , H02J3/14
CPC分类号： H02J1/14 , Y10T307/484
摘要： A voltage sequence output circuit includes a sequence control circuit and a number of voltage output circuits. The sequence control circuit includes a first NOR gate, and the first NOR gate includes a number of the input terminals. The voltage output circuits each includes an input terminal, an output terminal, and a positively enabled tristate buffer connected between the input terminal and the output terminal thereof. The input terminals of the voltage output circuits is connected to the input terminals of the first NOR gate. If all of input terminals of the voltage output circuits are connected with electronic devices, the positively enabled tristate buffer of the voltage output circuits are enabled. The output terminals of the voltage output circuits sequentially output a voltage.
摘要翻译：电压序列输出电路包括序列控制电路和多个电压输出电路。序列控制电路包括第一或非门，第一或非门包括多个输入端。电压输出电路各自包括输入端子，输出端子和连接在输入端子和其输出端子之间的正向三通缓冲器。电压输出电路的输入端连接到第一或非门的输入端。如果电压输出电路的所有输入端子均与电子设备相连，电压输出电路的正向三态缓冲器被使能。电压输出电路的输出端依次输出电压。

22. 发明申请

US20100072957A1 Nanotube-based logic driver circuits 失效
标题翻译：基于纳米管的逻辑驱动电路
公开(公告)号：US20100072957A1
公开(公告)日：2010-03-25
申请号：US11897812
申请日：2007-08-31
申请人： Claude L. Bertin
发明人： Claude L. Bertin
IPC分类号： H03K19/02 , H02J7/00 , H03K19/20
CPC分类号： G11C13/025 , B82Y10/00 , G11C23/00 , G11C2213/16 , H03K19/02
摘要： Nanotube based logic driver circuits. These include pull-up driver circuits, push-pull driver circuits, tristate driver circuits, among others. Under one embodiment, an off-chip driver circuit includes a differential input having first and second signal links, each coupled to a respective one of two differential, on-chip signals. At least one output link is connectable to an off-chip impedance load, and at least one switching element has an input node, an output node, a nanotube channel element, and a control structure disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said input node and said output node. The input node is coupled to a reference signal and the control structure is coupled to the first and second signal links. The output node is coupled to the output link, and the channel element is sized to carry sufficient current to drive said off-chip impedance load.
摘要翻译：基于纳米管的逻辑驱动电路。这些包括上拉驱动电路，推挽驱动电路，三态驱动电路等。在一个实施例中，片外驱动器电路包括具有第一和第二信号链路的差分输入，每个信号链路耦合到两个差分片上信号中的相应一个。至少一个输出链路可连接到片外阻抗负载，并且至少一个开关元件具有输入节点，输出节点，纳米管通道元件和相对于纳米管通道元件设置的可控制地形成的控制结构并且在所述输入节点和所述输出节点之间取消导电通道。输入节点耦合到参考信号，并且控制结构耦合到第一和第二信号链路。输出节点耦合到输出链路，并且信道单元的大小适于承载足够的电流以驱动所述片外阻抗负载。

23. 发明授权

US07667489B1 Power-on reset circuit for a voltage regulator having multiple power supply voltages 有权
标题翻译：具有多个电源电压的稳压器的上电复位电路
公开(公告)号：US07667489B1
公开(公告)日：2010-02-23
申请号：US11977831
申请日：2007-10-26
申请人： Narasimhan Vasudevan
发明人： Narasimhan Vasudevan
IPC分类号： H03K19/00 , H03K19/02 , H03K19/096
CPC分类号： H03K19/17772 , H03K19/17784
摘要： A voltage regulator and method of voltage regulation for a power-on reset condition are described. Voltage regulation control signals responsive to the power-on reset condition are obtained. The control signals are generated with a first voltage to be associated with a second voltage to provide a first power-on-reset signal and a second power-on-reset signal which are opposite in state to one another. A portion of driver logic is tri-stated responsive to the control signals, and the second power-on-reset signal to at least impede supply to supply current leakage. Voltage is pulled up on a first output port and a second output port of the driver logic responsive to the first power-on-reset signal. A portion of a semiconductor substrate is electrically coupled to a higher one of a first voltage and a second voltage responsive to the pulling up to at least further impede the supply to supply current leakage.
摘要翻译：描述了上电复位条件下的电压调节器和电压调节方法。获得响应于上电复位条件的电压调节控制信号。控制信号以与第二电压相关联的第一电压产生，以提供彼此处于相反状态的第一上电复位信号和第二上电复位信号。驱动器逻辑的一部分响应于控制信号而被三态化，并且第二上电复位信号至少阻碍电源以提供电流泄漏。响应于第一上电复位信号，驱动器逻辑的第一输出端口和第二输出端口上拉电压。半导体衬底的一部分电耦合到第一电压和第二电压中较高的一个，以响应于上拉至少进一步阻碍电源以供应电流泄漏。

24. 发明授权

US07652505B2 Level conversion circuit for converting voltage amplitude of signal 有权
标题翻译：用于转换信号电压幅度的电平转换电路
公开(公告)号：US07652505B2
公开(公告)日：2010-01-26
申请号：US12230007
申请日：2008-08-21
申请人： Teruaki Kanzaki
发明人： Teruaki Kanzaki
IPC分类号： H03K19/0175 , H03K19/094 , H03K19/00 , H03K19/02 , H03K19/20 , H03K3/01 , G01R19/00 , G11C7/00 , H03F3/45 , H03L5/00 , G05F1/10 , G05F3/02
CPC分类号： H03K19/018521
摘要： In a level conversion circuit, two P channel MOS transistors form a current mirror circuit. When an input signal rises from the “L” level to the “H” level, an N channel MOS transistor connected to a drain of one P channel MOS transistor is brought out of conduction to prevent a leak current from flowing through two P channel MOS transistors, which decreases a power consumption. In addition, when the input signal rises from the “L” level to the “H” level, a P channel MOS transistor connected to a drain of the other P channel MOS transistor is brought into conduction to fix a potential of a node of the drain of the other P channel MOS transistor to the “H” level, which prevents the potential of the node from becoming unstable.
摘要翻译：在电平转换电路中，两个P沟道MOS晶体管形成电流镜电路。当输入信号从“L”电平上升到“H”电平时，连接到一个P沟道MOS晶体管的漏极的N沟道MOS晶体管导通，以防止漏电流流过两个P沟道MOS 晶体管，这降低了功耗。此外，当输入信号从“L”电平上升到“H”电平时，连接到另一个P沟道MOS晶体管的漏极的P沟道MOS晶体管导通，以固定其中的一个节点的电位另一个P沟道MOS晶体管的漏极为“H”电平，从而防止节点的电位变得不稳定。

25. 发明申请

US20090206877A1 QUAD STATE LOGIC DESIGN METHODS, CIRCUITS AND SYSTEMS 有权
标题翻译：四态逻辑设计方法，电路和系统
公开(公告)号：US20090206877A1
公开(公告)日：2009-08-20
申请号：US12431330
申请日：2009-04-28
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： H03K19/02 , H03K19/00
CPC分类号： G11C5/063 , G11C11/56 , H03K19/0002 , H03K19/1732
摘要： Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs.
摘要翻译：四态逻辑元件和四态存储器元件用于降低集成电路的布线密度。存储器和逻辑元件之间的布线互连的减少导致更高的速度，更高的密度和更低功率的集成电路设计。

26. 发明授权

US07567094B2 Tri-stated driver for bandwidth-limited load 有权
标题翻译：三态驱动器，用于带宽限制负载
公开(公告)号：US07567094B2
公开(公告)日：2009-07-28
申请号：US11807150
申请日：2007-05-25
申请人： Kalpendu Shastri
发明人： Kalpendu Shastri
IPC分类号： H03K19/00 , H03K19/02
CPC分类号： H03K19/09429
摘要： A CMOS driver circuit is configured to provide a tri-state condition after a predetermined number of like-valued data bits have been transmitted, reducing the presence of intersymbol interference (ISI) along a transmission channel. In situations where the transmission channel is bandwidth-limited, the use of the tri-stating technique allows for the complete transition to the supply rails during the given bit period.
摘要翻译： CMOS驱动器电路被配置为在已经发送了预定数量的类似值的数据位之后提供三态条件，从而减少了沿着传输信道的符号间干扰（ISI）的存在。在传输信道受带宽限制的情况下，三态技术的使用允许在给定位周期期间完全转换到电源轨。

27. 发明授权

US07548094B2 Systems and methods for on-chip signaling 有权
标题翻译：片上信令的系统和方法
公开(公告)号：US07548094B2
公开(公告)日：2009-06-16
申请号：US11654286
申请日：2007-01-17
申请人： Kenneth L. Shepard , Anup P. Jose
发明人： Kenneth L. Shepard , Anup P. Jose
IPC分类号： H03K19/0175 , H03K19/02
CPC分类号： G06F13/4072 , Y02D10/14 , Y02D10/151
摘要： Systems and methods for on-chip signaling are disclosed. In some embodiments, an integrated circuit having on-chip signaling between a first component and a second component includes, a differential interconnect capable of coupling the first component to the second component, a driver capable of being coupled to the first component that sends data on the differential interconnect, a receiver capable of being coupled to the second component that receives the data, and a plurality of negative impedance converters capable of being coupled to the differential interconnect that provide loss compensation.
摘要翻译：公开了用于片上信令的系统和方法。在一些实施例中，在第一组件和第二组件之间具有片上信令的集成电路包括能够将第一组件耦合到第二组件的差分互连，能够耦合到第一组件的驱动器，该第一组件向差分互连，能够耦合到接收数据的第二组件的接收器以及能够耦合到提供损耗补偿的差分互连的多个负阻抗转换器。

28. 发明申请

US20090002017A1 Multiple-Mode Compensated Buffer Circuit 有权
标题翻译：多模式补偿缓冲电路
公开(公告)号：US20090002017A1
公开(公告)日：2009-01-01
申请号：US11768496
申请日：2007-06-26
申请人： Dipankar Bhattacharya , Gregg R. Harleman , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
发明人： Dipankar Bhattacharya , Gregg R. Harleman , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
IPC分类号： H03K19/0175 , H03K19/02
CPC分类号： H03K19/00376
摘要： A compensated buffer circuit operative in one of at least a first mode and a second mode includes a plurality of output blocks and a plurality of predrivers, each of the predrivers having an output connected to an input of a corresponding one of the output blocks. Respective outputs of the output blocks are connected together and form an output of the buffer circuit. The output blocks are arranged in a sequence and are binary weighted such that a drive strength of a given one of the output blocks is about twice as large as a drive strength of an output block immediately preceding the given output block. Each of the predrivers selectively enables the corresponding output block connected thereto as a function of a control signal supplied to the predriver for compensating the buffer circuit for PVT variations to which the buffer circuit may be subjected. The respective control signals supplied to the predrivers collectively represent a binary code word, the binary code word in the second mode being equivalent to an arithmetic shift of the binary code word in the first mode.
摘要翻译：以至少第一模式和第二模式之一工作的补偿缓冲器电路包括多个输出块和多个预驱动器，每个预驱动器具有连接到相应一个输出块的输入的输出。输出块的各输出端连接在一起形成缓冲电路的输出。输出块按顺序排列并且被二进制加权，使得给定的一个输出块的驱动强度大约是在给定输出块之前的输出块的驱动强度的两倍。每个预驱动器根据提供给预驱动器的控制信号选择性地使连接到其上的相应输出块能够补偿用于缓冲电路可能经受的PVT变化的缓冲电路。提供给预驱动器的各个控制信号共同表示二进制码字，第二模式中的二进制码字等价于第一模式中的二进制码字的算术移位。

29. 发明授权

US07463063B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07463063B2
公开(公告)日：2008-12-09
申请号：US11802368
申请日：2007-05-22
申请人： Yoshinori Hashimoto
发明人： Yoshinori Hashimoto
IPC分类号： H03K19/00 , H03K19/02 , H03K19/0175
CPC分类号： G01R31/31715
摘要： In normal operation, an internal circuit operates in synchronism with a clock CK, so that switching operation of the output circuit is performed based on inputted data and an output enable signal. At this point, an output from the internal circuit to a three-state control circuit is forcedly set by state control circuits, whereby different test operations are performed on the output circuit.
摘要翻译：在正常操作中，内部电路与时钟CK同步工作，从而基于输入的数据和输出使能信号来执行输出电路的切换操作。此时，由状态控制电路强制设定从内部电路向三态控制电路的输出，由此对输出电路进行不同的测试动作。

30. 发明授权

US07403036B2 Interface circuit 失效
标题翻译：接口电路
公开(公告)号：US07403036B2
公开(公告)日：2008-07-22
申请号：US11342881
申请日：2006-01-31
申请人： Kazuhiko Bando , Masanori Inazumi
发明人： Kazuhiko Bando , Masanori Inazumi
IPC分类号： H03K19/00 , H03K19/02
CPC分类号： H03K19/0016
摘要： As a data bus control enable signal is set to “H,” a PMOS turns on when a bi-directional bus is not in use (i.e., when a data bus active signal is “L”), so that the bi-directional bus is pulled down through a pull-down resistor. When the data bus control enable signal is set to “L,” the PMOS turns off, thus holding the bi-directional bus in a high-impedance state. By setting the data bus control enable signal in accordance with the specifications of a peripheral device connected thereto, the state of the bi-directional bus can be arbitrarily set when it is inactive.
摘要翻译：当数据总线控制使能信号被设置为“H”时，当不使用双向总线时（即，当数据总线有效信号为“L”）时，PMOS导通，使得双向总线通过下拉电阻下拉。当数据总线控制使能信号设置为“L”时，PMOS关断，因此将双向总线保持在高阻态。通过根据与其连接的外围设备的规格设置数据总线控制使能信号，双向总线的状态可以在不活动时任意设置。

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