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31. 发明授权

US07648909B2 Method for fabricating semiconductor device with metal line 失效
标题翻译：用金属线制造半导体器件的方法
公开(公告)号：US07648909B2
公开(公告)日：2010-01-19
申请号：US11321533
申请日：2005-12-30
申请人： Hae-Jung Lee , Sang-Hoon Cho , Suk-Ki Kim
发明人： Hae-Jung Lee , Sang-Hoon Cho , Suk-Ki Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76877 , H01L21/32115 , H01L21/32136 , H01L21/76843 , H01L21/76849
摘要： A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and filled in the openings; etching the first conductive layer to form interconnection layers in the openings and to expose portions of the metal barrier layer, the interconnection layers being inside the openings and at a depth from a top of the openings; etching the exposed portions of the metal barrier layer to obtain a sloped profile of the metal barrier layer at top lateral portions of the openings; forming a second conductive layer over the inter-layer insulation layer, the interconnection layers and the metal barrier layer with the sloped profile; and patterning the second conductive layer to form metal lines.
摘要翻译：一种制造半导体器件的方法包括在衬底上形成层间绝缘层; 在层间绝缘层中形成开口; 在开口和层间绝缘层上形成金属阻挡层; 在所述金属阻挡层上形成第一导电层并填充在所述开口中; 蚀刻所述第一导电层以在所述开口中形成互连层并且暴露所述金属阻挡层的部分，所述互连层位于所述开口内部以及在距所述开口顶部的深度处; 蚀刻金属阻挡层的暴露部分以在开口的顶侧部分处获得金属阻挡层的倾斜轮廓; 在所述层间绝缘层上形成第二导电层，所述互连层和所述金属阻挡层具有所述倾斜轮廓; 并且图案化第二导电层以形成金属线。

32. 发明授权

US07626448B2 Internal voltage generator 有权
标题翻译：内部电压发生器
公开(公告)号：US07626448B2
公开(公告)日：2009-12-01
申请号：US11528650
申请日：2006-09-28
申请人： Sang-Jin Byeon , Jae-Hyuk Im
发明人： Sang-Jin Byeon , Jae-Hyuk Im
IPC分类号： G05F1/10
CPC分类号： G11C5/14
摘要： An internal voltage generator includes: an internal voltage driving unit for supplying an internal voltage corresponding to a reference voltage maintaining a predetermined voltage level regardless of a temperature variation; and a temperature compensation current sinking unit for sinking a current generated by an internal voltage in response to a voltage level inversely proportional to a temperature.
摘要翻译：内部电压发生器包括：内部电压驱动单元，用于提供与保持预定电压电平的参考电压相对应的内部电压，而不管温度变化如何; 以及温度补偿电流吸收单元，用于响应于与温度成反比的电压电平来吸收由内部电压产生的电流。

33. 发明授权

US07609195B2 On die thermal sensor and method for generating thermal code of ODTS 有权
标题翻译：用于生成热传感器和ODTS热代码的方法
公开(公告)号：US07609195B2
公开(公告)日：2009-10-27
申请号：US12003678
申请日：2007-12-31
申请人： Chun-Seok Jeong
发明人： Chun-Seok Jeong
IPC分类号： H03M1/10
CPC分类号： G01K7/015 , G01K7/425 , H01L23/34 , H01L2924/0002 , H03M1/186 , H03M1/48 , H01L2924/00
摘要： An on die thermal sensor (ODTS) in a memory device includes: a band gap unit for detecting a temperature of the memory device to output a first voltage corresponding to the temperature; and an analog-to-digital converting unit for outputting a digital code having temperature information based on the first voltage, the digital code having varied resolution according to temperature ranges.
摘要翻译：存储器件中的裸片热传感器（ODTS）包括：带隙单元，用于检测存储器件的温度以输出对应于该温度的第一电压; 以及模数转换单元，用于根据温度范围输出具有基于第一电压的温度信息的数字代码，数字代码具有不同的分辨率。

34. 发明授权

US07821847B2 Circuit and method for controlling slew rate of data output circuit in semiconductor memory device 失效
标题翻译：用于控制半导体存储器件中的数据输出电路的转换速度的电路和方法
公开(公告)号：US07821847B2
公开(公告)日：2010-10-26
申请号：US12345248
申请日：2008-12-29
申请人： Mi-Hye Kim
发明人： Mi-Hye Kim
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/1057
摘要： A data output circuit of a semiconductor memory device includes at least two data output pads disposed adjacent to each other, a driver unit configured to output a first data by driving a first pad among the data output pads, and a control unit configured to determine whether a phase of the first data is equal to a phase of adjacent data outputted through second pad adjacent to the first pad, and control a slew rate of the driver unit according to the determination result.
摘要翻译：半导体存储器件的数据输出电路包括彼此相邻布置的至少两个数据输出焊盘，驱动器单元，被配置为通过驱动数据输出焊盘之间的第一焊盘来输出第一数据;以及控制单元，被配置为确定是否第一数据的相位等于通过与第一焊盘相邻的第二焊盘输出的相邻数据的相位，并且根据确定结果来控制驱动器单元的转换速率。

35. 发明授权

US07821846B2 Semiconductor memory device and its driving method 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US07821846B2
公开(公告)日：2010-10-26
申请号：US12240459
申请日：2008-09-29
申请人： Seok-Cheol Yoon
发明人： Seok-Cheol Yoon
IPC分类号： G11C7/10
CPC分类号： G11C7/1045
摘要： A semiconductor memory device including a first latch that latches a Mode Register Set (MRS) code consisting of multiple bits in response to an MRS command pulse, a code controller that generates a control signal in response to a code value of preset bits out of an output signal from the first latch, a second latch that selectively latches the output signal from the first latch in response to the control signal and a mode decoder that decodes an output signal from the second latch to output an operation mode.
摘要翻译：一种半导体存储器件，包括：第一锁存器，其响应于MRS指令脉冲锁存由多个位组成的模式寄存器组（MRS）代码;代码控制器，其响应于预定位的代码值而生成控制信号来自第一锁存器的输出信号;响应于控制信号选择性地锁存来自第一锁存器的输出信号的第二锁存器;以及解码来自第二锁存器的输出信号以输出操作模式的模式解码器。

36. 发明授权

US07818526B2 Semiconductor memory device having test mode for data access time 有权
标题翻译：半导体存储器件具有用于数据存取时间的测试模式
公开(公告)号：US07818526B2
公开(公告)日：2010-10-19
申请号：US11022828
申请日：2004-12-28
申请人： Ji-Eun Jang , Kee-Teok Park
发明人： Ji-Eun Jang , Kee-Teok Park
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G11C29/00 , G11C7/00
CPC分类号： G11C29/02 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C29/022 , G11C29/028 , G11C29/50012
摘要： A semiconductor memory device for measuring a data access time by controlling data output operation, including: a pipe latch control unit for generating an input control signal based on a test mode signal; a pipe latch unit for receiving data and controlling the data according to a CAS latency in synchronization with a clock signal at a normal mode or passing the data without synchronization with the clock signal at a test mode based on the input control signal; an output control unit for generating an output node control signal based on the test mode signal; and an output unit for controlling an output data outputted from the pipe latch means according to the CAS latency in synchronization with the clock signal at the normal mode or passing the output data without synchronization with the clock signal at the test mode based on the output node control signal.
摘要翻译：一种用于通过控制数据输出操作来测量数据访问时间的半导体存储器件，包括：管锁存器控制单元，用于基于测试模式信号产生输入控制信号; 管道锁存单元，用于基于所述输入控制信号，在测试模式下，与正常模式下的时钟信号同步地接收数据并根据CAS延迟来控制所述数据，或者与所述时钟信号同步地传送所述数据; 输出控制单元，用于基于测试模式信号产生输出节点控制信号; 以及输出单元，用于基于所述输出节点，在与所述正常模式下的所述时钟信号同步地控制从所述管锁存装置输出的输出数据，或者使所述输出数据与所述测试模式下的所述时钟信号同步，控制信号。

37. 发明授权

US07817491B2 Bank control device and semiconductor device including the same 有权
标题翻译：银行控制装置和包括其的半导体装置
公开(公告)号：US07817491B2
公开(公告)日：2010-10-19
申请号：US12165127
申请日：2008-06-30
申请人： Seung-Wook Kwak
发明人： Seung-Wook Kwak
IPC分类号： G11C8/00
CPC分类号： G11C7/1048 , G11C7/1012 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C8/12 , G11C11/4093
摘要： A semiconductor memory device includes a plurality of banks a plurality of banks stacked in a column direction, a global data line corresponding to the plurality of banks and a common global data line driving unit for multiplexing data on a plurality of local data lines corresponding to each of the banks to transmit the multiplexed result to the global data line.
摘要翻译：一种半导体存储器件，包括沿着列方向堆叠的多个存储体的多个存储体，与该多个存储体对应的全局数据线，以及公共全局数据线驱动单元，用于对与每个存储器对应的多条本地数据线复用数据以将多路复用结果发送到全局数据线。

38. 发明授权

US07813197B2 Write circuit of memory device 有权
标题翻译：存储器件的写电路
公开(公告)号：US07813197B2
公开(公告)日：2010-10-12
申请号：US12027068
申请日：2008-02-06
申请人： Beom-Ju Shin
发明人： Beom-Ju Shin
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/1006 , G11C7/1027 , G11C7/1039 , G11C7/1045 , G11C7/1066 , G11C7/1072 , G11C7/1087 , G11C7/1096 , G11C11/4093 , G11C11/4096 , G11C2207/107
摘要： A write circuit of a semiconductor memory device includes a global data input/output (I/O) line; an amplifying block for receiving and amplifying write data and transmitting the amplified write data as global data onto the global data I/O line; and a control block for comparing the write data with the global data to thereby disable the amplifying block when the write data and the global data have substantially the same data value.
摘要翻译：半导体存储器件的写入电路包括全局数据输入/输出（I / O）线; 放大块，用于接收和放大写入数据，并将放大的写入数据作为全局数据发送到全局数据I / O线上; 以及控制块，用于将写入数据与全局数据进行比较，从而当写入数据和全局数据具有基本相同的数据值时禁止放大块。

39. 发明授权

US07804727B2 Semiconductor device having multiple I/O modes 有权
标题翻译：具有多个I / O模式的半导体器件
公开(公告)号：US07804727B2
公开(公告)日：2010-09-28
申请号：US12164155
申请日：2008-06-30
申请人： Kwan-Dong Kim
发明人： Kwan-Dong Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/1087 , G11C7/1093
摘要： Semiconductor device having multiple I/O modes. The device includes a data buffer configured to receive data; a strobe input buffer configured to receive a data strobe signal, a phase controller configured to shift a phase of the data strobe signal by different numbers of degrees, including 0 degrees, according to input modes and a data detector configured to detect the data in response to the data strobe signal output from the phase controller.
摘要翻译：具有多个I / O模式的半导体器件。该设备包括被配置为接收数据的数据缓冲器; 配置为接收数据选通信号的选通输入缓冲器;相位控制器，被配置为根据输入模式将数据选通信号的相位移位不同的度数，包括0度;以及数据检测器，被配置为检测响应中的数据到从相位控制器输出的数据选通信号。

40. 发明授权

US07804723B2 Semiconductor memory device with signal aligning circuit 有权
标题翻译：具有信号对准电路的半导体存储器件
公开(公告)号：US07804723B2
公开(公告)日：2010-09-28
申请号：US11478092
申请日：2006-06-30
申请人： Hwang Hur , Chang-Ho Do
发明人： Hwang Hur , Chang-Ho Do
IPC分类号： G11C7/00
CPC分类号： G11C29/34 , G11C7/1006 , G11C7/22 , G11C8/16 , G11C29/02 , G11C29/022 , G11C29/1201 , G11C2207/108
摘要： A signal aligning circuit includes a plurality of pads receiving input signals in parallel 1 bit by 1 bit; a first transferring unit for transferring the input signals as first signals in synchronization with a first clock signal of an internal clock, and transferring the input signals as second signals in synchronization with a second clock signal of the internal clock; a second transferring unit for transferring the first signals in synchronization with the second clock signal of the internal clock; and an aligning unit for aligning the first and second signals transferred from the first and second transferring units and outputting the aligned signal as output signals.
摘要翻译：信号对准电路包括多个焊盘，1比特1比特并行地接收输入信号; 第一传送单元，用于将输入信号作为与内部时钟的第一时钟信号同步的第一信号传送，并且将输入信号作为与内部时钟的第二时钟信号同步的第二信号传送; 第二传送单元，用于与所述内部时钟的第二时钟信号同步地传送所述第一信号; 以及对准单元，用于对准从第一和第二传送单元传送的第一和第二信号，并输出对准的信号作为输出信号。

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