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31. 发明授权

US06560163B2 Semiconductor device including a repetitive pattern 失效
公开(公告)号：US06560163B2
公开(公告)日：2003-05-06
申请号：US10040479
申请日：2002-01-09
申请人： Hironobu Akita , Shinichiro Shiratake , Fumihiro Kohno
发明人： Hironobu Akita , Shinichiro Shiratake , Fumihiro Kohno
IPC分类号： G11C800
CPC分类号： G11C8/10 , G11C8/14 , G11C11/4087 , H01L27/10897
摘要： The present invention provides a DRAM in which a first repetitive unit including a plurality of decoders for selecting a plurality of word lines and a second repetitive unit having the same arrangement as that of the first repetitive unit are arranged symmetrically with respect a boundary region therebetween. The first and second repetitive units have a wire and a contact located on a boundary portion therebetween in common.

32. 发明授权

US06452833B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06452833B2
公开(公告)日：2002-09-17
申请号：US09773606
申请日：2001-02-02
申请人： Hironobu Akita , Kenji Tsuchida , Fumihiro Kohno
发明人： Hironobu Akita , Kenji Tsuchida , Fumihiro Kohno
IPC分类号： G11C1124
CPC分类号： G11C7/12 , G11C11/4094
摘要： A BL kicker circuit includes first capacitors each of which is connected at one end to a first bit line which is one of bit lines of a corresponding pair and commonly connected at the other end, second capacitors each of which is connected at one end to a second bit line which is the other one of the bit lines of a corresponding pair and commonly connected at the other end, a first driver circuit having an output node for a first signal connected to the common connection node of the other ends of the first capacitors, a second drive circuit having an output node for a second signal connected to the common connection node of the other ends of the second capacitors, and a switch circuit used as an equalizing circuit connected between the output node for the first signal and the output node for the second signal.
摘要翻译： BL激光电路包括第一电容器，每个电容器的一端连接到第一位线，第一位线是相应对的位线之一，并且在另一端共同连接，第二电容器的一端连接到一端第二位线，其是相应对中的另一个位线并且在另一端共同连接，第一驱动器电路具有用于连接到第一电容器的另一端的公共连接节点的第一信号的输出节点具有连接到第二电容器的另一端的公共连接节点的第二信号的输出节点的第二驱动电路和用作连接在第一信号的输出节点和输出节点之间的均衡电路的开关电路对于第二个信号。

33. 发明授权

US06373303B1 Sync signal generating circuit provided in semiconductor integrated circuit 有权
公开(公告)号：US06373303B1
公开(公告)日：2002-04-16
申请号：US09846286
申请日：2001-05-02
申请人： Hironobu Akita
发明人： Hironobu Akita
IPC分类号： H03L706
摘要： A sync signal generating circuit has a first I/O replica for delaying an external clock signal, a comparator replica with a variable delay time for delaying an output of the first I/O replica, a first ramp-voltage generating circuit for outputting a first voltage whose potential level begins to rise at a time of transition of a level of the output of the comparator replica and stops rising at a predetermined timing, a second ramp-voltage generating circuit for outputting a second voltage whose potential level begins to rise after the rising of the potential level of the first voltage stops, a voltage comparator for comparing the first and second voltages and outputting an internal clock signal, a second I/O replica for delaying the internal clock signal with a delay time substantially equal to the delay time of the first I/O replica, and a phase comparator for comparing a phase of an output of the second I/O replica and a phase of an input to the first I/O replica. A delay time in the comparator replica is adjusted on the basis of an output from the phase comparator.

34. 发明授权

US06370057B1 Semiconductor memory device having plate lines and precharge circuits 失效
标题翻译：具有板线和预充电电路的半导体存储器件
公开(公告)号：US06370057B1
公开(公告)日：2002-04-09
申请号：US09609774
申请日：2000-07-03
申请人： Hironobu Akita
发明人： Hironobu Akita
IPC分类号： G11C1124
CPC分类号： H01L27/10897 , G11C7/12 , G11C11/4074 , G11C11/4094
摘要： A dynamic semiconductor memory device includes memory cells each having a one-transistor/one-capacitor. The memory cells are arranged at their respective intersections of bit lines and word lines. Bit-line precharge circuits are provided at bit line pairs, respectively, to precharge and equalize the bit line pairs. An output potential of a plate potential generator is applied to the power supply terminals of the bit-line precharge circuits. The memory cells have a plurality of capacitors. A plate electrode of the capacitors are connected in common. An insulation film is formed on the plate electrode and a wiring layer is formed on the insulation film. The wiring layer is electrically connected to the plate electrode through a via hole formed in the insulation film and connected in common to the power supply terminals of the bit-line precharge circuits through a contact hole formed in the insulation film, thereby transmitting a potential in proportion to variations in plate potential.
摘要翻译：动态半导体存储器件包括各自具有单晶体管/单电容器的存储单元。存储单元被布置在位线和字线的各自交叉点处。分别在位线对上提供位线预充电电路，以对位线对进行预充电和均衡。板电位发生器的输出电位施加到位线预充电电路的电源端子。存储单元具有多个电容器。电容器的平板电极共同连接。在平板电极上形成绝缘膜，在绝缘膜上形成布线层。布线层通过形成在绝缘膜上的通孔与板电极电连接，并通过形成在绝缘膜上的接触孔共同连接到位线预充电电路的电源端，从而将电位传输到与板电位变化的比例。

35. 发明授权

US06339345B1 Semiconductor device equipped with output circuit adjusting duration of high and low levels 有权
标题翻译：半导体器件配备有输出电路调节持续时间的高低电平
公开(公告)号：US06339345B1
公开(公告)日：2002-01-15
申请号：US09696048
申请日：2000-10-26
申请人： Satoshi Eto , Hironobu Akita , Katsuaki Isobe
发明人： Satoshi Eto , Hironobu Akita , Katsuaki Isobe
IPC分类号： H03L700
CPC分类号： G11C7/1066 , G11C7/1072 , G11C7/222 , G11C2207/2254 , H03K5/135 , H03K19/00384 , H03L7/00
摘要： In an output circuit 10, a latch circuit 11, a phase difference controlled circuit 12 and an output buffer circuit 13 are cascaded and a DATA is clocked into the latch circuit 11. A replica circuit 20 is a down-scaled version of a layout pattern of the output circuit 10, comprises circuits 21 to 23 corresponding to the circuits 11, 12 and 13, and a CLK is provided through a delay circuit 5 and a divide-by-2 frequency divider 16 to the data input of the latch circuit 21 as a data. The output of the replica circuit 20 is provided through a dummy load circuit 24 and a low pass filter 25 to a comparator 26, the output thereof is compared with a reference voltage Vref to generate count-up or count-down pulses. The pulses are counted by an up-down counter 27 whose count is provided to the phase difference controlled circuit 12 and its replica 22 to reduce the phase difference between rising and falling edges of the output signal of the output buffer circuit 23.
摘要翻译：在输出电路10中，锁存电路11，相位差控制电路12和输出缓冲器电路13级联，并且DATA被锁定到锁存电路11中。复制电路20是布局模式的缩小版本输出电路10包括对应于电路11,12和13的电路21至23，并且通过延迟电路5和分频2分频器16将CLK提供给锁存电路21的数据输入作为数据。复制电路20的输出通过虚拟负载电路24和低通滤波器25提供给比较器26，其输出与参考电压Vref进行比较，以产生递增计数或递减计数脉冲。脉冲由计数器27计数，该计数器的计数被提供给相位差控制电路12及其副本22，以减小输出缓冲电路23的输出信号的上升沿和下降沿之间的相位差。

36. 发明授权

US06333658B1 Analog synchronization circuit 有权
标题翻译：模拟同步电路
公开(公告)号：US06333658B1
公开(公告)日：2001-12-25
申请号：US09707791
申请日：2000-11-08
申请人： Hironobu Akita , Satoshi Eto , Katsuaki Isobe , Masaharu Wada , Haruki Toda
发明人： Hironobu Akita , Satoshi Eto , Katsuaki Isobe , Masaharu Wada , Haruki Toda
IPC分类号： H03H1126
CPC分类号： H03K5/135
摘要： An analog synchronization circuit includes an input buffer which is supplied with an external clock signal, a delay monitor which is supplied with a clock signal output from the input buffer, an output buffer for outputting a clock signal synchronous with the external clock signal and two charge balance delay circuits. The two charge balance delay circuits are equivalent to delay lines in a mirror type delay locked loop. Each charge balance delay circuits operates once in two consecutive cycles of the external clock signal. The two charge balance delay circuits alternately operate and output signals of the charge balance delay circuits are supplied to the output buffer via an OR gate. First and second capacitors are provided in each charge balance delay circuits. A first current source circuit charges the first capacitor for a time equivalent to a delay time of a forward pulse. The second capacitor is charged by a second current source circuit. A comparator compares charge voltages of the first and second capacitors with each other and generates a timing signal when both charge voltages coincide with each other.
摘要翻译：模拟同步电路包括被提供有外部时钟信号的输入缓冲器，被提供有从输入缓冲器输出的时钟信号的延迟监视器，用于输出与外部时钟信号同步的时钟信号的输出缓冲器和两个充电平衡延迟电路。两个电荷平衡延迟电路等效于镜像延迟锁定环路中的延迟线。每个电荷平衡延迟电路在外部时钟信号的两个连续周期中运行一次。两个电荷平衡延迟电路交替工作，并且电荷平衡延迟电路的输出信号通过或门提供给输出缓冲器。在每个电荷平衡延迟电路中提供第一和第二电容器。第一电流源电路对第一电容器充电等于正向脉冲的延迟时间的时间。第二电容器由第二电流源电路充电。比较器将第一和第二电容器的充电电压彼此进行比较，并且当两个充电电压彼此一致时产生定时信号。

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