专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06898100B2 Semiconductor memory device used for cache memory 有权
标题翻译：半导体存储器件用于缓存存储器
公开(公告)号：US06898100B2
公开(公告)日：2005-05-24
申请号：US10736849
申请日：2003-12-17
申请人： Fumihiro Kohno
发明人： Fumihiro Kohno
IPC分类号： G06F12/08 , G11C11/41 , G11C15/00 , G11C15/04
CPC分类号： G11C15/04
摘要： A data memory circuit having divided several cache lines storing data, and several entries, and a tag circuit, are provided. The tag circuit having an array of an associative memory including a memory cell circuit having several memory cells storing address corresponding to the data stored in the data memory circuit and divided several rows, and a comparator circuit comparing the address stored in the memory cell circuit with input address, the comparator circuit comparing the address stored in divided several rows of the memory cell circuit with the input address concurrently in each of divided rows storing the address, and generating a cache hit/miss determination signal based on the comparative result of each row, the hit/miss determination signal being supplied to the data memory circuit.
摘要翻译：提供了分割存储数据的多个高速缓存行和数个条目以及标签电路的数据存储电路。所述标签电路具有包括存储单元电路的存储单元电路阵列的存储单元电路，所述存储单元电路具有多个存储单元，存储与存储在所述数据存储电路中的数据相对应的地址，并分割数行;以及比较器电路，将存储单元电路中存储的地址输入地址，所述比较器电路将存储单元电路的划分的多行的地址与存储该地址的每个分割行中的输入地址同时地进行比较，并且基于每行的比较结果生成高速缓存命中/未命中确定信号，命中/未命中确定信号被提供给数据存储电路。

2. 发明授权

US06560163B2 Semiconductor device including a repetitive pattern 失效
公开(公告)号：US06560163B2
公开(公告)日：2003-05-06
申请号：US10040479
申请日：2002-01-09
申请人： Hironobu Akita , Shinichiro Shiratake , Fumihiro Kohno
发明人： Hironobu Akita , Shinichiro Shiratake , Fumihiro Kohno
IPC分类号： G11C800
CPC分类号： G11C8/10 , G11C8/14 , G11C11/4087 , H01L27/10897
摘要： The present invention provides a DRAM in which a first repetitive unit including a plurality of decoders for selecting a plurality of word lines and a second repetitive unit having the same arrangement as that of the first repetitive unit are arranged symmetrically with respect a boundary region therebetween. The first and second repetitive units have a wire and a contact located on a boundary portion therebetween in common.

3. 发明授权

US06538955B2 Semiconductor integrated circuit for which high voltage countermeasure was taken 失效
公开(公告)号：US06538955B2
公开(公告)日：2003-03-25
申请号：US09906116
申请日：2001-07-17
申请人： Fumihiro Kohno
发明人： Fumihiro Kohno
IPC分类号： G11C800
CPC分类号： G11C8/08
摘要： There are provided a plurality of CMOS configured pre-driver circuits, wherein an increased voltage obtained by increasing a power voltage is applied to a source of each P-channel transistor, and a word line driver circuit each having a P-channel transistor and an N-channel transistor to which an output of the pre-driver circuit is inputted. The source of each N-channel transistor in the plurality of pre-driver circuits is connected in common to that of each N-channel transistor in the word line driver circuit, and a source-drain path of an N-channel transistor for voltage alleviation is connected between this source common node and a node of a grounding voltage. The increased voltage is applied to a gate of the N-channel transistor for voltage alleviation.

4. 发明授权

US06452833B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06452833B2
公开(公告)日：2002-09-17
申请号：US09773606
申请日：2001-02-02
申请人： Hironobu Akita , Kenji Tsuchida , Fumihiro Kohno
发明人： Hironobu Akita , Kenji Tsuchida , Fumihiro Kohno
IPC分类号： G11C1124
CPC分类号： G11C7/12 , G11C11/4094
摘要： A BL kicker circuit includes first capacitors each of which is connected at one end to a first bit line which is one of bit lines of a corresponding pair and commonly connected at the other end, second capacitors each of which is connected at one end to a second bit line which is the other one of the bit lines of a corresponding pair and commonly connected at the other end, a first driver circuit having an output node for a first signal connected to the common connection node of the other ends of the first capacitors, a second drive circuit having an output node for a second signal connected to the common connection node of the other ends of the second capacitors, and a switch circuit used as an equalizing circuit connected between the output node for the first signal and the output node for the second signal.
摘要翻译： BL激光电路包括第一电容器，每个电容器的一端连接到第一位线，第一位线是相应对的位线之一，并且在另一端共同连接，第二电容器的一端连接到一端第二位线，其是相应对中的另一个位线并且在另一端共同连接，第一驱动器电路具有用于连接到第一电容器的另一端的公共连接节点的第一信号的输出节点具有连接到第二电容器的另一端的公共连接节点的第二信号的输出节点的第二驱动电路和用作连接在第一信号的输出节点和输出节点之间的均衡电路的开关电路对于第二个信号。

5. 发明授权

US6125071A Semiconductor memory device with high data read rate 有权
标题翻译：具有高数据读取速率的半导体存储器件
公开(公告)号：US6125071A
公开(公告)日：2000-09-26
申请号：US296268
申请日：1999-04-22
申请人： Fumihiro Kohno , Haruki Toda
发明人： Fumihiro Kohno , Haruki Toda
IPC分类号： G11C11/401 , G11C8/08 , G11C8/10 , G11C8/00
CPC分类号： G11C8/10 , G11C8/08
摘要： A memory cell array has a plurality of memory cells arranged in a matrix. A row decoder has a multiple selection period when a plurality of word lines are simultaneously selected and word lines are sequentially selected. A plurality of sense amplifiers are arranged for each bit line. These sense amplifiers are selectively connected to the bit lines by switch circuits formed on the bit lines. A sense amplifier receives data from memory cells on one bit line through a switch circuit. A plurality of word lines are simultaneously selected and sequentially set at a high level. Data from memory cells on one bit line are sequentially received by the sense amplifier and amplified.
摘要翻译：存储单元阵列具有以矩阵形式布置的多个存储单元。行解码器在同时选择多个字线并顺序地选择字线时具有多个选择周期。为每个位线布置多个读出放大器。这些读出放大器通过形成在位线上的开关电路选择性地连接到位线。读出放大器通过开关电路从一个位线上的存储器单元接收数据。同时选择多个字线并依次设置在高电平。来自一个位线上的存储器单元的数据被读出放大器依次接收并放大。

6. 发明授权

US06044035A Semiconductor memory device having level-shifted precharge signal 有权
标题翻译：具有电平移位预充电信号的半导体存储器件
公开(公告)号：US06044035A
公开(公告)日：2000-03-28
申请号：US168673
申请日：1998-10-09
申请人： Fumihiro Kohno
发明人： Fumihiro Kohno
IPC分类号： G11C11/407 , G11C7/00 , G11C8/00 , G11C8/08 , G11C8/10 , G11C11/401 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： G11C8/08 , G11C8/10
摘要： A semiconductor memory device comprising a plurality of row decoders, each having a precharge circuit connected to receive a precharge signal and a decode circuit connected to receive address signals. A level-shifted precharge signal is input to the precharge circuits.
摘要翻译：一种半导体存储器件，包括多个行解码器，每个行解码器具有连接以接收预充电信号的预充电电路和连接以接收地址信号的解码电路。电平移位的预充电信号被输入到预充电电路。

7. 发明授权

US5943285A Arrangement of memory blocks and pads 失效
标题翻译：记忆块和垫的排列
公开(公告)号：US5943285A
公开(公告)日：1999-08-24
申请号：US904955
申请日：1997-08-01
申请人： Fumihiro Kohno
发明人： Fumihiro Kohno
IPC分类号： G11C11/401 , G11C5/02 , G11C8/12 , H01L21/8242 , H01L23/50 , H01L27/108 , G11C7/00
CPC分类号： H01L23/50 , G11C5/025 , G11C8/12 , H01L27/10805 , H01L2924/0002
摘要： A semiconductor memory device adapted to enhanced functional features and a large memory capacity. The semiconductor memory device includes a semiconductor chip divided into 9 regions B1 through B9 having an identical area, in a 3.times.3 pattern. A main control block is arranged at least in a central region B9 and memory blocks are arranged respectively in the peripheral regions B1 through B8 of the 9 regions. Each of the memory blocks is controlled by the main control block and includes a data input/output circuit and a memory control circuit.
摘要翻译：一种适于增强功能特征和大存储容量的半导体存储器件。半导体存储器件包括以3×3图案划分为具有相同面积的9个区域B1至B9的半导体芯片。主控制块至少布置在中央区域B9中，并且存储块分别布置在9个区域的周边区域B1至B8中。每个存储器块由主控制块控制并且包括数据输入/输出电路和存储器控制电路。

8. 发明授权

US5838629A Semiconductor memory device having level-shifted precharge signal 失效
公开(公告)号：US5838629A
公开(公告)日：1998-11-17
申请号：US907030
申请日：1997-08-06
申请人： Fumihiro Kohno
发明人： Fumihiro Kohno
IPC分类号： G11C11/407 , G11C7/00 , G11C8/00 , G11C8/08 , G11C8/10 , G11C11/401 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： G11C8/08 , G11C8/10
摘要： A semiconductor memory device comprising a plurality of row decoders, each having a precharge circuit connected to receive a precharge signal and a decode circuit connected to receive address signals. A level-shifted precharge signal is input to the precharge circuits.

9. 发明授权

US5825714A Semiconductor memory device having noise killer circuit 失效
标题翻译：具有噪声抑制电路的半导体存储器件
公开(公告)号：US5825714A
公开(公告)日：1998-10-20
申请号：US379290
申请日：1995-01-27
申请人： Fumihiro Kohno
发明人： Fumihiro Kohno
IPC分类号： G11C11/407 , G11C7/00 , G11C8/00 , G11C8/08 , G11C8/10 , G11C11/401 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： G11C8/08 , G11C8/10
摘要： A semiconductor memory device comprising a plurality of row decoders, each having a precharge circuit connected to receive a precharge signal and a decode circuit connected to receive address signals. A level-shifted precharge signal is input to the precharge circuits.
摘要翻译：一种半导体存储器件，包括多个行解码器，每个行解码器具有连接以接收预充电信号的预充电电路和连接以接收地址信号的解码电路。电平移位的预充电信号被输入到预充电电路。

10. 发明授权

US5793695A Semiconductor memory device having level-shifted precharge signal 失效
公开(公告)号：US5793695A
公开(公告)日：1998-08-11
申请号：US696738
申请日：1996-08-14
申请人： Fumihiro Kohno
发明人： Fumihiro Kohno
IPC分类号： G11C11/407 , G11C7/00 , G11C8/00 , G11C8/08 , G11C8/10 , G11C11/401 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： G11C8/08 , G11C8/10
摘要： A semiconductor memory device comprising a plurality of row decoders, each having a precharge circuit connected to receive a precharge signal and a decode circuit connected to receive address signals. A level-shifted precharge signal is input to the precharge circuits.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式