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1. 发明授权

US06212090B1 Semiconductor device including a repetitive pattern 失效
公开(公告)号：US06212090B1
公开(公告)日：2001-04-03
申请号：US09471038
申请日：1999-12-23
申请人： Hironobu Akita , Shinichiro Shiratake , Fumihiro Kohno
发明人： Hironobu Akita , Shinichiro Shiratake , Fumihiro Kohno
IPC分类号： G11C506
CPC分类号： G11C8/10 , G11C8/14 , G11C11/4087 , H01L27/10897
摘要： The present invention provides a DRAM in which a first repetitive unit including a plurality of decoders for selecting a plurality of word lines and a second repetitive unit having the same arrangement as that of the first repetitive unit are arranged symmetrically with respect a boundary region therebetween. The first and second repetitive units have a wire and a contact located on a boundary portion therebetween in common.

2. 发明授权

US06362999B1 Semiconductor device including a repetitive pattern 有权
公开(公告)号：US06362999B1
公开(公告)日：2002-03-26
申请号：US09772069
申请日：2001-01-30
申请人： Hironobu Akita , Shinichiro Shiratake , Fumihiro Kohno
发明人： Hironobu Akita , Shinichiro Shiratake , Fumihiro Kohno
IPC分类号： G11C506
摘要： The present invention provides a DRAM in which a first repetitive unit including a plurality of decoders for selecting a plurality of word lines and a second repetitive unit having the same arrangement as that of the first repetitive unit are arranged symmetrically with respect a boundary region therebetween. The first and second repetitive units have a wire and a contact located on a boundary portion therebetween in common.

3. 发明授权

US06560163B2 Semiconductor device including a repetitive pattern 失效
公开(公告)号：US06560163B2
公开(公告)日：2003-05-06
申请号：US10040479
申请日：2002-01-09
申请人： Hironobu Akita , Shinichiro Shiratake , Fumihiro Kohno
发明人： Hironobu Akita , Shinichiro Shiratake , Fumihiro Kohno
IPC分类号： G11C800
CPC分类号： G11C8/10 , G11C8/14 , G11C11/4087 , H01L27/10897
摘要： The present invention provides a DRAM in which a first repetitive unit including a plurality of decoders for selecting a plurality of word lines and a second repetitive unit having the same arrangement as that of the first repetitive unit are arranged symmetrically with respect a boundary region therebetween. The first and second repetitive units have a wire and a contact located on a boundary portion therebetween in common.

4. 发明授权

US06452833B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06452833B2
公开(公告)日：2002-09-17
申请号：US09773606
申请日：2001-02-02
申请人： Hironobu Akita , Kenji Tsuchida , Fumihiro Kohno
发明人： Hironobu Akita , Kenji Tsuchida , Fumihiro Kohno
IPC分类号： G11C1124
CPC分类号： G11C7/12 , G11C11/4094
摘要： A BL kicker circuit includes first capacitors each of which is connected at one end to a first bit line which is one of bit lines of a corresponding pair and commonly connected at the other end, second capacitors each of which is connected at one end to a second bit line which is the other one of the bit lines of a corresponding pair and commonly connected at the other end, a first driver circuit having an output node for a first signal connected to the common connection node of the other ends of the first capacitors, a second drive circuit having an output node for a second signal connected to the common connection node of the other ends of the second capacitors, and a switch circuit used as an equalizing circuit connected between the output node for the first signal and the output node for the second signal.
摘要翻译： BL激光电路包括第一电容器，每个电容器的一端连接到第一位线，第一位线是相应对的位线之一，并且在另一端共同连接，第二电容器的一端连接到一端第二位线，其是相应对中的另一个位线并且在另一端共同连接，第一驱动器电路具有用于连接到第一电容器的另一端的公共连接节点的第一信号的输出节点具有连接到第二电容器的另一端的公共连接节点的第二信号的输出节点的第二驱动电路和用作连接在第一信号的输出节点和输出节点之间的均衡电路的开关电路对于第二个信号。

5. 发明授权

US06269047B1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06269047B1
公开(公告)日：2001-07-31
申请号：US09618163
申请日：2000-07-17
申请人： Fumihiro Kohno
发明人： Fumihiro Kohno
IPC分类号： G11C700
CPC分类号： G11C8/08 , G11C8/10
摘要： A semiconductor memory device comprising a plurality of row decoders, each having a precharge circuit connected to receive a precharge signal and a decode circuit connected to receive address signals. A level-shifted precharge signal is input to the precharge circuits.
摘要翻译：一种半导体存储器件，包括多个行解码器，每个行解码器具有连接以接收预充电信号的预充电电路和连接以接收地址信号的解码电路。电平移位的预充电信号被输入到预充电电路。

6. 发明授权

US07248520B2 Semiconductor memory and data read method of the same 失效
标题翻译：半导体存储器和数据读取方法相同
公开(公告)号：US07248520B2
公开(公告)日：2007-07-24
申请号：US11297380
申请日：2005-12-09
申请人： Fumihiro Kohno
发明人： Fumihiro Kohno
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C11/413
摘要： A semiconductor memory having memory cells each storing first data and second data in a memory cell array arranged in a column direction; a plurality of word lines connected to the memory cells in a row direction; and first and second bit lines, to which the first and second data are respectively read out, in the column direction. When one of the first and second bit lines changes from a first potential to a second potential lower than the first potential after data read out, the potential of the other bit line is changed from the second to the first potential, and if the electric potential of the selected bit line changes from the first to the second potential when data is read out, the other bit line is selected when the data is next read out, and, if the electric potential of the selected bit line maintains the first potential, the selected bit line is maintained selected even when the data is to be read out next.
摘要翻译：一种具有存储单元的半导体存储器，每个存储单元存储沿列方向布置的存储单元阵列中的第一数据和第二数据; 在行方向连接到存储单元的多个字线; 以及在列方向上分别读出第一和第二数据的第一和第二位线。当数据读出之后，当第一和第二位线之一从第一电位变为低于第一电位的第二电位时，另一位线的电位从第二电位变为第一电位，如果电位当数据被读出时，所选位线从第一电位变为第二电位，当下一次读出数据时选择另一位线，如果选定位线的电位保持第一电位，则即使下一次要读出数据，仍选择所选择的位线。

7. 发明授权

US06847579B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06847579B2
公开(公告)日：2005-01-25
申请号：US10133382
申请日：2002-04-29
申请人： Fumihiro Kohno , Toshimi Ikeda
发明人： Fumihiro Kohno , Toshimi Ikeda
IPC分类号： G11C11/407 , G11C8/08 , G11C8/10 , G11C11/408 , G11C7/00 , G11C8/00
CPC分类号： G11C8/08 , G11C8/10 , G11C11/4087
摘要： A semiconductor memory device includes a memory cell array having a plurality of memory cells. The memory cells are arranged at intersections between a plurality of word lines and a plurality of bit lines. The semiconductor memory device also includes a row decoder section located adjacent to the memory cell array. The row decoder section has a plurality of decoder circuits which selectively drive the word lines. The semiconductor memory device further includes a control circuit section located adjacent to the row decoder section. The control circuit section has at least one control circuit whose part is arranged in the row decoder section.
摘要翻译：半导体存储器件包括具有多个存储单元的存储单元阵列。存储单元布置在多个字线和多个位线之间的交点处。半导体存储器件还包括位于存储单元阵列附近的行解码器部分。行解码器部分具有选择性地驱动字线的多个解码器电路。半导体存储器件还包括位于行解码器部分附近的控制电路部分。控制电路部分具有至少一个控制电路，其部分被布置在行解码器部分中。

8. 发明授权

US6041013A Semiconductor memory device, method of laying out semiconductor memory device, method of driving semiconductor pattern of semiconductor device 失效
标题翻译：半导体存储器件，布线半导体存储器件的方法，半导体器件的半导体图案的驱动方法
公开(公告)号：US6041013A
公开(公告)日：2000-03-21
申请号：US289964
申请日：1999-04-13
申请人： Fumihiro Kohno
发明人： Fumihiro Kohno
IPC分类号： G11C11/401 , G11C5/02 , G11C8/12 , H01L21/8242 , H01L23/50 , H01L27/108 , G11C8/00
CPC分类号： H01L23/50 , G11C5/025 , G11C8/12 , H01L27/10805 , H01L2924/0002
摘要： A semiconductor memory device adapted to enhanced functional features and a large memory capacity. The semiconductor memory device includes a semiconductor chip divided into 9 regions B1 through B9 having an identical area, in a 3.times.3 pattern. A main control block is arranged at least in a central region B9 and memory blocks are arranged respectively in the peripheral regions B1 through B8 of the 9 regions. Each of the memory blocks is controlled by the main control block and includes a data input/output circuit and a memory control circuit.
摘要翻译：一种适于增强功能特征和大存储容量的半导体存储器件。半导体存储器件包括以3×3图案划分为具有相同面积的9个区域B1至B9的半导体芯片。主控制块至少布置在中央区域B9中，并且存储块分别布置在9个区域的周边区域B1至B8中。每个存储器块由主控制块控制并且包括数据输入/输出电路和存储器控制电路。

9. 发明申请

US20060203583A1 Semiconductor memory and data read method of the same 失效
标题翻译：半导体存储器和数据读取方法相同
公开(公告)号：US20060203583A1
公开(公告)日：2006-09-14
申请号：US11297380
申请日：2005-12-09
申请人： Fumihiro Kohno
发明人： Fumihiro Kohno
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C11/413
摘要： According to the present invention, there is provided a semiconductor memory having: a memory cell array in which a plurality of memory cells each holding data made up of first data and second data are arranged at least along a column direction; a plurality of word lines running along a row direction in the memory cell array, and connected to the memory cells; a first bit line which runs along the column direction in the memory cell array and is connected to the memory cells, and to which the first data is read out from the memory cell when the data is read out from the memory cell; a second bit line which runs along the column direction in the memory cell array and is connected to the memory cells, and to which the second data is read out from the memory cell when the data is read out from the memory cell; a bit line precharge unit which, when detecting that an electric potential of one of the first and second bit lines changes from a first potential to a second potential lower than the first potential after the data is read out from the memory cell, changes an electric potential of the other bit line from the second potential to the first potential; and a bit line selector which, if the electric potential of the selected one of the first and second bit lines changes from the first potential to the second potential when the data is read out, selects the other bit line when the data is to be read out next, and, if the electric potential of the selected one of the first and second bit lines maintains the first potential, keeps selecting the selected bit line even when the data is to be read out next.
摘要翻译：根据本发明，提供了一种半导体存储器，其具有：存储单元阵列，其中，至少沿列方向布置多个存储单元，每个存储单元保持由第一数据和第二数据构成的数据; 在存储单元阵列中沿着行方向延伸并连接到存储单元的多个字线; 第一位线沿着存储单元阵列中的列方向延伸并连接到存储单元，并且当从存储单元读出数据时从存储单元读出第一数据; 第二位线，沿着存储单元阵列中的列方向延伸并连接到存储单元，并且当从存储单元读出数据时，从存储单元读出第二数据; 位线预充电单元，当从存储单元读出数据之后，当检测到第一和第二位线中的一个的电位从第一电位变为低于第一电位的第二电位时，另一个位线从第二个电位到第一个电位的电位; 以及位线选择器，如果当读出数据时第一和第二位线中所选择的一个电位从第一电位变为第二电位，则当数据被读取时选择另一个位线并且如果所选择的第一位和第二位线之一的电位保持第一电位，则即使在接下来要读出数据时也继续选择所选择的位线。

10. 发明申请

US20050083719A1 SEMICONDUCTOR MEMORY DEVICE USED FOR CACHE MEMORY 有权
标题翻译：用于缓存存储器的半导体存储器件
公开(公告)号：US20050083719A1
公开(公告)日：2005-04-21
申请号：US10736849
申请日：2003-12-17
申请人： Fumihiro Kohno
发明人： Fumihiro Kohno
IPC分类号： G06F12/08 , G11C11/41 , G11C15/00 , G11C15/04
CPC分类号： G11C15/04
摘要： A data memory circuit having divided several cache lines storing data, and several entries, and a tag circuit, are provided. The tag circuit having an array of an associative memory including a memory cell circuit having several memory cells storing address corresponding to the data stored in the data memory circuit and divided several rows, and a comparator circuit comparing the address stored in the memory cell circuit with input address, the comparator circuit comparing the address stored in divided several rows of the memory cell circuit with the input address concurrently in each of divided rows storing the address, and generating a cache hit/miss determination signal based on the comparative result of each row, the hit/miss determination signal being supplied to the data memory circuit.
摘要翻译：提供了分割存储数据的多个高速缓存行和数个条目以及标签电路的数据存储电路。所述标签电路具有包括存储单元电路的存储单元电路阵列的存储单元电路，所述存储单元电路具有多个存储单元，存储与存储在所述数据存储电路中的数据相对应的地址，并分割数行;以及比较器电路，将存储单元电路中存储的地址输入地址，所述比较器电路将存储单元电路的划分的多行的地址与存储该地址的每个分割行中的输入地址同时地进行比较，并且基于每行的比较结果生成高速缓存命中/未命中确定信号，命中/未命中确定信号被提供给数据存储电路。

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