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1. 发明授权

US06362999B1 Semiconductor device including a repetitive pattern 有权
公开(公告)号：US06362999B1
公开(公告)日：2002-03-26
申请号：US09772069
申请日：2001-01-30
申请人： Hironobu Akita , Shinichiro Shiratake , Fumihiro Kohno
发明人： Hironobu Akita , Shinichiro Shiratake , Fumihiro Kohno
IPC分类号： G11C506
摘要： The present invention provides a DRAM in which a first repetitive unit including a plurality of decoders for selecting a plurality of word lines and a second repetitive unit having the same arrangement as that of the first repetitive unit are arranged symmetrically with respect a boundary region therebetween. The first and second repetitive units have a wire and a contact located on a boundary portion therebetween in common.

2. 发明授权

US06212090B1 Semiconductor device including a repetitive pattern 失效
公开(公告)号：US06212090B1
公开(公告)日：2001-04-03
申请号：US09471038
申请日：1999-12-23
申请人： Hironobu Akita , Shinichiro Shiratake , Fumihiro Kohno
发明人： Hironobu Akita , Shinichiro Shiratake , Fumihiro Kohno
IPC分类号： G11C506
CPC分类号： G11C8/10 , G11C8/14 , G11C11/4087 , H01L27/10897
摘要： The present invention provides a DRAM in which a first repetitive unit including a plurality of decoders for selecting a plurality of word lines and a second repetitive unit having the same arrangement as that of the first repetitive unit are arranged symmetrically with respect a boundary region therebetween. The first and second repetitive units have a wire and a contact located on a boundary portion therebetween in common.

3. 发明授权

US06560163B2 Semiconductor device including a repetitive pattern 失效
公开(公告)号：US06560163B2
公开(公告)日：2003-05-06
申请号：US10040479
申请日：2002-01-09
申请人： Hironobu Akita , Shinichiro Shiratake , Fumihiro Kohno
发明人： Hironobu Akita , Shinichiro Shiratake , Fumihiro Kohno
IPC分类号： G11C800
CPC分类号： G11C8/10 , G11C8/14 , G11C11/4087 , H01L27/10897
摘要： The present invention provides a DRAM in which a first repetitive unit including a plurality of decoders for selecting a plurality of word lines and a second repetitive unit having the same arrangement as that of the first repetitive unit are arranged symmetrically with respect a boundary region therebetween. The first and second repetitive units have a wire and a contact located on a boundary portion therebetween in common.

4. 发明授权

US06452833B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06452833B2
公开(公告)日：2002-09-17
申请号：US09773606
申请日：2001-02-02
申请人： Hironobu Akita , Kenji Tsuchida , Fumihiro Kohno
发明人： Hironobu Akita , Kenji Tsuchida , Fumihiro Kohno
IPC分类号： G11C1124
CPC分类号： G11C7/12 , G11C11/4094
摘要： A BL kicker circuit includes first capacitors each of which is connected at one end to a first bit line which is one of bit lines of a corresponding pair and commonly connected at the other end, second capacitors each of which is connected at one end to a second bit line which is the other one of the bit lines of a corresponding pair and commonly connected at the other end, a first driver circuit having an output node for a first signal connected to the common connection node of the other ends of the first capacitors, a second drive circuit having an output node for a second signal connected to the common connection node of the other ends of the second capacitors, and a switch circuit used as an equalizing circuit connected between the output node for the first signal and the output node for the second signal.
摘要翻译： BL激光电路包括第一电容器，每个电容器的一端连接到第一位线，第一位线是相应对的位线之一，并且在另一端共同连接，第二电容器的一端连接到一端第二位线，其是相应对中的另一个位线并且在另一端共同连接，第一驱动器电路具有用于连接到第一电容器的另一端的公共连接节点的第一信号的输出节点具有连接到第二电容器的另一端的公共连接节点的第二信号的输出节点的第二驱动电路和用作连接在第一信号的输出节点和输出节点之间的均衡电路的开关电路对于第二个信号。

5. 发明授权

US09418583B2 Transmission device, reception device, transmission-reception system, and image display system 有权
标题翻译：发送装置，接收装置，发送接收系统和图像显示系统
公开(公告)号：US09418583B2
公开(公告)日：2016-08-16
申请号：US13517462
申请日：2010-12-13
申请人： Seiichi Ozawa , Hironobu Akita
发明人： Seiichi Ozawa , Hironobu Akita
IPC分类号： G09G5/00 , G09G3/20 , G09G3/36 , H04L25/02
CPC分类号： G09G3/20 , G09G3/3611 , G09G2300/0426 , G09G2310/08 , G09G2370/08 , H04L25/0264
摘要： Reception devices 201 to 20N are arranged one-dimensionally in this order. The reception device 20n has a data input buffer 21, a first clock input buffer 221, and a first clock output buffer 231. The first clock input buffer 221 buffers a clock input to the first clock terminals P21 and P22, and outputs it to the first clock output buffer 231. The first clock output buffer 231 buffers a clock input from the first clock input buffer 221 and outputs it from the second clock terminals P31 and P32. The data input terminals P11 and P12 are located between the first clock terminal and the second clock terminal.
摘要翻译：接收装置201〜20N依次排列成一维。接收装置20n具有数据输入缓冲器21，第一时钟输入缓冲器221和第一时钟输出缓冲器231.第一时钟输入缓冲器221缓冲输入到第一时钟端子P21和P22的时钟，并将其输出到第一时钟输出缓冲器231缓冲从第一时钟输入缓冲器221输入的时钟并将其从第二时钟端子P31和P32输出。数据输入端子P11和P12位于第一时钟端子和第二时钟端子之间。

6. 发明授权

US06608514B1 Clock signal generator circuit and semiconductor integrated circuit with the same circuit 失效
标题翻译：时钟信号发生器电路和半导体集成电路具有相同的电路
公开(公告)号：US06608514B1
公开(公告)日：2003-08-19
申请号：US09511352
申请日：2000-02-23
申请人： Hironobu Akita , Katsuaki Isobe , Masaharu Wada , Kenji Tsuchida , Haruki Toda
发明人： Hironobu Akita , Katsuaki Isobe , Masaharu Wada , Kenji Tsuchida , Haruki Toda
IPC分类号： H03K300
CPC分类号： G11C7/222 , G11C7/22 , H03K5/00006 , H03K5/135
摘要： A clock signal generator circuit comprises an off-chip driver, a first clock control circuit for outputting a first internal clock signal Tu synchronizing with an external clock signal CK, a second clock control circuit for outputting a second internal clock signal Td 180° out-of-phase with the external clock signal CK, a third clock control circuit for outputting a third internal clock signal aTx1 synchronizing with the first clock signal Tu and advanced in phase by at least the signal delay time in the off-chip driver, a fourth clock control circuit for outputting a fourth internal clock signal aTx2 synchronizing with the second clock signal Td and advanced in phase by at least the signal delay time in the off-chip driver, an OR circuit to which the third and fourth internal clock signals aTx1, aTx2 are inputted and which outputs a fifth internal clock signal aTx, and a fifth clock control circuit for outputting a sixth internal clock signal Tx which is in synchronization with the fifth internal clock signal aTx outputted from the OR circuit, has twice the frequency of the external clock signal CK, and is advanced in phase by the signal delay time in the off-chip driver.
摘要翻译：时钟信号发生器电路包括片外驱动器，用于输出与外部时钟信号CK同步的第一内部时钟信号Tu的第一时钟控制电路，用于将第二内部时钟信号Td 180°输出的第二时钟控制电路，与外部时钟信号CK的同相;第三时钟控制电路，用于输出与第一时钟信号Tu同步的第三内部时钟信号aTx1并至少在芯片外驱动器中的信号延迟时间相位前进;第四时钟控制电路，时钟控制电路，用于输出与第二时钟信号Td同步的第四内部时钟信号aTx2并至少在片外驱动器中的信号延迟时间相位前进;第三和第四内部时钟信号aTx1，输入aTx2并输出第五内部时钟信号aTx，以及第五时钟控制电路，用于输出与f同步的第六内部时钟信号Tx 从OR电路输出的第四内部时钟信号aTx具有外部时钟信号CK的两倍频率，并且在片外驱动器中相位提前信号延迟时间。

7. 发明授权

US06449212B1 Analog synchronization circuit for synchronizing external and internal clock signals 失效
标题翻译：模拟同步电路，用于同步外部和内部时钟信号
公开(公告)号：US06449212B1
公开(公告)日：2002-09-10
申请号：US09628449
申请日：2000-07-28
申请人： Haruki Toda , Hironobu Akita , Katsuaki Isobe
发明人： Haruki Toda , Hironobu Akita , Katsuaki Isobe
IPC分类号： G11C800
CPC分类号： H03L7/00 , H03K5/08 , H03K5/13 , H03K5/135
摘要： A first capacitor is charged by a constant current source circuit for a time corresponding to the delay time of forward pulses. A second capacitor is charged by a constant current source circuit. A comparator compares the voltages of the first and second capacitors, and outputs a timing signal when these voltages match. For this reason, a timing at which the second capacitor has been charged for a time corresponding to the delay time of backward pulses can be obtained.
摘要翻译：第一电容器由恒流源电路充电一段与正向脉冲的延迟时间对应的时间。第二电容器由恒流源电路充电。比较器比较第一和第二电容器的电压，并且当这些电压匹配时输出定时信号。因此，可以获得第二电容器已经对与反向脉冲的延迟时间相对应的时间的定时。

8. 发明授权

US06359480B1 Synchronizing circuit for generating a signal synchronizing with a clock signal 失效
公开(公告)号：US06359480B1
公开(公告)日：2002-03-19
申请号：US09505204
申请日：2000-02-16
申请人： Katsuaki Isobe , Tsuneo Inaba , Hironobu Akita
发明人： Katsuaki Isobe , Tsuneo Inaba , Hironobu Akita
IPC分类号： H03L700
CPC分类号： H03K5/135 , H03K5/133 , H03L7/00
摘要： A first delay line for forward pulses and a second delay line for backward pulses are composed of unit delay elements. A state holding section determines the input position of a backward pulse on the second delay line according to the transfer position of a forward pulse transferred along the first delay line. In the unit delay elements constituting the first and second delay lines, the accuracy of synchronization can be improved by increasing the current driving capability of the transistors related to the rising of the pulse signal.

9. 发明授权

US06326834B1 Pump circuit boosting a supply voltage 失效
标题翻译：泵电路提升电源电压
公开(公告)号：US06326834B1
公开(公告)日：2001-12-04
申请号：US09602896
申请日：2000-06-23
申请人： Hironobu Akita , Masaharu Wada , Kenji Tsuchida , Hironori Banba
发明人： Hironobu Akita , Masaharu Wada , Kenji Tsuchida , Hironori Banba
IPC分类号： G05F110
CPC分类号： H02M3/073
摘要： First transistors for charging respective one side nodes of a plurality of capacitors are connected to these nodes of the capacitors, respectively. Second transistors for outputting electric charge of each capacitor are connected between respective one side nodes of the capacitors and an output terminal, respectively. A plurality of third transistors for transferring the electric charge of the other side nodes of the capacitors to the other nodes are connected to the respective other nodes. The electric charge of each capacitor is serially transferred from nodes of a high electric potential to nodes of a lower electric potential through one path by sequentially controlling the third transistors, or the electric charge of each capacitor is parallel transferred between arbitrary nodes of a high electric potential and low nodes through a plurality of paths. By these operations, electric charge of each capacitor is recycled.
摘要翻译：用于对多个电容器的各个侧面节点进行充电的第一晶体管分别连接到电容器的这些节点。用于输出每个电容器的电荷的第二晶体管分别连接在电容器的相应的一个侧面节点和输出端子之间。用于将电容器的另一侧节点的电荷转移到其他节点的多个第三晶体管连接到相应的其他节点。每个电容器的电荷通过顺序地控制第三晶体管，通过一个路径从高电位的节点被串行地传递到较低电位的节点，或者每个电容器的电荷在高电位的任意节点之间并行传送潜在和低节点通过多个路径。通过这些操作，每个电容器的电荷被再循环。

10. 发明授权

US6154402A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US6154402A
公开(公告)日：2000-11-28
申请号：US398201
申请日：1999-09-17
申请人： Hironobu Akita
发明人： Hironobu Akita
IPC分类号： G11C11/409 , G11C7/06 , G11C7/12 , G11C7/00
CPC分类号： G11C7/06 , G11C7/12
摘要： In a semiconductor memory device, charge transfer gates and a bit line precharging/equalizing circuit are inserted in the order mentioned in a bit line pair between memory cells and a sense amplifier. When the transfer gates are off, data of the memory cells are read out to the bit line pair located on the memory cell side. Subsequently, when the transfer gates are turned on, the data are transferred to the bit line pair located on the sense amplifier side. Thereafter, the transfer gates are turned off on the basis of a threshold value of the transfer gates. Then, the memory cell data transferred to the sense amplifier side are amplified by a conventional DRAM method. The bit line precharging/equalizing circuit does not require a large area. It is therefore possible to miniaturize the semiconductor memory device.
摘要翻译：在半导体存储器件中，按照存储器单元和读出放大器之间的位线对中所述的顺序插入电荷传输门和位线预充电/均衡电路。当传输门关闭时，存储器单元的数据被读出到位于存储单元侧的位线对。随后，当传输门被接通时，数据被传送到位于读出放大器侧的位线对。此后，基于传送门的阈值关闭传送门。然后，通过传统的DRAM方法放大传送到读出放大器侧的存储单元数据。位线预充电/均衡电路不需要大面积。因此，可以使半导体存储器件小型化。

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