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31. 发明申请

US20090092215A1 DATA RELAY APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME 失效
标题翻译：数据继电器和半导体集成电路
公开(公告)号：US20090092215A1
公开(公告)日：2009-04-09
申请号：US12038616
申请日：2008-02-27
申请人： Ic-Su Oh , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee
发明人： Ic-Su Oh , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee
IPC分类号： H04L7/00
CPC分类号： H03K5/135 , H03L7/06
摘要： A data relay apparatus according to one embodiment described herein can include a phase detection unit that can detect a phase difference between a clock output from a transmitter and a clock output from a receiver, and generate a plurality of phase detection signals, a data relay control unit that can distinguish a difference in clock timing between the clocks of the transmitter and the receiver in response to the plurality of phase detection signals, and output a relay data selection signal and a relay control clock, and a data relay unit that can transmit data output from the receiver to the transmitter in response to the relay data selection signal and the relay control clock.
摘要翻译：根据本文所述的一个实施例的数据中继装置可以包括相位检测单元，其可以检测从发送器输出的时钟与从接收器输出的时钟之间的相位差，并且生成多个相位检测信号，数据中继控制单元，其可以响应于所述多个相位检测信号来区分发射机和接收机的时钟之间的时钟定时的差异，并且输出中继数据选择信号和中继控制时钟，以及可以发送数据的数据中继单元响应于继电器数据选择信号和继电器控制时钟从接收器输出到发送器。

32. 发明申请

US20090058476A1 RECEIVER CIRCUIT FOR USE IN A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：在半导体集成电路中使用的接收器电路
公开(公告)号：US20090058476A1
公开(公告)日：2009-03-05
申请号：US12171214
申请日：2008-07-10
申请人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： H03L7/00
CPC分类号： H04L7/0337
摘要： A receiver circuit for sensing and transmitting input data in sync with a plurality of clock signals having mutually different phase sequentially enabled comprising a sense amplifier configured to receive, as offset voltages, first signals which can be obtained by amplifying the input data in sync with a first clock signal of the plurality of clock signals, being driven in sync with a second clock signal enabled subsequently to the first clock signal, and outputting second signals, and a discharging controller configured to control a discharging speed of the sense amplifier according to the offset voltages to control a driven speed of the sense amplifier.
摘要翻译：一种接收机电路，用于与具有相互不同相位的多个时钟信号同步地感测和发送输入数据，其顺序地使能，包括读出放大器，其被配置为接收作为偏移电压的第一信号，所述第一信号可以通过与所述多个时钟信号的第一时钟信号与与所述第一时钟信号之后使能的第二时钟信号同步地驱动，并输出第二信号;以及放电控制器，被配置为根据所述偏移来控制所述读出放大器的放电速度电压来控制读出放大器的驱动速度。

33. 发明申请

US20090041172A1 PHASE DETECTION CIRCUIT 有权
标题翻译：相位检测电路
公开(公告)号：US20090041172A1
公开(公告)日：2009-02-12
申请号：US12018770
申请日：2008-01-23
申请人： Yong Ju Kim , Kun Woo Park , Jong Woon Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang
发明人： Yong Ju Kim , Kun Woo Park , Jong Woon Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H03L7/085 , H03L7/091 , H03L7/10
摘要： A phase detection circuit includes a phase frequency detector for comparing a first input signal and a second input signal and outputting a first phase comparison signal and a second phase comparison signal, and a sensing circuit for sensing a pulse width difference between the first phase comparison signal and the second phase comparison signal and outputting phase detection signals which have different logic values.
摘要翻译：相位检测电路包括：相位频率检测器，用于比较第一输入信号和第二输入信号，并输出第一相位比较信号和第二相位比较信号;以及感测电路，用于感测第一相位比较信号和第二相位比较信号，并输出具有不同逻辑值的相位检测信号。

34. 发明申请

US20080252353A1 VOLTAGE MEASURING APPARATUS FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND VOLTAGE MEASURING SYSTEM HAVING THE SAME 有权
标题翻译：用于半导体集成电路的电压测量装置及其电压测量系统
公开(公告)号：US20080252353A1
公开(公告)日：2008-10-16
申请号：US11961988
申请日：2007-12-20
申请人： Hyung Soo Kim , Yong Ju Kim , Jong Woon Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang
发明人： Hyung Soo Kim , Yong Ju Kim , Jong Woon Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang
IPC分类号： H03H11/26
CPC分类号： G01R31/3004 , G01R29/26
摘要： A voltage measuring apparatus for a semiconductor integrated circuit includes a first delay unit configured to delay a reference clock in a first region, a second delay unit configured to delay the reference clock in a second region and an analysis unit configured to analyze a difference in voltage level between the regions based on the phases of associated with the delayed clock signals generated by the first and second delay units.
摘要翻译：一种用于半导体集成电路的电压测量装置包括：第一延迟单元，被配置为延迟第一区域中的参考时钟;第二延迟单元，被配置为在第二区域中延迟参考时钟;以及分析单元，被配置为分析电压差基于与由第一延迟单元和第二延迟单元生成的延迟时钟信号相关联的相位，区域之间的电平。

35. 发明申请

US20080068057A1 PLL circuit and method of controlling the same 失效
标题翻译： PLL电路及其控制方法
公开(公告)号：US20080068057A1
公开(公告)日：2008-03-20
申请号：US11819603
申请日：2007-06-28
申请人： Yong Ju Kim , Kun Woo Park , Jong Woon Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang
发明人： Yong Ju Kim , Kun Woo Park , Jong Woon Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang
IPC分类号： H03L7/085 , H03L7/08
CPC分类号： H03L7/0893 , H03L7/093 , H03L7/10
摘要： A PLL circuit includes a phase detector that compares the phase of an input clock with the phase of a feedback clock so as to generate pull-up and pull-down control signals. A low pass filter pumps a voltage in response to the pull-up and pull-down control signals, and removes a noise component from the pumped voltage so as to output a control voltage. A buffer that controls voltage so as to generate a bias voltage having a smaller swing width than the control voltage. A voltage controlled oscillator receives the bias voltage and oscillates an output clock. A clock divider divides the frequency of the output clock at a predetermined ratio so as to generate the feedback clock.
摘要翻译： PLL电路包括相位检测器，其将输入时钟的相位与反馈时钟的相位进行比较，以产生上拉和下拉控制信号。低通滤波器响应于上拉和下拉控制信号泵送电压，并从泵浦电压中去除噪声分量，以输出控制电压。控制电压以产生具有比控制电压更小的摆动宽度的偏置电压的缓冲器。压控振荡器接收偏置电压并振荡输出时钟。时钟分频器以预定的比例对输出时钟的频率进行分频，以产生反馈时钟。

36. 发明授权

US5984775A Grating and shutter apparatus for controlling air flow 失效
标题翻译：用于控制气流的光栅和快门装置
公开(公告)号：US5984775A
公开(公告)日：1999-11-16
申请号：US953380
申请日：1997-10-17
申请人： Kun-hyung Lee , Tae-jin Hwang
发明人： Kun-hyung Lee , Tae-jin Hwang
IPC分类号： F24F7/06 , F24F13/08 , F24F13/12 , H01L21/02
CPC分类号： F24F13/12
摘要： An apparatus for controlling air flow includes a grating having a plurality of air vents, a shutter assembly composed of a shutter fixed plate, having a plurality of first openings, attached to a lower surface of the grating, and a shutter moving plate, having a plurality of second openings corresponding to the first openings, movably disposed between the grating and the fixed plate. An opening-ratio controller moves the moving plate with respect to the fixed plate whereby an opening ratio defined by relative positions of the first openings and the second openings is controlled. The separation between the grating and the shutter fixed plate may be the thickness of the shutter moving plate. The opening-ratio controller may include an opening-ratio controlling screw having a pinion attached to the screw end.
摘要翻译：用于控制空气流的装置包括具有多个通风口的光栅，由快门固定板组成的快门组件，其具有附接到光栅的下表面的多个第一开口，以及快门移动板，具有对应于第一开口的多个第二开口，可移动地设置在光栅和固定板之间。打开比控制器相对于固定板移动移动板，由此控制由第一开口和第二开口的相对位置限定的开口率。光栅和快门固定板之间的间隔可以是快门移动板的厚度。打开比控制器可以包括开口比控制螺钉，其具有附接到螺钉端的小齿轮。

37. 发明申请

US20130333757A1 Preparation Method of Low Temperature Sintering Active Electrode Paste for Dye Sensitized Solar Cell 有权
标题翻译：用于染料敏化太阳能电池的低温烧结活性电极浆料的制备方法
公开(公告)号：US20130333757A1
公开(公告)日：2013-12-19
申请号：US13788912
申请日：2013-03-07
申请人： Tae Jin Hwang , Ho Hyeong Kim , Jae Young Park
发明人： Tae Jin Hwang , Ho Hyeong Kim , Jae Young Park
IPC分类号： H01G9/20
CPC分类号： H01G9/2031 , B82Y30/00 , C09C1/0084 , H01G9/2059 , Y02E10/542
摘要： The present invention relates to a method for preparing titanium dioxide paste for dye sensitized solar cell, and more specifically a method for preparing titanium dioxide paste fir dye sensitized solar cell, which is curable at a low temperature and is able to form a uniform coating layer and exhibits relatively high energy conversion efficiency. The present invention also relates to a method for preparing low temperature curable paste which requires no separate dye adsorption process or can improve energy conversion efficiency by adding dye or metal precursor in advance.
摘要翻译：本发明涉及一种制备用于染料敏化太阳能电池的二氧化钛糊料的方法，更具体地说，一种制备二氧化钛糊冷杉染料敏化太阳能电池的方法，其可在低温下固化并且能够形成均匀的涂层并表现出较高的能量转换效率。本发明还涉及一种制备低温可固化糊剂的方法，其不需要单独的染料吸附方法，或者可以通过预先加入染料或金属前体来提高能量转换效率。

38. 发明授权

US08339159B2 Input buffer circuit of semiconductor apparatus 有权
标题翻译：半导体装置的输入缓冲电路
公开(公告)号：US08339159B2
公开(公告)日：2012-12-25
申请号：US12540496
申请日：2009-08-13
申请人： Ji-Wang Lee , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
发明人： Ji-Wang Lee , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
IPC分类号： H03K5/153
CPC分类号： H03K5/153
摘要： The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.
摘要翻译：半导体装置的输入缓冲电路包括第一缓冲单元，其由第一电压端子和第二电压端子之间的电压电平差激活，并且通过比较第一电压电平和第二电压电平的电压电平来生成第一比较信号和第二比较信号参考电压和输入信号; 控制单元，其通过比较所述参考电压和所述第二比较信号的电压电平来控制在所述第二电压端子和接地端子之间流动的电流量; 以及第二缓冲单元，其通过比较输入信号和第一比较信号的电压电平来产生输出信号。

39. 发明授权

US08026701B2 Voltage regulator for a synchronous clock system to reduce clock tree jitter 失效
标题翻译：用于同步时钟系统的电压调节器，以减少时钟树抖动
公开(公告)号：US08026701B2
公开(公告)日：2011-09-27
申请号：US12265908
申请日：2008-11-06
申请人： Hyung-Soo Kim , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Hyung-Soo Kim , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： G05F1/652
CPC分类号： G11C5/147
摘要： A voltage regulator with an adaptive bandwidth, including a first buffer chain, a voltage generating unit, a trimming capacitor unit, a second buffer chain, and a control unit. The first buffer chain delays a clock signal using an external voltage as a supply voltage. The voltage generating unit generates a regulated voltage on the basis a reference voltage. The trimming capacitor unit controls a load capacitance of the voltage generating unit. The second buffer chain delays the clock signal using the regulated voltage as a supply voltage. The control unit adjusts the load capacitance by detecting a delay difference of clocks output from the first and second buffer chains.
摘要翻译：具有自适应带宽的电压调节器，包括第一缓冲链，电压产生单元，微调电容器单元，第二缓冲链和控制单元。第一个缓冲链使用外部电压作为电源电压来延迟时钟信号。电压产生单元基于参考电压产生调节电压。微调电容器单元控制电压产生单元的负载电容。第二缓冲链使用调节电压作为电源电压来延迟时钟信号。控制单元通过检测从第一和第二缓冲器链输出的时钟的延迟差来调节负载电容。

40. 发明授权

US07884659B2 Phase mixer and delay locked loop including the same 有权
标题翻译：相位混合器和延迟锁定环包括相同
公开(公告)号：US07884659B2
公开(公告)日：2011-02-08
申请号：US12347298
申请日：2008-12-31
申请人： Jae-Min Jang , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Chang-Kun Park
发明人： Jae-Min Jang , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Chang-Kun Park
IPC分类号： H03K11/16
CPC分类号： H03L7/0814 , H03K5/13 , H03K2005/00052 , H03K2005/00065 , H03L7/0818
摘要： A phase mixer includes a phase mixing unit configured to mix a phase of a first input signal and a phase of a second input signal in response to a phase control signal and output a phase mixed signal whose phase is varied by one or more units of a unit phase value, and a phase value adjusting unit configured to control an operation of the phrase mixing unit so that the unit phase value is adjusted in response to a code signal coding at least one of a process, voltage, or temperature (PVT) variation.
摘要翻译：相位混合器包括：相位混合单元，被配置为响应于相位控制信号混合第一输入信号的相位和第二输入信号的相位，并输出相位混合信号，该相位混合信号的相位由一个或多个单位单位相位值，以及相位值调整单元，被配置为控制短语混合单元的操作，使得响应于代码信号来编码单位相位值，编码信号编码处理，电压或温度（PVT）变化中的至少一个。

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