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31. 发明授权

US08053758B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08053758B2
公开(公告)日：2011-11-08
申请号：US12549140
申请日：2009-08-27
申请人： Takashi Yamauchi , Yoshifumi Nishi , Hiroto Honda , Kei Masunishi , Shinji Murai , Masumi Saitoh
发明人： Takashi Yamauchi , Yoshifumi Nishi , Hiroto Honda , Kei Masunishi , Shinji Murai , Masumi Saitoh
IPC分类号： H01L29/08 , H01L29/15 , H01L31/0352 , H01L31/0256 , H01L31/0232
CPC分类号： H01L27/14645 , H01L27/14683 , H01L31/0352
摘要： A semiconductor device for correcting an input signal and outputting a corrected signal are provided. The semiconductor device includes a semiconductor layer, a plurality of first conductors formed on one of faces of the semiconductor layer and serving as input terminals to which a signal is input, second conductors of the number larger than that of the first conductors at density higher than that of the first conductors, formed on the other face of the semiconductor layer, a high impurity concentration region provided on the semiconductor layer side of an interface between the second conductor and the semiconductor layer, an insulating layer formed on the other face, and a plurality of third conductors formed on the insulating layer and serving as output terminals for outputting the processed signal.
摘要翻译：提供了用于校正输入信号并输出校正信号的半导体器件。半导体器件包括半导体层，形成在半导体层的一个表面上并用作输入信号的输入端的多个第一导体，第二导体的数量大于第一导体的密度高于在半导体层的另一面形成的第一导体的第一导体的高杂质浓度区域设置在第二导体和半导体层之间的界面的半导体层侧，形成在另一面上的绝缘层，多个第三导体，形成在绝缘层上并用作用于输出处理信号的输出端。

32. 发明授权

US07893483B2 Neuron device 失效
标题翻译：神经元装置
公开(公告)号：US07893483B2
公开(公告)日：2011-02-22
申请号：US12043193
申请日：2008-03-06
申请人： Atsuhiro Kinoshita , Yoshifumi Nishi
发明人： Atsuhiro Kinoshita , Yoshifumi Nishi
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/66825 , H01L29/785
摘要： A neuron device includes: a semiconductor layer; source and drain regions formed in the semiconductor layer at a distance from each other; a protection film formed on an upper face of the semiconductor layer; a channel region formed in the semiconductor layer between the source region and the drain region; a pair of gate insulating films formed on two side faces of the channel region; a floating gate electrode including: a first portion covered on the gate insulating films and the protection film; a second portion connected to the first portion; and a third portion provided on the substrate so as to connect to the end portion of the second portion on the opposite side from the first portion; an interelectrode insulating film provided on the first to third portions; and a plurality of control gate electrodes provided on the third portion.
摘要翻译：神经元装置包括：半导体层; 源极和漏极区域形成在半导体层中彼此间隔一定距离; 形成在所述半导体层的上表面上的保护膜; 在所述源极区域和所述漏极区域之间的所述半导体层中形成的沟道区域; 形成在沟道区域的两个侧面上的一对栅极绝缘膜; 一种浮栅电极，包括：覆盖在栅极绝缘膜和保护膜上的第一部分; 连接到第一部分的第二部分; 以及第三部分，设置在所述基板上，以便在与所述第一部分相反的一侧连接到所述第二部分的端部; 设置在所述第一至第三部分上的电极间绝缘膜; 以及设置在第三部分上的多个控制栅电极。

33. 发明申请

US20090250742A1 NEURON DEVICE 失效
标题翻译：神经元设备
公开(公告)号：US20090250742A1
公开(公告)日：2009-10-08
申请号：US12043193
申请日：2008-03-06
申请人： Atsuhiro KINOSHITA , Yoshifumi Nishi
发明人： Atsuhiro KINOSHITA , Yoshifumi Nishi
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/66825 , H01L29/785
摘要： A neuron device includes: a semiconductor layer; source and drain regions formed in the semiconductor layer at a distance from each other; a protection film formed on an upper face of the semiconductor layer; a channel region formed in the semiconductor layer between the source region and the drain region; a pair of gate insulating films formed on two side faces of the channel region; a floating gate electrode including: a first portion covered on the gate insulating films and the protection film; a second portion connected to the first portion; and a third portion provided on the substrate so as to connect to the end portion of the second portion on the opposite side from the first portion; an interelectrode insulating film provided on the first to third portions; and a plurality of control gate electrodes provided on the third portion.
摘要翻译：神经元装置包括：半导体层; 源极和漏极区域形成在半导体层中彼此间隔一定距离; 形成在所述半导体层的上表面上的保护膜; 在所述源极区域和所述漏极区域之间的所述半导体层中形成的沟道区域; 形成在沟道区域的两个侧面上的一对栅极绝缘膜; 一种浮栅电极，包括：覆盖在栅极绝缘膜和保护膜上的第一部分; 连接到第一部分的第二部分; 以及第三部分，设置在所述基板上，以便在与所述第一部分相反的一侧连接到所述第二部分的端部; 设置在所述第一至第三部分上的电极间绝缘膜; 以及设置在第三部分上的多个控制栅电极。

34. 发明申请

US20090008726A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：US20090008726A1
公开(公告)日：2009-01-08
申请号：US12051947
申请日：2008-03-20
申请人： Takashi Yamauchi , Yoshifumi Nishi , Atsuhiro Kinoshita , Yoshinori Tsuchiya , Junji Koga , Koichi Kato
发明人： Takashi Yamauchi , Yoshifumi Nishi , Atsuhiro Kinoshita , Yoshinori Tsuchiya , Junji Koga , Koichi Kato
IPC分类号： H01L47/00 , H01L21/425
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823821 , H01L21/823835 , H01L21/823842 , H01L29/785
摘要： A method of manufacturing a semiconductor device reducing interface resistance of n-type and p-type MISFETs are provided. According to the method, a gate dielectric film and a gate electrode of the n-type MISFET are formed on a first semiconductor region, a gate dielectric film and a gate electrode of the p-type MISFET are formed on a second semiconductor region, an n-type diffusion layer is formed by ion implantation of As into the first semiconductor region, a first silicide layer is formed by first heat treatment after a first metal containing Ni is deposited on the n-type diffusion layer, the first silicide layer is made thicker by second heat treatment after a second metal containing Ni is deposited on the first silicide layer and second semiconductor region, and third heat treatment is provided after formation of a second silicide layer and ion implantation of B or Mg into the second silicide layer.
摘要翻译：提供了制造半导体器件降低n型和p型MISFET的界面电阻的方法。根据该方法，在第一半导体区域上形成栅极电介质膜和n型MISFET的栅电极，在第二半导体区域上形成p型MISFET的栅极电介质膜和栅电极，通过将As离子注入第一半导体区域形成n型扩散层，在n型扩散层上沉积含有Ni的第一金属之后，通过第一热处理形成第一硅化物层，制作第一硅化物层在第一硅化物层和第二半导体区域上沉积含有Ni的第二金属沉积第二热处理之后，在形成第二硅化物层和在第二硅化物层中离子注入B或Mg之后提供第三热处理。

35. 发明申请

US20060124080A1 Pilot oil ignition gas engine and method of operating pilot oil ignition gas engine 有权
公开(公告)号：US20060124080A1
公开(公告)日：2006-06-15
申请号：US11348189
申请日：2006-02-06
申请人： Satoru Goto , Yoshifumi Nishi
发明人： Satoru Goto , Yoshifumi Nishi
IPC分类号： F02B3/06
CPC分类号： F02M43/00 , F02D19/061 , F02D19/10 , F02D41/0027 , F02D41/042 , Y02T10/36
摘要： The gas engine of the present invention has a pilot oil fuel valve, a pilot oil pump, and first and second pipes connected to a pilot oil main pipe, for each of a plurality of combustion chambers. An operating pilot oil tank and an ignition stimulant-added pilot oil tank are connected via a switching valve to a third pipe, connected to an end of the pilot oil main pipe. Before operating stops, the pilot oil is discharged by opening an exhaust valve, and thereafter, the switching valve is switched and pilot oil which the ignition stimulant has been added to is supplied into the pipe. Consequently, the pilot oil downstream from the main pipe is replaced with the pilot oil which the ignition stimulant has been added to. Therefore, at the time of the next activation, pilot oil which the ignition stimulant has been added to is sprayed from the fuel valve, and, as a result, misfire at the time of activation is reduced, and a highly reliable engine is obtained.

36. 发明授权

US06209511B1 Lean combustion gas engine 有权
标题翻译：精益燃气发动机
公开(公告)号：US06209511B1
公开(公告)日：2001-04-03
申请号：US09307899
申请日：1999-05-10
申请人： Satoru Goto , Yoshifumi Nishi , Sadao Nakayama , Takeyuki Sakagami
发明人： Satoru Goto , Yoshifumi Nishi , Sadao Nakayama , Takeyuki Sakagami
IPC分类号： F02B1910
CPC分类号： F02B19/108 , F02B19/1095 , F02B19/12 , F02D19/0684 , F02D19/0692 , F02D19/105 , F02D37/02 , F02D41/0025 , F02D41/3047 , F02D41/3094 , F02D41/401 , F02D2041/389 , Y02T10/125 , Y02T10/36 , Y02T10/44
摘要： The present invention relates to a lean combustion gas engine which receives a drive output by means of supplying and combusting gas fuel in a main combustion chamber. The lean combustion engine of the present invention comprises: a main combustion chamber (1) which is surrounded by a piston (3), a cylinder (2) and a cylinder head (4); a precombustion chamber (30) equipped with a pilot fuel injection valve; and a spark plug (11) which serves as an ignition source for the fuel-air mixture within the main combustion chamber; wherein, the spark plug and pilot fuel injection valve-equipped precombustion chamber are provided in said cylinder head.
摘要翻译：本发明涉及一种通过在主燃烧室中供应和燃烧气体燃料来接收驱动输出的稀燃燃气发动机。本发明的稀燃内燃机包括：由活塞（3），气缸（2）和气缸盖（4）围绕的主燃烧室（1）; 配备有先导燃料喷射阀的预燃室（30）; 以及作为燃料 - 空气混合物在主燃烧室内的点火源的火花塞（11）; 其特征在于，在所述气缸盖中设置有配备有火花塞和先导燃料喷射阀的预燃室。

37. 发明授权

US09246709B2 Storage device in which forwarding-function-equipped memory nodes are mutually connected and data processing method 有权
标题翻译：具有转发功能的存储器节点相互连接的存储设备和数据处理方法
公开(公告)号：US09246709B2
公开(公告)日：2016-01-26
申请号：US13293399
申请日：2011-11-10
申请人： Kosuke Tatsumura , Atsuhiro Kinoshita , Hirotaka Nishino , Masamichi Suzuki , Yoshifumi Nishi , Takao Marukame , Takahiro Kurita
发明人： Kosuke Tatsumura , Atsuhiro Kinoshita , Hirotaka Nishino , Masamichi Suzuki , Yoshifumi Nishi , Takao Marukame , Takahiro Kurita
IPC分类号： G06F12/02 , H04L12/64 , G06F3/06
CPC分类号： H04L49/253 , G06F3/0605 , G06F3/0635 , G06F3/0656 , G06F3/0658 , G06F3/0683 , H04L12/6418 , H04L45/74
摘要： According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.
摘要翻译：根据一个实施例，存储设备包括多个存储器节点。每个存储器节点包括多个输入端口，多个输出端口，选择器，分组控制器和存储器。选择器将输入到输入端口的数据包输出输出到其中一个输出端口。分组控制器控制选择器。内存存储数据。存储器节点在输入端口和输出端口相互连接。存储器节点具有由其物理位置确定的地址。当接收到没有寻址到具有分组控制器的存储器节点的分组时，分组控制器基于包括分组的目的地地址的信息和具有分组控制器的存储器节点的地址来切换输出分组的输出端口。

38. 发明授权

US09112132B2 Resistance-variable memory device 有权
标题翻译：电阻变量存储器件
公开(公告)号：US09112132B2
公开(公告)日：2015-08-18
申请号：US13605746
申请日：2012-09-06
申请人： Takayuki Ishikawa , Yoshifumi Nishi , Dalsuke Matsushita , Masato Koyama
发明人： Takayuki Ishikawa , Yoshifumi Nishi , Dalsuke Matsushita , Masato Koyama
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： H01L45/04 , H01L45/1233 , H01L45/145
摘要： A memory device includes a first electrode, a second electrode, a third electrode, a first variable resistance layer between the first electrode and the third electrode, and a second variable resistance layer between the second electrode and the third electrode. The first, second, and third electrodes, and the first and second variable resistance layers are formed of materials that cause the first variable resistance layer to transition from a high resistance state to a low resistance state when a voltage is applied across the first and second electrodes and maintain the high resistance state when the voltage is cut off, and cause the second variable resistance layer to transition from a high resistance state to a low resistance state when the voltage is applied across the first and second electrodes and transition from the high resistance state to the low resistance state when the voltage is cut off.
摘要翻译：存储器件包括第一电极，第二电极，第三电极，第一电极和第三电极之间的第一可变电阻层，以及在第二电极和第三电极之间的第二可变电阻层。第一，第二和第三电极以及第一和第二可变电阻层由当第一和第二电极层施加电压时使第一可变电阻层从高电阻状态转变为低电阻状态的材料形成电极，当电压被切断时保持高电阻状态，并且当电压施加在第一和第二电极两端并从高电阻转变时，使第二可变电阻层从高电阻状态转变到低电阻状态当电压被切断时，状态为低电阻状态。

39. 发明授权

US08664632B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US08664632B2
公开(公告)日：2014-03-04
申请号：US13599504
申请日：2012-08-30
申请人： Daisuke Matsushita , Shosuke Fujii , Yoshifumi Nishi , Akira Takashima , Takayuki Ishikawa , Hidenori Miyagawa , Takashi Haimoto , Yusuke Arayashiki , Hideki Inokuma
发明人： Daisuke Matsushita , Shosuke Fujii , Yoshifumi Nishi , Akira Takashima , Takayuki Ishikawa , Hidenori Miyagawa , Takashi Haimoto , Yusuke Arayashiki , Hideki Inokuma
IPC分类号： H01L47/00 , G11C11/00
CPC分类号： H01L45/1253 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/148
摘要： According to one embodiment, a memory device includes a first electrode, a second electrode, and a variable resistance film. The variable resistance film is connected between the first electrode and the second electrode. The first electrode includes a metal contained in a matrix made of a conductive material. A cohesive energy of the metal is lower than a cohesive energy of the conductive material. A concentration of the metal at a central portion of the first electrode in a width direction thereof is higher than concentrations of the metal in two end portions of the first electrode in the width direction.
摘要翻译：根据一个实施例，存储器件包括第一电极，第二电极和可变电阻膜。可变电阻膜连接在第一电极和第二电极之间。第一电极包括由导电材料制成的基体中所含的金属。金属的内聚能低于导电材料的内聚能。第一电极的宽度方向的中央部的金属浓度高于第一电极的宽度方向的两端部的金属的浓度。

40. 发明申请

US20130307054A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20130307054A1
公开(公告)日：2013-11-21
申请号：US13606292
申请日：2012-09-07
申请人： Shinichi YASUDA , Kosuke Tatsumura , Mari Matsumoto , Koichiro Zaitsu , Masato Oda , Atsuhiro Kinoshita , Daisuke Hagishima , Yoshifumi Nishi , Takahiro Kurita , Shinobu Fujita
发明人： Shinichi YASUDA , Kosuke Tatsumura , Mari Matsumoto , Koichiro Zaitsu , Masato Oda , Atsuhiro Kinoshita , Daisuke Hagishima , Yoshifumi Nishi , Takahiro Kurita , Shinobu Fujita
IPC分类号： H01L27/105
CPC分类号： G11C16/10 , H01L21/823456 , H01L21/823462 , H01L27/11526 , H01L27/11573 , H01L29/7881 , H01L29/792
摘要： One embodiment provides a semiconductor integrated circuit, including: a substrate; a plurality of nonvolatile memory portions formed in the substrate, each including a first nonvolatile memory and a second nonvolatile memory; and a plurality of logic transistor portions formed in the substrate, each including at least one of logic transistor, wherein the logic transistors include: a first transistor which is directly connected to drains of the first and second nonvolatile memories at its gate; and a second transistor which is not directly connected to the drains of the first and second nonvolatile memories, and wherein a bottom surface of the gate of each of the logic transistors sandwiching the first and second nonvolatile memories is lower in height from a top surface of the substrate than a bottom surface of the control gate of each of the first and second nonvolatile memories.
摘要翻译：一个实施例提供一种半导体集成电路，包括：基板; 形成在所述基板中的多个非易失性存储部，每个包括第一非易失性存储器和第二非易失性存储器; 以及形成在所述衬底中的多个逻辑晶体管部分，每个逻辑晶体管部分包括逻辑晶体管中的至少一个，其中所述逻辑晶体管包括：第一晶体管，其第一和第二非易失性存储器的栅极直接连接到第一晶体管; 以及第二晶体管，其不直接连接到第一和第二非易失性存储器的漏极，并且其中夹着第一和第二非易失性存储器的每个逻辑晶体管的栅极的底表面的高度与所述基板比所述第一和第二非易失性存储器中的每一个的所述控制栅极的底表面。

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