专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08658999B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08658999B2
公开(公告)日：2014-02-25
申请号：US13728552
申请日：2012-12-27
申请人： Yoshifumi Nishi , Takao Marukame , Takayuki Ishikawa , Masato Koyama
发明人： Yoshifumi Nishi , Takao Marukame , Takayuki Ishikawa , Masato Koyama
IPC分类号： H01L29/02
CPC分类号： H01L45/14 , H01L27/2472 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/16
摘要： According to an embodiment, a semiconductor device includes first and second memristors. The first memristor includes a first electrode made of a first material, a second electrode made of a second material, and a first resistive switching film arranged between the first and second electrodes. The first resistive switching film is connected to both the first and second electrodes. The second memristor includes a third electrode made of a third material, a fourth electrode made of the second material, and a second resistive switching film arranged between the third and fourth electrodes. The second resistive switching film is connected to both the third and fourth electrodes. The work function of the first material is smaller than that of the second material. The work function of the third material is larger than that of the second material.
摘要翻译：根据实施例，半导体器件包括第一和第二忆阻器。第一忆阻器包括由第一材料制成的第一电极，由第二材料制成的第二电极和布置在第一和第二电极之间的第一电阻切换膜。第一电阻开关膜连接到第一和第二电极。第二忆阻器包括由第三材料制成的第三电极，由第二材料制成的第四电极和布置在第三和第四电极之间的第二电阻切换膜。第二电阻开关膜连接到第三和第四电极。第一材料的功函数小于第二材料的功函数。第三种材料的功函数大于第二种材料的功函数。

2. 发明授权

US08592924B2 Semiconductor device including gate electrode having a laminate structure and a plug electrically connected thereto 有权
标题翻译：半导体装置包括具有层叠结构的栅电极和与其电连接的插头
公开(公告)号：US08592924B2
公开(公告)日：2013-11-26
申请号：US13470372
申请日：2012-05-14
申请人： Yoshinori Tsuchiya , Masato Koyama
发明人： Yoshinori Tsuchiya , Masato Koyama
IPC分类号： H01L29/49
CPC分类号： H01L29/4958 , H01L21/2807 , H01L21/28079 , H01L21/28088 , H01L21/76802 , H01L21/76877 , H01L21/823807 , H01L21/823828 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L29/4966 , H01L29/4975 , H01L29/665
摘要： A semiconductor device includes a semiconductor substrate having a semiconductor layer, a gate electrode, a source region, a drain region, an element separation insulating film layer and a wiring. The gate electrode include a laminated structure having a gate insulating film formed on the semiconductor layer, a metal or a metallic compound formed on the gate insulating film and a polycrystalline silicon layer formed on the metal or metallic compound. The source region and drain region are formed on a surface portion of the semiconductor substrate and sandwich the gate electrode therebetween. The element separation insulating film layer surrounds the semiconductor layer. The wiring is in contact with the metal or metallic compound of the gate electrode.
摘要翻译：半导体器件包括具有半导体层，栅电极，源极区，漏极区，元件隔离绝缘膜层和布线的半导体衬底。栅极包括在半导体层上形成有栅极绝缘膜的层压结构，形成在栅极绝缘膜上的金属或金属化合物以及形成在金属或金属化合物上的多晶硅层。源极区域和漏极区域形成在半导体衬底的表面部分上，并将栅电极夹在其间。元件分离绝缘膜层围绕半导体层。布线与栅电极的金属或金属化合物接触。

3. 发明授权

US08203189B2 Semiconductor device including gate electrode having a laminate structure and plug electrically connected thereto 有权
标题翻译：半导体器件包括具有层叠结构的栅电极和与其电连接的插头
公开(公告)号：US08203189B2
公开(公告)日：2012-06-19
申请号：US12549298
申请日：2009-08-27
申请人： Yoshinori Tsuchiya , Masato Koyama
发明人： Yoshinori Tsuchiya , Masato Koyama
IPC分类号： H01L29/49
CPC分类号： H01L29/4958 , H01L21/2807 , H01L21/28079 , H01L21/28088 , H01L21/76802 , H01L21/76877 , H01L21/823807 , H01L21/823828 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L29/4966 , H01L29/4975 , H01L29/665
摘要： A semiconductor device includes a semiconductor substrate having a semiconductor layer, a gate electrode, a source region, a drain region, an element separation insulating film layer and a wiring. The gate electrode include a laminated structure having a gate insulating film formed on the semiconductor layer, a metal or a metallic compound formed on the gate insulating film and a polycrystalline silicon layer formed on the metal or metallic compound. The source region and drain region are formed on a surface portion of the semiconductor substrate and sandwich the gate electrode therebetween. The element separation insulating film layer surrounds the semiconductor layer. The wiring is in contact with the metal or metallic compound of the gate electrode.
摘要翻译：半导体器件包括具有半导体层，栅电极，源极区，漏极区，元件隔离绝缘膜层和布线的半导体衬底。栅极包括在半导体层上形成有栅极绝缘膜的层压结构，形成在栅极绝缘膜上的金属或金属化合物以及形成在金属或金属化合物上的多晶硅层。源极区域和漏极区域形成在半导体衬底的表面部分上，并将栅电极夹在其间。元件分离绝缘膜层围绕半导体层。布线与栅电极的金属或金属化合物接触。

4. 发明申请

US20110275184A1 Semiconductor Device 有权
标题翻译：半导体器件
公开(公告)号：US20110275184A1
公开(公告)日：2011-11-10
申请号：US13184116
申请日：2011-07-15
申请人： Reika ICHIHARA , Yoshinori TSUCHIYA , Masato KOYAMA , Akira NISHIYAMA
发明人： Reika ICHIHARA , Yoshinori TSUCHIYA , Masato KOYAMA , Akira NISHIYAMA
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823462
摘要： A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.
摘要翻译：半导体器件包括半导体衬底，形成在衬底上的nMISFET，nMISFET包括形成在衬底上的第一电介质和形成在第一电介质上的第一金属栅极，并由选自Ti，Zr，Hf， Ta，Sc，Y，镧系元素和锕系和选自所述一种金属元素的硼化物，硅化物和锗化合物的一种，以及形成在所述衬底上的pMISFET，所述pMISFET包括形成在所述衬底上的第二电介质和第二金属栅电极形成在第二电介质上并由与第一金属栅电极相同的材料制成，第二电介质面向第二金属栅电极的至少一部分由绝缘材料制成，绝缘材料与至少一部分的第一电介质面向第一金属栅电极。

5. 发明申请

US20110266632A1 Semiconductor Device 有权
公开(公告)号：US20110266632A1
公开(公告)日：2011-11-03
申请号：US13184159
申请日：2011-07-15
申请人： Reika ICHIHARA , Yoshinori Tsuchiya , Masato Koyama , Akira Nishiyama
发明人： Reika ICHIHARA , Yoshinori Tsuchiya , Masato Koyama , Akira Nishiyama
IPC分类号： H01L27/092
CPC分类号： H01L21/823857 , H01L21/823462
摘要： A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.

6. 发明申请

US20110227164A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110227164A1
公开(公告)日：2011-09-22
申请号：US13098811
申请日：2011-05-02
申请人： Tatsuo SHIMIZU , Masato Koyama
发明人： Tatsuo SHIMIZU , Masato Koyama
IPC分类号： H01L27/092
CPC分类号： H01L21/823857 , H01L21/823821 , H01L21/823842 , H01L27/1203 , H01L29/785
摘要： According to one embodiment, it is possible to provide a semiconductor device provided with an MIS transistor which has an effective work function being, as much as possible, suitable for low threshold operation. A CMIS device provided with an electrode having an optimal effective work function and enabling low threshold operation to achieve by producing an in-gap level by the addition of a high valence metal in an Hf (or Zr) oxide and changing a position of the in-gap level by nitrogen or fluorine or the like has been realized.
摘要翻译：根据一个实施例，可以提供一种设置有MIS晶体管的半导体器件，该半导体器件具有尽可能多的适合于低阈值操作的有效功函数。具有电极的CMIS器件具有最佳的有效功函数，并且能够通过在Hf（或Zr）氧化物中添加高价金属而产生空隙间电平来实现低阈值操作，从而改变位于通过氮或氟等的差异水平已经实现。

7. 发明授权

US07968956B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07968956B2
公开(公告)日：2011-06-28
申请号：US12388965
申请日：2009-02-19
申请人： Kosuke Tatsumura , Masakazu Goto , Reika Ichihara , Masato Koyama , Shigeru Kawanaka , Kazuaki Nakajima
发明人： Kosuke Tatsumura , Masakazu Goto , Reika Ichihara , Masato Koyama , Shigeru Kawanaka , Kazuaki Nakajima
IPC分类号： H01L29/78 , H01L21/70
CPC分类号： H01L21/823828 , H01L21/823842 , H01L29/785
摘要： A semiconductor device includes a semiconductor substrate, a p-channel MIS transistor formed on the substrate, the p-channel transistor having a first gate dielectric formed on the substrate and a first gate electrode layer formed on the first dielectric, and an n-channel MIS transistor formed on the substrate, the n-channel transistor having a second gate dielectric formed on the substrate and a second gate electrode layer formed on the second dielectric. A bottom layer of the first gate electrode layer in contact with the first gate dielectric and a bottom layer of the second gate electrode layer in contact with the second gate dielectric have the same orientation and the same composition including Ta and C, and a mole ratio of Ta to a total of C and Ta, (Ta/(Ta+C)), is larger than 0.5.
摘要翻译：半导体器件包括半导体衬底，形成在衬底上的p沟道MIS晶体管，形成在衬底上的第一栅极电介质的p沟道晶体管和形成在第一电介质上的第一栅极电极层，以及n沟道形成在衬底上的MIS晶体管，所述n沟道晶体管具有形成在衬底上的第二栅极电介质和形成在第二电介质上的第二栅极电极层。与第一栅极电介质接触的第一栅极电极层的底层和与第二栅极电介质接触的第二栅电极层的底层具有相同的取向和相同的组成，包括Ta和C，以及摩尔比的Ta与总计C和Ta（Ta /（Ta + C））大于0.5。

8. 发明授权

US07964489B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07964489B2
公开(公告)日：2011-06-21
申请号：US12491984
申请日：2009-06-25
申请人： Masato Koyama , Yoshinori Tsuchiya , Yuuichi Kamimuta , Reika Ichihara , Katsuyuki Sekine
发明人： Masato Koyama , Yoshinori Tsuchiya , Yuuichi Kamimuta , Reika Ichihara , Katsuyuki Sekine
IPC分类号： H01L21/3205
CPC分类号： H01L27/092 , H01L21/28097 , H01L21/823842 , H01L21/823857 , H01L29/4975 , H01L29/513 , H01L29/517 , H01L29/7833
摘要： A semiconductor device includes: a p-channel MIS transistor including: a first insulating layer formed on a semiconductor region between a source region and a drain region, and containing at least silicon and oxygen; a second insulating layer formed on the first insulating layer, and containing hafnium, silicon, oxygen, and nitrogen, and a first gate electrode formed on the second insulating layer. The first and second insulating layers have a first and second region respectively. The first and second regions are in a 0.3 nm range in the film thickness direction from an interface between the first insulating layer and the second insulating layer. Each of the first and second regions include aluminum atoms with a concentration of 1×1020 cm−3 or more to 1×1022 cm−3 or less.
摘要翻译：半导体器件包括：p沟道MIS晶体管，包括：第一绝缘层，形成在源极区域和漏极区域之间的半导体区域上，并且至少包含硅和氧; 形成在所述第一绝缘层上并且包含铪，硅，氧和氮的第二绝缘层，以及形成在所述第二绝缘层上的第一栅电极。第一和第二绝缘层分别具有第一和第二区域。第一和第二区域在从第一绝缘层和第二绝缘层之间的界面的膜厚度方向上为0.3nm的范围内。第一和第二区域中的每一个包括浓度为1×1020cm-3或更高至1×1022cm-3或更低的铝原子。

9. 发明授权

US07825458B2 Nonvolatile semiconductor memory and manufacturing method thereof 有权
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US07825458B2
公开(公告)日：2010-11-02
申请号：US12050427
申请日：2008-03-18
申请人： Tatsuo Shimizu , Koichi Muraoka , Masato Koyama , Shoko Kikuchi
发明人： Tatsuo Shimizu , Koichi Muraoka , Masato Koyama , Shoko Kikuchi
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/4234 , H01L29/513 , H01L29/66833 , H01L29/785
摘要： A nonvolatile semiconductor memory includes a source area and a drain area provided on a semiconductor substrate with a gap which serves as a channel area, a first insulating layer, a charge accumulating layer, a second insulating layer (block layer) and a control electrode, formed successively on the channel area, and the second insulating layer is formed by adding an appropriate amount of high valence substance into base material composed of substance having a sufficiently higher dielectric constant than the first insulating layer so as to accumulate a large amount of negative charges in the block layer by localized state capable of trapping electrons, so that the high dielectric constant of the block layer and the high electronic barrier are achieved at the same time.
摘要翻译：非易失性半导体存储器包括设置在具有用作沟道区的间隙的半导体衬底上的源区和漏区，第一绝缘层，电荷累积层，第二绝缘层（阻挡层）和控制电极，在通道区域上依次形成，并且通过向具有比第一绝缘层高的介电常数的物质构成的基材中添加适量的高价态物质形成第二绝缘层，以便积累大量的负电荷在阻挡层中通过能够捕获电子的局部状态，从而同时实现阻挡层和高电子势垒的高介电常数。

10. 发明授权

US07807990B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07807990B2
公开(公告)日：2010-10-05
申请号：US11753186
申请日：2007-05-24
申请人： Masato Koyama , Yoshinori Tsuchiya , Yuuichi Kamimuta , Reika Ichihara , Katsuyuki Sekine
发明人： Masato Koyama , Yoshinori Tsuchiya , Yuuichi Kamimuta , Reika Ichihara , Katsuyuki Sekine
IPC分类号： H01L31/00
CPC分类号： H01L27/092 , H01L21/28097 , H01L21/823842 , H01L21/823857 , H01L29/4975 , H01L29/513 , H01L29/517 , H01L29/7833
摘要： A semiconductor device includes: a p-channel MIS transistor including: a first insulating layer formed on a semiconductor region between a source region and a drain region, and containing at least silicon and oxygen; a second insulating layer formed on the first insulating layer, and containing hafnium, silicon, oxygen, and nitrogen, and a first gate electrode formed on the second insulating layer. The first and second insulating layers have a first and second region respectively. The first and second regions are in a 0.3 nm range in the film thickness direction from an interface between the first insulating layer and the second insulating layer. Each of the first and second regions include aluminum atoms with a concentration of 1×1020 cm−3 or more to 1×1022 cm−3 or less.
摘要翻译：半导体器件包括：p沟道MIS晶体管，包括：第一绝缘层，形成在源极区域和漏极区域之间的半导体区域上，并且至少包含硅和氧; 形成在所述第一绝缘层上并且包含铪，硅，氧和氮的第二绝缘层，以及形成在所述第二绝缘层上的第一栅电极。第一和第二绝缘层分别具有第一和第二区域。第一和第二区域在从第一绝缘层和第二绝缘层之间的界面的膜厚度方向上为0.3nm的范围内。第一和第二区域中的每一个包括浓度为1×1020cm-3或更高至1×1022cm-3或更低的铝原子。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式