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31. 外观设计

USD450710S1 Computer generated image for display panel or screen 失效
公开(公告)号：USD450710S1
公开(公告)日：2001-11-20
申请号：US29117162
申请日：2000-01-19
申请人： Keiichi Yoshioka
设计人： Keiichi Yoshioka

32. 发明授权

US06266762B1 Information processing apparatus 失效
标题翻译：信息处理装置
公开(公告)号：US06266762B1
公开(公告)日：2001-07-24
申请号：US09227471
申请日：1999-01-08
申请人： Hideyuki Aota , Keiichi Yoshioka
发明人： Hideyuki Aota , Keiichi Yoshioka
IPC分类号： G06F1340
CPC分类号： G06F9/3012 , G06F9/30101 , G06F9/30141
摘要： A general-use register set includes a plurality of registers in a central processing unit body. A register-bank memory has memory regions relevant to the plurality of registers and is connected to the central processing unit. An output signal of an address circuit included in the central processing unit is supplied to the register-bank memory. Alternatively, an output signal of a decoding circuit included in the central processing unit may be supplied to the register-bank memory. A signal for selecting either activation or deactivation of the register-bank memory is a signal which indicates a selection of the deactivation of the register-bank memory except in a case where data is written in the general-use register set and a case of a restoration operation after register bank switching. Instead, a signal for selecting either generating or non-generating of a clock signal for the register-bank memory may be a signal which indicates a selection of the non-generation of the clock signal for the register-bank memory except in a case where data is written in the general-use register set and in a case of a restoration operation after register bank switching.
摘要翻译：通用寄存器组包括在中央处理单元主体中的多个寄存器。寄存器组存储器具有与多个寄存器相关的存储器区域，并且连接到中央处理单元。包括在中央处理单元中的地址电路的输出信号被提供给寄存器组存储器。或者，包括在中央处理单元中的解码电路的输出信号可以被提供给寄存器组存储器。用于选择寄存器组存储器的激活或去激活的信号是指示除了在通用寄存器组中写入数据的情况下的寄存器组存储器的去激活的选择的信号，以及寄存器组切换后的恢复操作。相反，用于选择产生或不产生用于寄存器组存储器的时钟信号的信号可以是指示对于寄存器组存储器的非时钟信号的选择的信号，除了在数据被写入通用寄存器组中，并且在寄存器组切换之后的恢复操作的情况下。

33. 发明授权

US5696957A Integrated circuit comprising a central processing unit for executing a plurality of programs 失效
标题翻译：集成电路，包括用于执行多个节目的中央处理单元
公开(公告)号：US5696957A
公开(公告)日：1997-12-09
申请号：US593482
申请日：1996-01-29
申请人： Shinichi Yamaura , Kazuhiko Hara , Keiichi Yoshioka , Takashi Yasui
发明人： Shinichi Yamaura , Kazuhiko Hara , Keiichi Yoshioka , Takashi Yasui
IPC分类号： G06F9/30 , G06F9/46
CPC分类号： G06F9/3012 , G06F9/462
摘要： An integrated circuit has a central processing unit for executing programs. The integrated circuit includes a register set, provided in the central processing unit, for storing crate required for executing a program in the central processing unit; and a register-file RAM, coupled to the central processing unit, for storing at least the same data as that stored in the register set in the central processing unit, wherein data stored in the register-file RAM can be supplied to the register set in the central processing unit.
摘要翻译：集成电路具有用于执行程序的中央处理单元。集成电路包括设置在中央处理单元中的寄存器组，用于存储在中央处理单元中执行程序所需的箱; 以及耦合到中央处理单元的寄存器文件RAM，用于存储至少与存储在中央处理单元中的寄存器中的数据相同的数据，其中存储在寄存器文件RAM中的数据可以被提供给寄存器组在中央处理单位。

34. 发明授权

US5630158A Central processing unit including inhibited branch area 失效
标题翻译：中央处理单元包括禁止分支区域
公开(公告)号：US5630158A
公开(公告)日：1997-05-13
申请号：US361936
申请日：1994-12-22
申请人： Kazuhiko Hara , Shinichi Yamaura , Keiichi Yoshioka , Takao Katayama
发明人： Kazuhiko Hara , Shinichi Yamaura , Keiichi Yoshioka , Takao Katayama
IPC分类号： G06F9/26 , G06F9/32 , G06F9/355 , G06F9/38 , G06F9/00
CPC分类号： G06F9/342 , G06F9/321 , G06F9/322 , G06F9/3861
摘要： A central processing unit includes an instruction register storing instruction codes, a timing control unit controlling timings of steps of execution of an instruction, an execution unit executing an operation on data and temporarily storing data, the execution unit having a program counter and a data bus, a decoder decoding instruction codes read from the instruction register and controlling the instruction register, the timing control unit and the execution unit, and a next enable unit receiving an indication signal indicating proceeding to a next instruction should be performed and controlling outputting of the indication signal to the instruction register and the timing control unit based on first and second signals. The first signal is supplied from the decoder and instructing data on the data bus to be input to the program counter. The second signal is supplied from the execution unit and indicating whether a counter value of the program counter is an odd number or an even number.
摘要翻译：中央处理单元包括存储指令代码的指令寄存器，控制指令执行步骤的定时的定时控制单元，执行对数据的操作和暂时存储数据的执行单元，执行单元具有程序计数器和数据总线应执行从指令寄存器读取的解码器解码指令代码和控制指令寄存器，定时控制单元和执行单元，以及接收指示进行下一条指令的指示信号的下一个使能单元，并且控制该指示的输出基于第一和第二信号向指令寄存器和定时控制单元发送信号。第一个信号从解码器提供，并指示数据总线上的数据输入到程序计数器。第二信号从执行单元提供并指示程序计数器的计数器值是奇数还是偶数。

35. 发明授权

US5594890A Emulation system for emulating CPU core, CPU core with provision for emulation and ASIC having the CPU core 失效
标题翻译：用于仿真CPU核心的仿真系统，具有用于仿真的CPU核心和具有CPU核心的ASIC
公开(公告)号：US5594890A
公开(公告)日：1997-01-14
申请号：US200705
申请日：1994-02-23
申请人： Shinichi Yamaura , Keiichi Yoshioka , Kazuhiko Hara , Takao Katayama
发明人： Shinichi Yamaura , Keiichi Yoshioka , Kazuhiko Hara , Takao Katayama
IPC分类号： G06F11/22 , G06F11/36 , G06F17/00
CPC分类号： G06F11/3652
摘要： An IC is provided with a CPU core selected from a plurality of CPU cores, each of which has a specific function. Each CPU core has a system-bus terminal and a common emulator connecting-exclusive terminal. The IC is also provided with a predetermined function device connected to a system bus of the selected CPU core. An emulation bus connects an emulator to the selected CPU core via the common emulator connecting-exclusive terminal. An emulator performs emulation on the selected CPU core which is connected via the emulation bus when the selected CPU core is in a monitor mode. The number of terminal elements and the function associated with each terminal element of the common emulator connecting-exclusive terminal are identical among the common emulator connecting-exclusive terminals.
摘要翻译： IC具有从多个CPU核心中选择的CPU核心，每个CPU核心具有特定功能。每个CPU内核都有一个系统总线端子和一个通用的仿真器连接专用端子。 IC还具有连接到所选CPU核心的系统总线的预定功能装置。仿真总线通过通用仿真器连接专用端子将仿真器连接到选定的CPU内核。仿真器对选定的CPU内核进行仿真，当所选择的CPU内核处于监视模式时，通过仿真总线连接。公共仿真器连接专用端子的终端元件数量和与每个终端元件相关联的功能在通用仿真器连接专用端子中是相同的。

36. 发明授权

US4969980A Process for electroplating stainless steel strips with zinc or zinc-nickel alloy 失效
标题翻译：用锌或锌 - 镍合金电镀不锈钢带的工艺
公开(公告)号：US4969980A
公开(公告)日：1990-11-13
申请号：US189641
申请日：1988-05-03
申请人： Keiichi Yoshioka , Kenji Watanabe , Yasushi Kato
发明人： Keiichi Yoshioka , Kenji Watanabe , Yasushi Kato
IPC分类号： C25D5/02 , C25D5/36
CPC分类号： C25D5/028 , C25D5/36 , Y10T428/12611 , Y10T428/12799
摘要： An exterior stainless steel sheet is provided comprising a stainless steel substrate and a coating layer formed on one surface of the steel substrate from Al, Al alloy, Zn or Zn alloy to a thickness of 0.1 to 70 .mu.m, preferably 1 to 70 .mu.m. A Zn or Zn-Ni alloy plated stainless steel strip is prepared by degreasing a stainless steel strip, substantially activating the surface of the strip, and electroplating the strip by immersing the strip in a hydrochloric acid solution having a concentration of 0.5 to 40 wt % in a zinc or zinc-nickel alloy plating bath at pH 3.5 or lower. Alternatively, activation may be carried out by cathodic electrolytic treatment in a hydrochloric acid solution having a concentration of 0.5 to 40 wt % at a current density of 0.1 to 100 A/dm. During electroplating of one side, the other side of the strip not to be plated is covered with a protective film. A stainless steel sheet comprising a stainless steel substrate and a coating layer formed on one surface of the steel substrate from Zn or Zn alloy to a thickness of 0.1 to 50 .mu.m, preferably 1 to 50 .mu.m is useful in preparing welded pipes.

37. 发明授权

US4885215A Zn-coated stainless steel welded pipe 失效
标题翻译：镀Zn不锈钢焊管
公开(公告)号：US4885215A
公开(公告)日：1989-12-05
申请号：US102024
申请日：1987-09-29
申请人： Keiichi Yoshioka , Kenji Watanabe , Yasushi Kato
发明人： Keiichi Yoshioka , Kenji Watanabe , Yasushi Kato
IPC分类号： C25D5/02 , C25D5/36
CPC分类号： C25D5/028 , C25D5/36 , Y10T428/12611 , Y10T428/12799
摘要： An exterior stainless steel sheet is provided comprising a stainless steel substrate and a coating layer formed on one surface of the steel substrate from Al, Al alloy, Zn or Zn alloy to a thickness of 0.1 to 70 .mu.m, preferably 1 to 70 .mu.m. A Zn or Zn-Ni alloy plated stainless steel strip is prepared by degreasing a stainless steel strip, substantially activating the surface of the strip, and electroplating the strip in a zinc or zinc-nickel alloy plating bath at pH 3.5 or lower. During electroplating of one side, the other side of the strip not to be plated is covered with a protective film. A stainless steel sheet comprising a stainless steel substrate and a coating layer formed on one surface of the steel substrate from Zn or Zn alloy to a thickness of 0.1 to 50 .mu.m, preferably 1 to 50 .mu.m is useful in preparing welded pipes.

38. 发明授权

US08829970B2 Standard cell circuit, semiconductor integrated circuit, and semiconductor integrated circuit device 有权
标题翻译：标准单元电路，半导体集成电路和半导体集成电路器件
公开(公告)号：US08829970B2
公开(公告)日：2014-09-09
申请号：US13556512
申请日：2012-07-24
申请人： Emi Okunishi , Keiichi Yoshioka
发明人： Emi Okunishi , Keiichi Yoshioka
IPC分类号： H03L5/00
CPC分类号： H01L27/0207 , H01L23/5286 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： A standard cell circuit including an input terminal to which input an input signal is input; an output terminal to output an output signal; a first wiring conductor, connected to an external power supply that outputs a first power supply voltage; a second wiring conductor to supply a second power supply voltage that is lower than the first power supply voltage; a standard cell to operate at the second power supply voltage supplied from the second wiring conductor; and a conversion circuit, connected to the first wiring conductor and the second wiring conductor, to convert the first power supply voltage input from the first wiring conductor into the second power supply voltage for output to the second wiring conductor.
摘要翻译：一种标准单元电路，包括：输入端输入输入信号的输入端子; 输出端子，输出输出信号; 连接到输出第一电源电压的外部电源的第一布线导体; 第二布线导体，用于提供低于第一电源电压的第二电源电压; 在从所述第二布线导体提供的所述第二电源电压下工作的标准单元; 以及转换电路，连接到第一布线导体和第二布线导体，以将从第一布线导体输入的第一电源电压转换为第二电源电压，以输出到第二布线导体。

39. 发明申请

US20130027016A1 STANDARD CELL CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：标准单元电路，半导体集成电路和半导体集成电路器件
公开(公告)号：US20130027016A1
公开(公告)日：2013-01-31
申请号：US13556512
申请日：2012-07-24
申请人： Emi OKUNISHI , Keiichi Yoshioka
发明人： Emi OKUNISHI , Keiichi Yoshioka
IPC分类号： G05F3/02
CPC分类号： H01L27/0207 , H01L23/5286 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： A standard cell circuit including an input terminal to which input an input signal is input; an output terminal to output an output signal; a first wiring conductor, connected to an external power supply that outputs a first power supply voltage; a second wiring conductor to supply a second power supply voltage that is lower than the first power supply voltage; a standard cell to operate at the second power supply voltage supplied from the second wiring conductor; and a conversion circuit, connected to the first wiring conductor and the second wiring conductor, to convert the first power supply voltage input from the first wiring conductor into the second power supply voltage for output to the second wiring conductor.
摘要翻译：一种标准单元电路，包括：输入端输入输入信号的输入端子; 输出端子，输出输出信号; 连接到输出第一电源电压的外部电源的第一布线导体; 第二布线导体，用于提供低于第一电源电压的第二电源电压; 在从所述第二布线导体提供的所述第二电源电压下工作的标准单元; 以及转换电路，连接到第一布线导体和第二布线导体，以将从第一布线导体输入的第一电源电压转换为第二电源电压，以输出到第二布线导体。

40. 发明授权

US08006205B2 Semiconductor device layout method, a computer program, and a semiconductor device manufacture method 有权
标题翻译：半导体器件布局方法，计算机程序和半导体器件制造方法
公开(公告)号：US08006205B2
公开(公告)日：2011-08-23
申请号：US11715246
申请日：2007-03-06
申请人： Keiichi Yoshioka
发明人： Keiichi Yoshioka
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device layout method is disclosed, wherein vias carrying the same signal are arranged at intervals equal to the minimum value defined by a design rule, and vias carrying different signals are arranged at second intervals that are greater than the minimum value.
摘要翻译：公开了一种半导体器件布局方法，其中携带相同信号的通孔以等于由设计规则定义的最小值的间隔布置，并且携带不同信号的通孔以大于最小值的第二间隔布置。

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