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41. 发明授权

US07930654B2 System and method of correcting errors in SEM-measurements 有权
标题翻译：校正SEM测量误差的系统和方法
公开(公告)号：US07930654B2
公开(公告)日：2011-04-19
申请号：US12112835
申请日：2008-04-30
申请人： Uwe Kramer , Robert Wildfeuer
发明人： Uwe Kramer , Robert Wildfeuer
IPC分类号： G06F17/50
CPC分类号： H01J37/263 , G03F1/36 , G03F1/84 , G03F7/70441 , G03F7/70516 , G03F7/70616 , G03F7/70625 , G06T7/0006 , G06T7/13 , G06T2207/10061 , G06T2207/30148 , H01J37/265 , H01J37/28 , H01J2237/2826 , H01L22/12
摘要： Embodiments of the invention relate to correcting errors in scanning electron measurements during measuring structural dimensions of an integrated circuit for optical proximity correction by extracting feature edges of a test pattern within an image, calculating at least one scaling error of the image by comparing the extracted feature edges of assist structures with a layout pattern, modifying feature edges of test structures within the test pattern by incorporating the at least one scaling error so as to at least partially compensate the scaling errors, and verifying a model for optical proximity corrections and/or model input data by using the modified feature edges of the test structures.
摘要翻译：本发明的实施例涉及通过提取图像内的测试图案的特征边缘来测量用于光学邻近校正的集成电路的结构尺寸来校正扫描电子测量中的误差，通过将所提取的特征进行比较来计算图像的至少一个缩放误差具有布局图案的辅助结构的边缘，通过结合至少一个缩放误差来修改测试图案内的测试结构的特征边缘，以便至少部分地补偿缩放误差，以及验证光学邻近校正和/或模型的模型通过使用测试结构的修改后的特征边缘输入数据。

42. 发明授权

US07929336B2 Integrated circuit including a memory element programmed using a seed pulse 有权
标题翻译：集成电路包括使用种子脉冲编程的存储元件
公开(公告)号：US07929336B2
公开(公告)日：2011-04-19
申请号：US12137096
申请日：2008-06-11
申请人： Jan Boris Philipp , Thomas Happ , Bernhard Ruf , Christian Rüster
发明人： Jan Boris Philipp , Thomas Happ , Bernhard Ruf , Christian Rüster
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2013/0092 , G11C2213/79
摘要： An integrated circuit includes a resistance changing memory element and a circuit. The circuit is configured to program the memory element to a crystalline state from an amorphous state by applying a seed pulse to the memory element followed by a set pulse.
摘要翻译：集成电路包括电阻变化存储元件和电路。该电路被配置为通过将晶体脉冲施加到存储元件，然后是设定脉冲，将存储元件编程为非晶状态的结晶状态。

43. 发明授权

US07928011B2 Method for structuring a substrate using a metal mask layer formed using a galvanization process 有权
标题翻译：使用使用镀锌工艺形成的金属掩模层来构造衬底的方法
公开(公告)号：US07928011B2
公开(公告)日：2011-04-19
申请号：US11969747
申请日：2008-01-04
申请人： Klaus Elian , Michael Sebald
发明人： Klaus Elian , Michael Sebald
IPC分类号： H01L21/44
CPC分类号： H01L21/0337 , H01L21/0332 , H01L24/27 , H01L24/30 , H01L2924/01006 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01074 , H01L2924/12044 , H01L2924/00
摘要： A method and intermediate product for structuring a substrate is disclosed. At least one seed layer including a first metal compound is positioned at least partially on the substrate. The seed layer is subjected to a solution comprising ions of a second metal compound. The ions are reduced in the solution by reduction means so that the second metal compound is deposited as mask layer on the seed layer.
摘要翻译：公开了一种用于构造衬底的方法和中间产物。包括第一金属化合物的至少一个种子层至少部分地位于基底上。种子层经受包含第二金属化合物的离子的溶液。离子通过还原装置在溶液中还原，使得第二金属化合物作为掩模层沉积在种子层上。

44. 发明授权

US07916524B2 Program method with locally optimized write parameters 有权
标题翻译：具有本地优化写入参数的程序方法
公开(公告)号：US07916524B2
公开(公告)日：2011-03-29
申请号：US11768540
申请日：2007-06-26
申请人： Thomas Happ , Jan Boris Philipp
发明人： Thomas Happ , Jan Boris Philipp
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0069 , G11C29/02 , G11C29/028 , G11C2013/009 , G11C2013/0092 , G11C2213/32
摘要： A method of addressing a memory cell includes applying a plurality of pulses to the memory cell, wherein a subsequent pulse has an amplitude greater than an initial pulse. In addition, a memory includes a memory cell and a control circuit configured to address the memory cell by applying a plurality of pulses to the memory cell, wherein a subsequent pulse has an amplitude greater than an initial pulse.
摘要翻译：寻址存储器单元的方法包括将多个脉冲施加到存储器单元，其中随后的脉冲具有大于初始脉冲的幅度。此外，存储器包括存储单元和控制电路，配置为通过向存储单元施加多个脉冲来对存储单元寻址，其中后续脉冲具有大于初始脉冲的幅度。

45. 发明授权

US07908232B2 Training connections in a memory arrangement 有权
标题翻译：训练连接在内存安排
公开(公告)号：US07908232B2
公开(公告)日：2011-03-15
申请号：US11844791
申请日：2007-08-24
申请人： Peter Gregorius
发明人： Peter Gregorius
IPC分类号： G06F15/18
CPC分类号： G06F13/1684
摘要： A method of training connections in a memory arrangement includes training a connection between a memory section and a receiver portion of a controller for controlling the memory arrangement before or simultaneously with a training of essentially all other connections between elements of the memory arrangement that are to be trained.
摘要翻译：训练存储器装置中的连接的方法包括训练存储器部分和控制器的接收器部分之间的连接，用于在存储器装置的元件之间的基本上所有其他连接的训练之前或同时进行控制，训练有素

46. 发明授权

US07906421B2 Method for applying solder to redistribution lines 有权
标题翻译：将焊料应用于再分配线的方法
公开(公告)号：US07906421B2
公开(公告)日：2011-03-15
申请号：US11766326
申请日：2007-06-21
申请人： Octavio Trovarelli , Martin Reiss , Bernd Zimmermann
发明人： Octavio Trovarelli , Martin Reiss , Bernd Zimmermann
IPC分类号： H01L21/00 , H01L21/44 , H01L21/4763
CPC分类号： H01L24/13 , H01L24/11 , H01L2224/05001 , H01L2224/05022 , H01L2224/05024 , H01L2224/05548 , H01L2224/05647 , H01L2224/1147 , H01L2224/13099 , H01L2224/131 , H01L2224/16 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/00014
摘要： In a method of making an electronic component, an electrically conductive redistribution line is formed on a surface of a semiconductor chip. The redistribution line includes a solder pad. A covering material is formed over the solder pad and an uncovered portion of the redistribution line is passivated. The covering material prevents passivation of the solder pad. Solder is then formed over the solder pad such that the uncovered portion of the redistribution line has solder resist properties due to the passivating.
摘要翻译：在制造电子元件的方法中，在半导体芯片的表面上形成导电再分配线。再分配线包括焊盘。覆盖材料形成在焊盘上方，再分配线的未覆盖部分被钝化。覆盖材料防止焊盘的钝化。然后在焊料焊盘上形成焊料，使得再分配线的未覆盖部分由于钝化而具有阻焊性能。

47. 发明申请

US20110057699A1 INTEGRATED CIRCUIT AND PROGRAMMABLE DELAY 有权
标题翻译：集成电路和可编程延迟
公开(公告)号：US20110057699A1
公开(公告)日：2011-03-10
申请号：US12939468
申请日：2010-11-04
申请人： Kazimierz Szczypinski
发明人： Kazimierz Szczypinski
IPC分类号： H03L7/00 , H03H11/26
CPC分类号： H03K5/135 , G11C7/22 , G11C7/222 , H03K5/133 , H03K2005/00104 , H03K2005/00123 , H03K2005/00241
摘要： Integrated circuit and programmable delay. One embodiment provides an integrated circuit including a programmable delay element having a plurality of single delay cells. The delay cells include a first input and a second input and a first output. The delay cells are arranged to form a chain such that the first output of a preceding delay cell is coupled to the second input of a successive delay cell. The first inputs of any delay cells are configured to receive an input signal to be delayed. The delay cells out of the plurality of delay cells is configured to constitute a starting point of a signal path including any of the delay cells arranged downstream of the starting point. The first output of the last delay cell in the chain forms an output of the programmable delay element.
摘要翻译：集成电路和可编程延迟。一个实施例提供了包括具有多个单个延迟单元的可编程延迟元件的集成电路。延迟单元包括第一输入和第二输入以及第一输出。延迟单元被布置成形成链，使得先前延迟单元的第一输出耦合到连续延迟单元的第二输入。任何延迟单元的第一输入被配置为接收待延迟的输入信号。多个延迟单元中的延迟单元被配置为构成包括布置在起始点下游的任何延迟单元的信号路径的起始点。链中最后一个延迟单元的第一个输出形成可编程延迟元件的输出。

48. 发明授权

US07902616B2 Integrated circuit having a magnetic tunnel junction device and method 有权
标题翻译：具有磁隧道连接装置和方法的集成电路
公开(公告)号：US07902616B2
公开(公告)日：2011-03-08
申请号：US12164736
申请日：2008-06-30
申请人： Ulrich Klostermann , Franz Kreupl
发明人： Ulrich Klostermann , Franz Kreupl
IPC分类号： H01L29/82
CPC分类号： H01L43/10 , H01L27/226 , H01L43/08
摘要： An integrated circuit having a magnetic tunnel junction and method. One embodiment provides an integrated circuit having a magnetic tunnel junction is provided. The magnetic tunnel junction includes a barrier layer. The barrier layer includes carbon, pyrolytic carbon, or graphene, or graphite.
摘要翻译：具有磁性隧道结的集成电路及其方法。一个实施例提供了一种具有磁性隧道结的集成电路。磁性隧道结包括阻挡层。阻挡层包括碳，热解碳或石墨烯或石墨。

49. 发明授权

US07882324B2 Method and apparatus for synchronizing memory enabled systems with master-slave architecture 有权
标题翻译：用于使具有主从结构的存储器启用系统同步的方法和装置
公开(公告)号：US07882324B2
公开(公告)日：2011-02-01
申请号：US11928633
申请日：2007-10-30
申请人： Josef Schnell , Klaus Hummler , Jong Hoon Oh , Wayne Frederick Ellis , Jung Pill Kim , Oliver Kiehl , Octavian Beldiman , Lee Ward Collins
发明人： Josef Schnell , Klaus Hummler , Jong Hoon Oh , Wayne Frederick Ellis , Jung Pill Kim , Oliver Kiehl , Octavian Beldiman , Lee Ward Collins
IPC分类号： G06F12/00
CPC分类号： G06F13/1689 , G06F1/10 , G11C7/22 , G11C2207/2254
摘要： Embodiments of the invention generally provide a system, method and memory device for accessing memory. One embodiment includes synchronization circuitry configured to determine timing skew between a first memory device and a second memory device, and introduce a delta delay to at least one of the first memory device and the second memory device to adjust the timing skew.
摘要翻译：本发明的实施例通常提供用于访问存储器的系统，方法和存储器件。一个实施例包括被配置为确定第一存储器设备和第二存储器设备之间的定时偏差的同步电路，并且向第一存储器设备和第二存储器设备中的至少一个引入增量延迟以调整定时偏差。

50. 发明授权

US07880309B2 Arrangement of stacked integrated circuit dice having a direct electrical connection 有权
标题翻译：具有直接电气连接的堆叠集成电路芯片的布置
公开(公告)号：US07880309B2
公开(公告)日：2011-02-01
申请号：US11830614
申请日：2007-07-30
申请人： Camillo Pilla
发明人： Camillo Pilla
IPC分类号： H01L23/49 , H01L23/52 , H01L23/02 , H01L23/495
CPC分类号： H01L25/0657 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05553 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/4911 , H01L2224/49113 , H01L2224/49175 , H01L2224/73265 , H01L2224/92247 , H01L2225/06506 , H01L2225/06513 , H01L2225/06555 , H01L2225/06562 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01031 , H01L2924/01033 , H01L2924/01049 , H01L2924/01058 , H01L2924/01078 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： An arrangement of integrated circuit dice, includes first die including a first electrical coupling site and a second die comprising a second electrical coupling site, wherein the second die is stacked onto the first die such that the first electrical coupling site is at least partially exposed, wherein the first electrical coupling site and the second electrical coupling site are directly electrically connected, and a third die arranged above the first die and the second die such that a recess is formed, wherein one of the first electrical coupling sites is arranged in the recess.
摘要翻译：集成电路芯片的布置包括包括第一电耦合位置的第一管芯和包括第二电耦合部位的第二管芯，其中第二管芯被堆叠在第一管芯上，使得第一电耦合部位至少部分地露出，其中所述第一电耦合位置和所述第二电耦合位置直接电连接，以及设置在所述第一管芯和所述第二管芯上方的第三管芯，使得形成凹部，其中所述第一电耦合部位之一布置在所述凹部。

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