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41. 发明授权

US07869343B1 Field programmable gate array architectures and methods for supporting forward error correction 有权
标题翻译：用于支持前向纠错的现场可编程门阵列架构和方法
公开(公告)号：US07869343B1
公开(公告)日：2011-01-11
申请号：US11447745
申请日：2006-06-05
申请人： Ning Xue , Chong H. Lee
发明人： Ning Xue , Chong H. Lee
IPC分类号： G06F11/00
CPC分类号： H04L1/0041
摘要： A field-programmable gate array (“FPGA”) or programmable logic device (“PLD”) includes relatively general-purpose PLD core circuitry and relatively specialized high-speed serial interface (“HSSI”) hard IP circuitry. To better support applications that include forward error correction (“FEC”), some tasks related to FEC (e.g., FIFO operations) are performed in the PLD core circuitry, while other FEC tasks (e.g., FEC calculations) are performed in the HSSI hard IP circuitry.
摘要翻译：现场可编程门阵列（“FPGA”）或可编程逻辑器件（“PLD”）包括相对通用的PLD核心电路和相对专门的高速串行接口（“HSSI”）硬IP电路。为了更好地支持包括前向纠错（“FEC”）的应用，在PLD核心电路中执行与FEC相关的一些任务（例如FIFO操作），而在HSSI硬执行其他FEC任务（例如，FEC计算） IP电路。

42. 发明授权

US07646217B2 Programmable logic device with serial interconnect 有权
标题翻译：具有串行互连的可编程逻辑器件
公开(公告)号：US07646217B2
公开(公告)日：2010-01-12
申请号：US11539006
申请日：2006-10-05
申请人： Ramanand Venkata , Rakesh H. Patel , Chong H. Lee
发明人： Ramanand Venkata , Rakesh H. Patel , Chong H. Lee
IPC分类号： H01L25/00
CPC分类号： H03K19/17736 , H03K19/17744 , H03K19/17784
摘要： In a programmable logic device, some or all of the parallel interconnect resources are replaced by serial interconnect resources within the device. Some or all of the functional blocks on the device are supplemented with serial interfaces. Although this makes the functional blocks more complex, it allows a significant reduction in the area consumed by interconnect resources. This translates into a significant reduction in device power consumption. The serial interfaces may operate synchronously from a global device clock (such as a PLL). In some cases, serial interfaces that are provided in the input/output blocks for external signalling can be omitted because the serial interfaces in the functional blocks can take over the external serial interface function as well, although in those cases the serial interfaces in the functional blocks would have to be more complex because they would have to be able to operate asynchronously with external devices.
摘要翻译：在可编程逻辑器件中，部分或全部并行互连资源由器件内的串行互连资源代替。设备上的部分或全部功能块被补充有串行接口。尽管这使得功能块更加复杂，但它允许显着减少互连资源消耗的面积。这意味着设备功耗的显着降低。串行接口可以与全局设备时钟（例如PLL）同步工作。在某些情况下，可以省略输入/输出块中提供的用于外部信号的串行接口，因为功能块中的串行接口也可以接管外部串行接口功能，尽管在这些情况下，功能中的串行接口块将不得不更复杂，因为它们必须能够与外部设备异步操作。

43. 发明授权

US06888376B1 Multiple data rates in programmable logic device serial interface 有权
标题翻译：可编程逻辑器件串行接口中的多个数据速率
公开(公告)号：US06888376B1
公开(公告)日：2005-05-03
申请号：US10670845
申请日：2003-09-24
申请人： Ramanand Venkata , Chong H. Lee , Rakesh Patel
发明人： Ramanand Venkata , Chong H. Lee , Rakesh Patel
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/1778 , H03K19/17796
摘要： A serial interface for a programmable logic device supports a higher physical medium attachment (“PMA”) data rate than the available physical coding sublayer (“PCS”) data rate by using multiple PCS modules, operating in parallel, to support one PMA module. In a channel-based structure, the PMA module is supported by a PCS module in its own channel and at least one PCS module from a second channel. The second channel may include its own PMA module which, if provided, may operate at a lower rate, supportable by the PCS module in that channel. Optionally, two modes are provided. In one mode, two PCS modules in two channels support one higher-speed PMA module in one of the channels. In a second mode, each PCS module supports a PMA module in its own channel, with the higher-speed PMA module constrained to operate at the lower data rate of the PCS module.
摘要翻译：用于可编程逻辑器件的串行接口通过使用并行操作的多个PCS模块来支持比可用物理编码子层（“PCS”）数据速率更高的物理介质附加（“PMA”）数据速率，以支持一个PMA模块。在基于通道的结构中，PMA模块由其自身通道中的PCS模块和来自第二通道的至少一个PCS模块支持。第二通道可以包括其自己的PMA模块，如果提供的话，该模块可以以较低的速率操作，由PCS模块在该通道中支持。可选地，提供两种模式。在一种模式下，两个通道中的两个PCS模块在其中一个通道中支持一个更高速的PMA模块。在第二种模式下，每个PCS模块都支持自己的通道中的PMA模块，而高速PMA模块则被限制在PCS模块的较低数据速率下工作。

44. 发明授权

US06650140B2 Programmable logic device with high speed serial interface circuitry 有权
公开(公告)号：US06650140B2
公开(公告)日：2003-11-18
申请号：US10093785
申请日：2002-03-06
申请人： Chong H. Lee , Reza Asayesh
发明人： Chong H. Lee , Reza Asayesh
IPC分类号： H03K19177
CPC分类号： H03K19/17744 , H03K19/17732
摘要： A programmable logic device (“PLD”) includes high speed serial interface (“HSSI”) circuitry that can support several high speed serial (“HSS”) standards. Examples of the standards that can be supported are XAUI, InfiniBand, 1G Ethernet, FibreChannel, and Serial RapidIO. The HSSI circuitry may be partly programmable to support these various standards. In some cases control may come from the associated PLD core circuitry. Also in some cases some of the interface functions may be performed in the PLD core circuitry.

45. 发明申请

US20100058099A1 HETEROGENEOUS TRANSCEIVER ARCHITECTURE FOR WIDE RANGE PROGRAMMABILITY OF PROGRAMMABLE LOGIC DEVICES 有权
标题翻译：用于可编程逻辑器件的宽范围可编程性的异构收发器架构
公开(公告)号：US20100058099A1
公开(公告)日：2010-03-04
申请号：US12576507
申请日：2009-10-09
申请人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
发明人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
IPC分类号： G06F1/04 , G06F1/12
CPC分类号： H04L5/14 , H03K19/17744 , H04L27/00
摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.
摘要翻译：可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道达到第二个相对较高的最大数据速率。相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

46. 发明授权

US07138837B2 Digital phase locked loop circuitry and methods 有权
标题翻译：数字锁相环电路及方法
公开(公告)号：US07138837B2
公开(公告)日：2006-11-21
申请号：US10349541
申请日：2003-01-21
申请人： Ramanand Venkata , Chong H. Lee , Henry Lui
发明人： Ramanand Venkata , Chong H. Lee , Henry Lui
IPC分类号： H03L7/00
CPC分类号： H03L7/089 , H03L2207/50 , H04L7/0337
摘要： Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal.
摘要翻译：锁相环电路以数字方式进行数字操作，至少在很大程度上从多个相位分布的候选时钟信号中选择最接近相位的信号，以便在诸如时钟数据恢复（“CDR”）信号的另一个信号中转换。该电路被构造和操作以避免由于候选时钟信号的选择变化而导致的输出时钟信号中的毛刺。

47. 发明授权

US07064685B1 Data converter with reduced component count for padded-protocol interface 失效
标题翻译：数据转换器，减少了填充协议接口的组件数量
公开(公告)号：US07064685B1
公开(公告)日：2006-06-20
申请号：US10969448
申请日：2004-10-20
申请人： Ning Xue , Chong H. Lee
发明人： Ning Xue , Chong H. Lee
IPC分类号： H03M7/00
CPC分类号： H04L25/4908
摘要： A data converter, or “gearbox,” for a padded protocol interface uses a reduced number of components by processing a narrower intermediate data stream, while at the same time multiplying the clock speed of its intermediate input and output so that it processes more data per clock cycle. The data streams can be narrowed to any integer factor of the original width (other than the original width).
摘要翻译：用于填充协议接口的数据转换器或“变速箱”通过处理较窄的中间数据流来减少数量的组件，同时将其中间输入和输出的时钟速度乘以使其处理更多的数据时钟周期。数据流可以缩小为原始宽度（原始宽度除外）的任何整数因子。

48. 发明授权

US06963223B2 Programmable logic devices with multi-standard byte synchronization and channel alignment for communication 有权
公开(公告)号：US06963223B2
公开(公告)日：2005-11-08
申请号：US10835081
申请日：2004-04-28
申请人： Ramanand Venkata , Chong H. Lee , Rakesh Patel
发明人： Ramanand Venkata , Chong H. Lee , Rakesh Patel
IPC分类号： H03K19/177 , H04Q11/04
CPC分类号： H03K19/17744 , H03K19/17732 , H04J3/1617 , H04J2203/0082 , H04J2203/0094
摘要： A programmable logic device (“PLD”) includes communication interface circuitry that can support any of a wide range of communication protocols, including Packet Over Sonet (“POS-5”) and 8-bit/10-bit (“8B10B”) protocols. The interface circuitry includes various functional blocks that are at least partly hard-wired to perform particular types of functions, but that in at least many cases are also partly programmable to allow the basic functions to be adapted for various protocols. Routing of signals to, from, between, and/or around the various functional blocks is also preferably at least partly programmable to facilitate combining the functional blocks in various ways to support various protocols.

49. 发明授权

US06854044B1 Byte alignment circuitry 有权
标题翻译：字节对齐电路
公开(公告)号：US06854044B1
公开(公告)日：2005-02-08
申请号：US10317262
申请日：2002-12-10
申请人： Ramanand Venkata , Chong H. Lee
发明人： Ramanand Venkata , Chong H. Lee
IPC分类号： G06F12/00 , G06F13/40 , H04J3/06
CPC分类号： G06F13/4018 , H04J3/0608
摘要： Circuitry for locating the boundaries between bytes in a data stream is only selectively enabled to find a possible new byte alignment by a control signal. After the byte alignment circuitry has found a byte alignment, it outputs byte-aligned data and a first status signal indicating the presence of such data. If the byte alignment circuitry subsequently detects information that suggests a possible need for a new or changed byte alignment, it outputs a second status signal to that effect. However, the byte alignment circuitry does not actually attempt to change its byte alignment until enabled to do so by the control signal. Programmable logic circuitry or other utilization circuitry is typically provided to receive the outputs of the byte alignment circuitry and to selectively provide the control signal.
摘要翻译：用于定位数据流中的字节之间的边界的电路仅被选择性地用于通过控制信号找到可能的新字节对齐。在字节对齐电路找到一个字节对齐之后，它输出字节对齐的数据和指示这种数据的存在的第一状态信号。如果字节对齐电路随后检测出可能需要新的或改变的字节对齐的信息，则输出第二状态信号。然而，字节对齐电路实际上并不会尝试改变其字节对齐，直到通过控制信号使其能够这样做。通常提供可编程逻辑电路或其他利用电路以接收字节对准电路的输出并选择性地提供控制信号。

50. 发明授权

US06771105B2 Voltage controlled oscillator programmable delay cells 有权
标题翻译：压控振荡器可编程延时单元
公开(公告)号：US06771105B2
公开(公告)日：2004-08-03
申请号：US10099707
申请日：2002-03-13
申请人： Stjepan William Andrasic , Rakesh H. Patel , Chong H. Lee
发明人： Stjepan William Andrasic , Rakesh H. Patel , Chong H. Lee
IPC分类号： H03H1126
CPC分类号： H03K5/133 , H03K3/0322 , H03K3/354 , H03L7/0995 , H03L7/10
摘要： A delay cell has selectable numbers of parallel load resistance transistors operable in parallel, and a similarly selectable number of bias current transistors connectable in parallel. The delay cell is preferably differential in construction and operation. A voltage controlled oscillator (“VCO”) includes a plurality of such delay cells connected in a closed loop series. Phase locked loop (“PLL”) circuitry includes such a VCO controlled by phase/frequency detector circuitry. The PLL can have a very wide range of operating frequencies as a result of the ability to control the number of load resistance transistors and bias current transistors that are active or inactive in each delay cell. Such activation/deactivation may be programmable or otherwise controlled.
摘要翻译：延迟单元具有可并行操作的并联负载电阻晶体管的可选数量，以及可并联连接的类似可选数量的偏置电流晶体管。延迟单元优选在构造和操作上是不同的。压控振荡器（“VCO”）包括以闭环系列连接的多个这样的延迟单元。锁相环（“PLL”）电路包括由相位/频率检测器电路控制的这种VCO。由于能够控制在每个延迟单元中有效或无效的负载电阻晶体管和偏置电流晶体管的数量，PLL可以具有非常宽的工作频率范围。这种激活/去激活可以是可编程的或以其他方式控制的。

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