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41. 发明授权

US09252240B2 Manufacturing method for semiconductor device with discrete field oxide structure 有权
标题翻译：具有离散场氧化物结构的半导体器件的制造方法
公开(公告)号：US09252240B2
公开(公告)日：2016-02-02
申请号：US14436016
申请日：2013-12-31
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Jian Xu , Min He , Shu Zhang , Zehuang Luo , Xiaojia Wu
IPC分类号： H01L21/762 , H01L29/66 , H01L29/10 , H01L21/02 , H01L21/265 , H01L21/306 , H01L21/311 , H01L29/40
CPC分类号： H01L29/66681 , H01L21/0217 , H01L21/02233 , H01L21/02238 , H01L21/265 , H01L21/26513 , H01L21/30604 , H01L21/31111 , H01L21/31116 , H01L21/32 , H01L21/76213 , H01L29/0653 , H01L29/1095 , H01L29/408
摘要： A manufacturing method for a semiconductor device with a discrete field oxide structure is provided, the method includes: growing a first PAD oxide layer on the surface of a wafer; forming a first silicon nitride layer (302) on the first PAD oxide layer through deposition; defining a field region by photolithography and etching same to remove the first silicon nitride layer (302) located on the field region; performing an ion implantation process to the field region; performing field region oxidation to grow a field oxide layer (304); peeling off the first silicon nitride layer (302); wet-dipping the wafer to remove the first PAD oxide layer and a part of field oxide layer (304); growing a second PAD oxide layer on the surface of the wafer, and forming a second silicon nitride layer (312) on the second PAD oxide layer through deposition; defining a drift region by photolithography and etching same to remove the second silicon nitride layer (312) on the drift region; performing an ion implantation process to the drift region; and performing drift region oxidation to grow a drift region oxide layer (314). The above-mentioned method peels off the silicon nitride layer (302) after the growth of the field oxide layer (304) is finished, at this time, the length of a bird beak of field-oxide (304) can be optimized by adjusting a wet-dipping amount to solve the problem that the bird beak of field-oxide (304) is too long.
摘要翻译：提供一种具有离散场氧化物结构的半导体器件的制造方法，该方法包括：在晶片表面上生长第一PAD氧化物层; 通过沉积在所述第一PAD氧化物层上形成第一氮化硅层（302）; 通过光刻法定义场区域并进行蚀刻以去除位于场区域上的第一氮化硅层（302）; 对场区进行离子注入工艺; 进行场区氧化以生长场氧化物层（304）; 剥离第一氮化硅层（302）; 湿浸湿晶片以去除第一PAD氧化物层和一部分场氧化物层（304）; 在所述晶片的表面上生长第二PAD氧化物层，并且通过沉积在所述第二PAD氧化物层上形成第二氮化硅层（312）; 通过光刻法定义漂移区域并进行蚀刻以去除漂移区域上的第二氮化硅层（312）; 对漂移区域进行离子注入工艺; 以及进行漂移区氧化以生长漂移区氧化物层（314）。上述方法在场氧化物层（304）的生长完成之后，剥离氮化硅层（302），此时可以通过调整场氧化物（304）的鸟喙的长度来优化用于解决场氧化物（304）的鸟喙太长的问题的湿浸量。

42. 发明授权

US09166399B2 Lithium battery protection circuitry 有权
标题翻译：锂电池保护电路
公开(公告)号：US09166399B2
公开(公告)日：2015-10-20
申请号：US13807635
申请日：2011-11-29
申请人： Shunhui Lei
发明人： Shunhui Lei
IPC分类号： H02J7/00 , H02H7/18
CPC分类号： H02H7/18 , H02J7/0029 , H02J7/0031 , H02J2007/0039 , Y02E60/12
摘要： A lithium battery protection circuit coupled to a lithium battery is provided. The lithium battery protection circuit includes an over-charge protection circuit and a logic circuit coupled to over-charge protection circuit. The logic circuit has a first logic output and a second logic output. The lithium battery protection circuit also includes a level shift circuit coupled to the logic circuit through the first logic output and the second logic output, and the level shift circuit is configured to convert the first logic output and the second logic output to high voltage levels in an over-charge protection state. Further, the lithium battery protection circuit includes a substrate switching circuit coupled to the level shift circuit and a power transistor coupled between a negative end of the lithium battery and an external circuit negative electrode. The level shift circuit includes a first inverter coupled to the second logic output, a plurality of PMOS transistors, at least one of which has high source-drain voltage and low gate-source voltage, and a plurality of NMOS transistors, at least one of which is a low-voltage NMOS transistor.
摘要翻译：提供耦合到锂电池的锂电池保护电路。锂电池保护电路包括过充电保护电路和耦合到过充电保护电路的逻辑电路。逻辑电路具有第一逻辑输出和第二逻辑输出。锂电池保护电路还包括通过第一逻辑输出和第二逻辑输出耦合到逻辑电路的电平移位电路，并且电平移位电路被配置为将第一逻辑输出和第二逻辑输出转换成高电压电平过充保护状态。此外，锂电池保护电路包括耦合到电平移位电路的衬底切换电路和耦合在锂电池的负端和外部电路负极之间的功率晶体管。电平移位电路包括耦合到第二逻辑输出的第一反相器，多个PMOS晶体管，其中至少一个具有高源极 - 漏极电压和低栅极 - 源极电压，以及多个NMOS晶体管，至少一个其是低电压NMOS晶体管。

43. 发明申请

US20150270139A1 CORROSION METHOD OF PASSIVATION LAYER OF SILICON WAFER 有权
标题翻译：硅腐蚀钝化层腐蚀方法
公开(公告)号：US20150270139A1
公开(公告)日：2015-09-24
申请号：US14436037
申请日：2013-12-31
申请人： CSMC TECHNOLOGIES CO., LTD.
发明人： Qiliang Sun
IPC分类号： H01L21/311
CPC分类号： H01L21/31116 , B81C1/00476 , B81C2201/0132
摘要： A corrosion method of a passivation layer (320) of a silicon wafer (300) includes: pouring hydrofluoric acid solution (100) into a container (200) with an open top; putting the silicon wafer (300) to the opening of the container (200) and one side of the silicon wafer (300) with the passivation layer (320) is opposite to the hydrofluoric acid solution (100); the hydrogen fluoride gas generated from the volatilization of the hydrofluoric acid solution (100) corrodes the passivation layer (320) of the silicon wafer (300), the corrosion time is larger or equal to (thickness of the passivation layer/corrosion rate). By means of the corrosion of the passivation layer of silicon wafer by the fluoride gas generated from the volatilization of the hydrofluoric acid solution, the fluoride gas can fully touch the passivation layer; therefore the passivation layer can be completely corroded, and the corrosion precision is high.
摘要翻译：硅晶片（300）的钝化层（320）的腐蚀方法包括：将氢氟酸溶液（100）倒入具有开口顶部的容器（200）中; 将硅晶片（300）放置到容器（200）的开口，并且具有钝化层（320）的硅晶片（300）的一侧与氢氟酸溶液（100）相反; 由氢氟酸溶液（100）的挥发产生的氟化氢气体腐蚀硅晶片（300）的钝化层（320），腐蚀时间大于或等于（钝化层的厚度/腐蚀速率）。通过由氢氟酸溶液的挥发产生的氟化物气体对硅晶片的钝化层的腐蚀，氟化物气体可完全接触钝化层; 因此钝化层可以完全腐蚀，腐蚀精度高。

44. 发明申请

US20150233965A1 PARALLEL PLATE CAPACITOR AND ACCELERATION SENSOR COMPRISING SAME 有权
标题翻译：平行平板电容器和加速传感器包括相同
公开(公告)号：US20150233965A1
公开(公告)日：2015-08-20
申请号：US14435925
申请日：2013-08-30
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Meihan Guo , Xinwei Zhang , Changfeng Xia , Wei Su
IPC分类号： G01P15/125 , B81B7/02 , H02N1/08
CPC分类号： G01P15/125 , B81B7/02 , G01P2015/0837 , H01G5/16 , H02N1/08
摘要： A parallel plate capacitor includes a first polar plate (10), and a second polar plate disposed opposite to the first polar plate (10). The parallel plate capacitor further includes at least a pair of sensitive units disposed on a substrate forming the first polar plate (10); the sensitive units includes sensitive elements (21a, 21b, 22a, 22b) and element connecting arms (23a, 23b, 24a, 24b) connecting the sensitive elements (21a, 21b, 22a, 22b) to the first polar plate (10). The parallel plate capacitor further includes anchoring bases (30, 31, 32, 33) disposed on a substrate where the second polar plate is located; the anchoring bases (30, 31, 32, 33) are connected to the element connecting arms (23a, 23b, 24a, 24b) via cantilever beams (30a, 30b, 31a, 31b, 32a, 32b, 33a, 33b); each element connecting arm (23a, 23b, 24a, 24b) is connected to at least two anchoring bases (30, 31, 32, 33), which are symmetric with respect to the element connecting arm. The parallel plate capacitor is more likely to be influenced by an external factor, thus being more likely to experience capacitance change. An acceleration sensor including the parallel plate capacitor is also provided.
摘要翻译：平行板电容器包括第一极板（10）和与第一极板（10）相对设置的第二极板。平行板电容器还包括至少一对设置在形成第一极板（10）的基板上的敏感单元。敏感单元包括将敏感元件（21a，21b，22a，22b）连接到第一极板（10）的敏感元件（21a，21b，22a，22b）和元件连接臂（23a，23b，24a，24b）。平行板电容器还包括设置在第二极板所在的基板上的固定基座（30,31,32,33）。通过悬臂梁（30a，30b，31a，31b，32a，32b，33a，33b）将锚定基座（30,31,32,33）连接到元件连接臂（23a，23b，24a，24b）每个元件连接臂（23a，23b，24a，24b）连接到至少两个相对于元件连接臂对称的锚定基座（30,31,32,33）。并联平板电容更可能受到外部因素的影响，因此更容易发生电容变化。还提供了包括平行板电容器的加速度传感器。

45. 发明申请

US20150175409A1 METHOD FOR FABRICATING MULTI-TRENCH STRUCTURE 审中-公开
标题翻译：制作多层结构的方法
公开(公告)号：US20150175409A1
公开(公告)日：2015-06-25
申请号：US14411989
申请日：2013-08-19
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Xinwei Zhang , Dan Dai , Guoping Zhou , Changfeng Xia
IPC分类号： B81C1/00
CPC分类号： B81C1/0038 , B81B2203/0127 , B81C1/00158 , B81C1/00531
摘要： Provided is a method for fabricating a multi-trench structure, including steps of: performing anisotropic etching on a semiconductor substrate so as to form a vertical trench; growing a first epitaxial layer on the semiconductor substrate in which the vertical trench has been formed, so that the first epitaxial layer covers the top of the vertical trench to form a closed structure; performing anisotropic and isotropic etching on the closed structure, so as to form a trench array, and to make the trench array communicate with the vertical trench, the trench array including a number of trenches or vias, upper portions of a number of trenches or vias being separated from each other, and lower portions thereof communicating with each other to form a cavity; and growing a second epitaxial layer to cover the trench array, so as to form a closed multi-trench structure. With two times of growth of the epitaxial layers, the multi-trench structure remains stable and solid in a fabricating process, which prevents phenomena of film breakage or falling off in the fabricating process.
摘要翻译：提供一种制造多沟槽结构的方法，包括以下步骤：在半导体衬底上进行各向异性蚀刻以形成垂直沟槽; 在其上形成有垂直沟槽的半导体衬底上生长第一外延层，使得第一外延层覆盖垂直沟槽的顶部以形成闭合结构; 在闭合结构上执行各向异性和各向同性蚀刻，以便形成沟槽阵列，并且使沟槽阵列与垂直沟槽连通，沟槽阵列包括多个沟槽或通孔，多个沟槽或通孔的上部彼此分离，并且其下部彼此连通以形成空腔; 以及生长第二外延层以覆盖沟槽阵列，以便形成封闭的多沟槽结构。通过外延层的两次生长，多沟槽结构在制造过程中保持稳定和稳定，这防止了制造过程中膜断裂或脱落的现象。

46. 发明授权

US08803250B2 Metal-oxide-semiconductor field-effect transistor and method for manufacturing the same 有权
标题翻译：金属氧化物半导体场效应晶体管及其制造方法
公开(公告)号：US08803250B2
公开(公告)日：2014-08-12
申请号：US13807308
申请日：2011-11-18
申请人： Le Wang
发明人： Le Wang
IPC分类号： H01L29/02 , H01L29/66 , H01L29/78 , H01L29/10
CPC分类号： H01L29/78 , H01L29/1033 , H01L29/66477 , H01L29/66651
摘要： A Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is disclosed. The MOSFET includes a substrate, a well region formed in the substrate, a shallow channel layer, a channel, a gate oxide layer, a gate region, a source region, and a drain region. The shallow channel layer is formed on a portion of the well region and includes a first shallow channel region and a second shallow channel region. The channel is arranged between the first shallow channel region and the second shallow channel region and connects the first shallow channel region and the second shallow channel region. Further, the gate oxide layer is formed on a portion of the well region between the first shallow channel region and the second shallow channel region and includes a first gate oxide region and a second gate oxide region arranged on different sides of the channel. The gate region is formed on the channel and the gate oxide layer; the source region is formed in the first shallow channel region and vertically extends into the well region under the first shallow channel region; and the drain region is formed in the second shallow channel region and vertically extends into the well region under the second shallow channel region.
摘要翻译：公开了一种金属氧化物半导体场效应晶体管（MOSFET）。 MOSFET包括衬底，形成在衬底中的阱区，浅沟道层，沟道，栅极氧化物层，栅极区，源极区和漏极区。浅沟道层形成在阱区的一部分上，并且包括第一浅沟道区和第二浅沟道区。通道布置在第一浅沟道区域和第二浅沟道区域之间，并且连接第一浅沟道区域和第二浅沟道区域。此外，栅极氧化层形成在第一浅沟道区域和第二浅沟道区域之间的阱区域的一部分上，并且包括布置在沟道的不同侧上的第一栅极氧化物区域和第二栅极氧化物区域。栅极区形成在沟道和栅极氧化物层上; 源极区域形成在第一浅沟道区域中并垂直延伸到第一浅沟道区域下方的阱区域中; 并且所述漏极区域形成在所述第二浅沟道区域中并且垂直延伸到所述第二浅沟道区域下方的阱区域中。

47. 发明授权

US08772864B2 Trench MOSFET device and method for fabricating the same 有权
标题翻译：沟槽MOSFET器件及其制造方法
公开(公告)号：US08772864B2
公开(公告)日：2014-07-08
申请号：US13807612
申请日：2011-11-29
申请人： Jiakun Wang
发明人： Jiakun Wang
IPC分类号： H01L29/66
CPC分类号： H01L29/7827 , H01L29/4236 , H01L29/66666
摘要： A trench Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) device is disclosed. The trench MOSFET device includes a substrate, a body region, a source region, a dielectric layer, a metal layer, a contact hole, and a trench structure. The substrate includes a substrate layer and an epitaxial layer formed on the substrate layer; the body region is formed in the epitaxial layer; and the source region is formed in the body region of the epitaxial layer. Further, the dielectric layer is formed on the epitaxial layer; the metal layer is formed on the dielectric layer; and the contact hole is formed in the dielectric layer to connect the source region with the metal layer. In addition, the trench structure is formed in the epitaxial layer, and the trench structure includes a first trench that is a pectinate trench including a plurality of tooth trenches and a bar trench interconnecting the plurality of tooth trenches.
摘要翻译：公开了一种沟槽金属氧化物半导体场效应晶体管（MOSFET）器件。沟槽MOSFET器件包括衬底，体区，源极区，电介质层，金属层，接触孔和沟槽结构。衬底包括衬底层和形成在衬底层上的外延层; 在外延层中形成体区; 并且源区域形成在外延层的体区中。此外，介电层形成在外延层上; 金属层形成在电介质层上; 并且在电介质层中形成接触孔以将源极区域与金属层连接。此外，沟槽结构形成在外延层中，并且沟槽结构包括第一沟槽，其是包括多个齿槽的果胶沟槽和互连多个齿槽的条形沟槽。

48. 发明申请

US20140147980A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20140147980A1
公开(公告)日：2014-05-29
申请号：US14130476
申请日：2012-11-28
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Hsiaochia Wu , Shilin Fang , Tsehuang Lo , Zhengpei Chen , Shu Zhang , Yanqiang He
IPC分类号： H01L21/8234 , H01L21/8238
CPC分类号： H01L21/823412 , H01L21/823456 , H01L21/8238 , H01L21/823807 , H01L21/82385 , H01L27/0922
摘要： The present invention relates to the technical field of semiconductor manufacturing. A method for manufacturing a semiconductor device is disclosed, which solves the problem in the prior art that the silicon on the edge of an oxide layer in an LDMOS drift region is easily exposed and causes breakdown of an LDMOS device. The method includes: providing a semiconductor substrate comprising an LDMOS region and a CMOS region; forming a sacrificial oxide layer on the semiconductor substrate; removing the sacrificial oxide layer; forming a masking layer on the semiconductor substrate after the sacrificial oxidation treatment; using the masking layer as a mask to form an LDMOS drift region, and forming a drift region oxide layer above the drift region; and removing the masking layer. The embodiment of the present invention is applicable to a BCD process and the like.
摘要翻译：本发明涉及半导体制造技术领域。公开了一种用于制造半导体器件的方法，其解决了现有技术中在LDMOS漂移区域中的氧化物层的边缘上的硅容易暴露并导致LDMOS器件破坏的问题。该方法包括：提供包括LDMOS区域和CMOS区域的半导体衬底; 在所述半导体衬底上形成牺牲氧化物层; 去除牺牲氧化物层; 在牺牲氧化处理后在半导体衬底上形成掩模层; 使用掩模层作为掩模形成LDMOS漂移区，以及在漂移区上方形成漂移区氧化物层; 并去除掩模层。本发明的实施例可应用于BCD处理等。

49. 发明授权

US08530961B2 Compatible vertical double diffused metal oxide semiconductor transistor and lateral double diffused metal oxide semiconductor transistor and manufacture method thereof 有权
标题翻译：兼容的垂直双扩散金属氧化物半导体晶体管和横向双扩散金属氧化物半导体晶体管及其制造方法
公开(公告)号：US08530961B2
公开(公告)日：2013-09-10
申请号：US13384002
申请日：2010-10-26
申请人： Linchun Gui , Le Wang , Zhiyong Zhao , Lili He
发明人： Linchun Gui , Le Wang , Zhiyong Zhao , Lili He
IPC分类号： H01L29/66 , H01L21/336
CPC分类号： H01L29/66712 , H01L21/823418 , H01L21/823487 , H01L21/8249 , H01L27/088 , H01L29/0847 , H01L29/42368 , H01L29/66659 , H01L29/7809 , H01L29/7835
摘要： A method for manufacturing compatible vertical double diffused metal oxide semiconductor (VDMOS) transistor and lateral double diffused metal oxide semiconductor (LDMOS) transistor includes: providing a substrate having an LDMOS transistor region and a VDMOS transistor region; forming an N-buried region in the substrate; forming an epitaxial layer on the N-buried layer region; forming isolation regions in the LDMOS transistor region and the VDMOS transistor region; forming a drift region in the LDMOS transistor region; forming gates in the LDMOS transistor region and the VDMOS transistor region; forming PBODY regions in the LDMOS transistor region and the VDMOS transistor region; forming an N-type GRADE region in the LDMOS transistor region; forming an NSINK region in the VDMOS transistor region, where the NSINK region is in contact with the N-buried layer region; forming sources and drains in the LDMOS transistor region and the VDMOS transistor region; and forming a P+ region in the LDMOS transistor region, where the P+ region is in contact with the source.
摘要翻译：制造兼容的垂直双扩散金属氧化物半导体（VDMOS）晶体管和横向双扩散金属氧化物半导体（LDMOS）晶体管的方法包括：提供具有LDMOS晶体管区域和VDMOS晶体管区域的衬底; 在所述衬底中形成N掩埋区域; 在N掩埋层区域上形成外延层; 在LDMOS晶体管区域和VDMOS晶体管区域中形成隔离区域; 在LDMOS晶体管区域中形成漂移区; 在LDMOS晶体管区域和VDMOS晶体管区域中形成栅极; 在LDMOS晶体管区域和VDMOS晶体管区域中形成PBODY区域; 在LDMOS晶体管区域中形成N型GRADE区域; 在所述VDMOS晶体管区域中形成NSINK区域，其中所述NSINK区域与所述N埋层区域接触; 在LDMOS晶体管区域和VDMOS晶体管区域中形成源极和漏极; 以及在LDMOS晶体管区域中形成P +区域，其中P +区域与源极接触。

50. 发明授权

US10084036B2 Insulated gate bipolar transistor and manufacturing method therefor 有权
公开(公告)号：US10084036B2
公开(公告)日：2018-09-25
申请号：US15840791
申请日：2017-12-13
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shengrong Zhong , Dongfei Zhou , Xiaoshe Deng , Genyi Wang
IPC分类号： H01L21/338 , H01L21/336 , H01L29/06 , H01L29/16 , H01L21/761 , H01L29/04 , H01L29/161 , H01L29/20 , H01L29/10 , H01L29/739 , H01L29/66
CPC分类号： H01L29/0623 , H01L21/761 , H01L29/045 , H01L29/0619 , H01L29/1095 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/20 , H01L29/66333 , H01L29/6634 , H01L29/7395 , H01L29/7396
摘要： An insulated gate bipolar transistor (100) is provided. A substrate (10) of the insulated gate bipolar transistor (100) is of an N type. A P-type region (16) is disposed on a back of the N-type substrate. A back metal structure (18) is disposed on a back of the P-type region (16). A terminal protection ring is disposed in a terminal structure. A polysilicon gate (31) is disposed on a front surface of the substrate (10) in an active region. Sidewalls (72) are disposed at two sides of the polysilicon gate (31) on the substrate (10). An interlayer medium (81) covered with the polysilicon gate (31) and the sidewalls (72) is disposed on the substrate (10). The interlayer medium (81) is covered with a metal lead wire layer (91). An N-type carrier enhancement region (41) is disposed in the substrate (10) in the active region. A P-type body region (51) is disposed in the carrier enhancement region (41). An N-type heavily doped region (61) is disposed in the P-type body region (51). A P-type heavily doped region (71) is disposed in the N-type heavily doped region (61). An inward recessed shallow pit (62) with a depth of 0.15 to 0.3 micrometers is formed on a surface of the P-type heavily doped region (71). By disposing the carrier enhancement region (41), the carrier concentration of a channel can be increased and a forward voltage drop can be reduced; in addition, the shallow pit (62) can make a device obtain good impurity distribution and a large metal contact area, thereby improving the performance of the device.

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