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41. 发明申请

US20130094271A1 CONNECTION OF MULTIPLE SEMICONDUCTOR MEMORY DEVICES WITH CHIP ENABLE FUNCTION 审中-公开
标题翻译：多芯半导体存储器件与芯片启用功能的连接
公开(公告)号：US20130094271A1
公开(公告)日：2013-04-18
申请号：US13588195
申请日：2012-08-17
申请人： Roland Schuetz
发明人： Roland Schuetz
IPC分类号： G11C5/06
CPC分类号： G11C5/06 , G06F13/4234 , G06F13/4247 , G11C5/066 , G11C7/10 , G11C7/20 , G11C16/08 , G11C2216/30
摘要： A system comprising a plurality of memory devices coupled by a common bus to a controller has a single serially coupled enable signal per channel. Each memory device or chip comprises a serial enable input and enable output and a register for storing a device identifier, e.g., chip ID. The memory devices are serially coupled by a serial enable link, for assertion of a single enable signal to all devices. This parallel data and serial enable configuration provides reduced per-channel pin count, relative to conventional systems that require a unique enable signal for each device. In operation, commands on the common bus targeting an individual device are asserted by adding an address field comprising a device identifier to each command string, preferably in an initial identification cycle of the command. Methods are also disclosed for initializing the system, comprising assigning device identifiers and obtaining a device count, prior to normal operation.
摘要翻译：包括通过公共总线耦合到控制器的多个存储器件的系统具有每个通道的单个串联耦合使能信号。每个存储器件或芯片包括串行使能输入和使能输出以及用于存储器件标识符（例如芯片ID）的寄存器。存储器件通过串行使能链路串联耦合，用于断言所有器件的单个使能信号。相对于需要每个器件的唯一使能信号的传统系统，这种并行数据和串行使能配置提供减少的每通道引脚数。在操作中，通过将优选地在命令的初始识别周期中添加包括设备标识符的地址字段到每个命令串来断言公共总线上针对单个设备的命令被断言。还公开了用于初始化系统的方法，包括在正常操作之前分配设备标识符并获得设备计数。

42. 发明授权

US08412968B2 Circuit, system and method for selectively turning off internal clock drivers 有权
公开(公告)号：US08412968B2
公开(公告)日：2013-04-02
申请号：US12652897
申请日：2010-01-06
申请人： George B. Raad
发明人： George B. Raad
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32 , G06F13/28
CPC分类号： G06F1/3237 , G06F1/04 , G06F1/3203 , G06F1/3225 , G06F1/3234 , G06F1/324 , G06F1/3275 , G11C7/20 , G11C7/22 , G11C7/225 , G11C2207/2227 , Y02D10/128 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： The present invention includes a circuit, system and method for selectively turning off internal clock drivers to reduce operating current. The present invention may be used to reduce power consumption by reducing operating current in a memory device. Operating current may be reduced by turning off internal clock drivers that deliver a clock signal during selected periods of time. According to an embodiment of clock control circuitry of the present invention, an internal clock is disabled if a no operation command is detected during periods of time when no read or write burst operation is taking place. Methods, memory devices and computer systems including the clock control circuitry and its functionality are also disclosed.

43. 发明授权

US08406070B2 Single-strobe operation of memory devices 有权
标题翻译：存储器件的单次选通操作
公开(公告)号：US08406070B2
公开(公告)日：2013-03-26
申请号：US12984987
申请日：2011-01-05
申请人： Roland Schuetz , Jin-Ki Kim
发明人： Roland Schuetz , Jin-Ki Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093
摘要： An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted on the data bus followed by a payload, includes an encoded indication of the type of the payload. Aspects of the present application relate to providing a traditional memory device with external logic devices, where the logic devices handle the single strobe and the packet header, thereby permitting single strobe operation.
摘要翻译：存储器件和控制器的布置基于相对于已知的存储器件和控制器布置具有减少的引脚数的接口。便利减少引脚数接口，将多个选通信号降低到单个选通信号。此外，在数据总线上发送的分组报头后跟有效载荷，包括有效载荷的类型的编码指示。本申请的方面涉及向传统的存储设备提供外部逻辑设备，其中逻辑设备处理单个选通和分组报头，从而允许单次选通操作。

44. 发明申请

US20130046921A1 METHOD OF CONFIGURING NON-VOLATILE MEMORY FOR A HYBRID DISK DRIVE 有权
标题翻译：配置混合磁盘驱动器的非易失性存储器的方法
公开(公告)号：US20130046921A1
公开(公告)日：2013-02-21
申请号：US13655582
申请日：2012-10-19
申请人： MOSAID Technologies Incorporated
发明人： Hong Beom PYEON
IPC分类号： G06F12/00
CPC分类号： G06F3/0664 , G06F3/061 , G06F3/0625 , G06F3/068 , G06F9/4408 , G06F12/0868 , G06F2212/217 , Y02D10/13 , Y02D10/154
摘要： A system, method and machine-readable medium are provided to configure a non-volatile memory (NVM) including a plurality of NVM modules, in a system having a hard disk drive (HDD) and an operating system (O/S). In response to a user selection of a hybrid drive mode for the NVM, the plurality of NVM modules are ranked according to speed performance. Boot portions of the O/S are copied to a highly ranked NVM module, or a plurality of highly ranked NVM modules, and the HDD and the highly ranked NVM modules are assigned as a logical hybrid drive of the computer system. Ranking each of the plurality of NVM modules can include carrying out a speed performance test. This approach can provide hybrid disk performance using conventional hardware, or enhance performance of an existing hybrid drive, while taking into account relative performance of available NVM modules.
摘要翻译：在具有硬盘驱动器（HDD）和操作系统（O / S）的系统中，提供了一种系统，方法和机器可读介质来配置包括多个NVM模块的非易失性存储器（NVM）。响应于用户选择NVM的混合驱动模式，根据速度性能对多个NVM模块进行排序。 O / S的引导部分被复制到高排名的NVM模块或多个高排名的NVM模块，并且HDD和高排名的NVM模块被分配为计算机系统的逻辑混合驱动器。对多个NVM模块中的每一个进行排序可以包括进行速度性能测试。这种方法可以使用常规硬件提供混合磁盘性能，或提高现有混合驱动器的性能，同时考虑可用的NVM模块的相对性能。

45. 发明申请

US20130039125A1 FLASH MEMORY PROGRAM INHIBIT SCHEME 审中-公开
公开(公告)号：US20130039125A1
公开(公告)日：2013-02-14
申请号：US13652947
申请日：2012-10-16
申请人： Jin-Ki KIM
发明人： Jin-Ki KIM
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/24 , G11C16/3418 , G11C16/3427
摘要： A method for minimizing program disturb in Flash memories. To reduce program disturb in a NAND Flash memory cell string where no programming from the erased state is desired, a local boosted channel inhibit scheme is used. In the local boosted channel inhibit scheme, the selected memory cell in a NAND string where no programming is desired, is decoupled from the other cells in the NAND string. This allows the channel of the decoupled cell to be locally boosted to a voltage level sufficient for inhibiting F-N tunneling when the corresponding wordline is raised to a programming voltage. Due to the high boosting efficiency, the pass voltage applied to the gates of the remaining memory cells in the NAND string can be reduced relative to prior art schemes, thereby minimizing program disturb while allowing for random page programming.

46. 发明申请

US20130033929A1 WRITE SCHEME IN A PHASE CHANGE MEMORY 审中-公开
标题翻译：相变记忆中的写入方案
公开(公告)号：US20130033929A1
公开(公告)日：2013-02-07
申请号：US13636547
申请日：2011-04-26
申请人： Jin-Ki Kim
发明人： Jin-Ki Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/0035 , G11C13/0061 , G11C13/0064 , G11C2013/0054 , G11C2013/0076 , G11C2013/0088 , G11C2213/72
摘要： In a phase change memory, an input data corresponding to a plurality of memory cells is received and a previous data is read from the plurality of memory cells. The input data is compared with the previous data. In the case where the input data is different from the previous data for one or more of the plurality of memory cells and a write count is less than a maximum value, one or more of the plurality of memory cells is programmed with the input data and the write count is updated or incremented. Such operations of data comparison and update of the write count are repeated. If the write count reaches the maximum value, it will be determined that the writing is failed.
摘要翻译：在相变存储器中，接收与多个存储单元相对应的输入数据，并从多个存储单元读取先前的数据。将输入数据与先前的数据进行比较。在输入数据与多个存储单元中的一个或多个的先前数据不同且写入数小于最大值的情况下，多个存储器单元中的一个或多个用输入数据编程，并且写入计数更新或增加。重复数据比较和更新写入次数的这种操作。如果写入计数达到最大值，则确定写入失败。

47. 发明授权

US08359485B2 Non-volatile semiconductor memory device with power saving feature 有权
标题翻译：具有省电功能的非易失性半导体存储器件
公开(公告)号：US08359485B2
公开(公告)日：2013-01-22
申请号：US13408252
申请日：2012-02-29
申请人： HakJune Oh
发明人： HakJune Oh
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3275 , G11C16/16 , G11C16/32 , Y02D10/14
摘要： A non-volatile semiconductor memory device, which comprises (i) an interface having an input for receiving an input clock and a set of data lines for receiving commands issued by a controller including an erase command; (ii) a module having circuit components in a feedback loop configuration and being driven by a reference clock; (iii) a clock control circuit capable of controllably switching between a first state in which the reference clock tracks the input clock and a second state in which the reference clock is decoupled from the input clock; and (iv) a command processing unit configured to recognize the commands and to cause the clock control circuit to switch from the first state to the second state in response to recognizing the erase command. The module consumes less power when the reference clock is decoupled from the input clock than when the reference clock tracks the input clock.
摘要翻译：一种非易失性半导体存储器件，其包括（i）具有用于接收输入时钟的输入的接口和用于接收由包括擦除命令的控制器发出的命令的一组数据线; （ii）具有反馈回路配置并由参考时钟驱动的电路部件的模块; （iii）时钟控制电路，其能够可控地在其中参考时钟跟踪输入时钟的第一状态和参考时钟与输入时钟去耦的第二状态之间切换; 以及（iv）命令处理单元，被配置为响应于识别所述擦除命令，识别所述命令并使所述时钟控制电路从所述第一状态切换到所述第二状态。当参考时钟与输入时钟去耦时，该模块消耗的功率要小于参考时钟跟踪输入时钟时的功耗。

48. 发明申请

US20130010538A1 MEMORY DEVICE AND METHOD FOR REPAIRING A SEMICONDUCTOR MEMORY 失效
公开(公告)号：US20130010538A1
公开(公告)日：2013-01-10
申请号：US13614573
申请日：2012-09-13
申请人： Greg A. Blodgett
发明人： Greg A. Blodgett
IPC分类号： G11C29/00 , G11C16/06
CPC分类号： G11C29/808 , G11C29/846
摘要： A block repair device is used in a Dynamic Random Access Memory (DRAM) having a primary array with a defective cell and a redundant array with a redundant row. The block repair device stores a block repair configuration that determines the dimensions (e.g., the number of rows and columns spanned) of a repair block. Routing circuitry is configured by the stored block repair configuration to output some row and column address bits from received row and column addresses in a selected ratio. Comparison circuitry compares the row and column address bits output by the routing circuitry with the address of the defective cell that defines the repair block. When a match occurs, the comparison circuitry implements a block repair by activating the redundant row and by causing data to be written to or read from the activated redundant row instead of the primary array.

49. 发明申请

US20130003483A1 WIDE FREQUENCY RANGE DELAY LOCKED LOOP 有权
标题翻译：宽频范围延迟锁定环
公开(公告)号：US20130003483A1
公开(公告)日：2013-01-03
申请号：US13523406
申请日：2012-06-14
申请人： Peter Vlasenko , Dieter Haerle
发明人： Peter Vlasenko , Dieter Haerle
IPC分类号： H03L7/08 , G11C8/00
CPC分类号： H03L7/081 , H03L7/0814 , H03L7/0818 , H03L7/0891 , H03L7/095 , H03L7/10
摘要： A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.
摘要翻译：延迟锁定环路在宽频率范围内工作，具有高精度，小面积使用，低功耗和短锁定时间。该DLL结合了模拟域和数字域。数字域负责初始锁定和操作点稳定性，并在达到锁定后冻结。模拟域在达到锁定后负责正常运行，并使用较小的硅面积和低功耗提供高精度。

50. 发明授权

US08300468B2 Flash memory program inhibit scheme 有权
标题翻译：闪存程序禁止方案
公开(公告)号：US08300468B2
公开(公告)日：2012-10-30
申请号：US13208732
申请日：2011-08-12
申请人： Jin-Ki Kim
发明人： Jin-Ki Kim
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/24 , G11C16/3418 , G11C16/3427
摘要： A method for minimizing program disturb in Flash memories. To reduce program disturb in a NAND Flash memory cell string where no programming from the erased state is desired, a local boosted channel inhibit scheme is used. In the local boosted channel inhibit scheme, the selected memory cell in a NAND string where no programming is desired, is decoupled from the other cells in the NAND string. This allows the channel of the decoupled cell to be locally boosted to a voltage level sufficient for inhibiting F-N tunneling when the corresponding wordline is raised to a programming voltage. Due to the high boosting efficiency, the pass voltage applied to the gates of the remaining memory cells in the NAND string can be reduced relative to prior art schemes, thereby minimizing program disturb while allowing for random page programming.
摘要翻译：一种用于最小化闪存中程序干扰的方法。为了减少在不需要擦除状态的编程的NAND闪存单元串中的程序干扰，使用局部增强的通道抑制方案。在本地提升通道禁止方案中，在NAND串中未选择编程的NAND串中选择的存储单元与NAND串中的其它单元解耦。这使得解耦单元的通道在相应的字线升高到编程电压时被局部提升到足以抑制F-N隧穿的电压电平。由于高的提升效率，相对于现有技术的方案，可以减少施加到NAND串中的剩余存储单元的栅极的通过电压，从而最小化程序干扰同时允许随机页面编程。

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