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51. 发明授权

US09442230B2 Sub-wavelength extreme ultraviolet metal transmission grating and manufacturing method thereof 有权
标题翻译：亚波长极紫外金属透射光栅及其制造方法
公开(公告)号：US09442230B2
公开(公告)日：2016-09-13
申请号：US14144222
申请日：2013-12-30
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Hailiang Li , Changqing Xie , Ming Liu , Dongmei Li , Lina Shi , Xiaoli Zhu
IPC分类号： G06K7/10 , G02B5/18 , G03F7/075 , G03F7/20 , G03F7/40
CPC分类号： G02B5/1871 , G02B5/1809 , G02B5/1838 , G02B5/1857 , G02B2005/1804 , G03F7/0757 , G03F7/2059 , G03F7/40
摘要： A method of manufacturing a sub-wavelength extreme ultraviolet metal transmission grating is disclosed. In one aspect, the method comprises forming a silicon nitride self-supporting film window on a back surface of a silicon-based substrate having both surfaces polished, then spin-coating a silicon nitride film on a front surface of the substrate with an electron beam resist HSQ. Then, performing electron beam direct writing exposure on the HSQ, developing and fixing to form a plurality of grating line patterns and a ring pattern surrounding the grating line patterns. Then depositing a chrome material on the front surface of the substrate through magnetron sputtering. Then, removing the chrome material inside the ring pattern. Then, growing a gold material on the front surface of the substrate through atomic layer deposition. Lastly, removing the gold material on the chrome material outside the ring pattern as well as on and between the grating line patterns, thereby only retaining the gold material on sidewalls of the grating line patterns.
摘要翻译：公开了一种制造亚波长极紫外金属透射光栅的方法。在一个方面，该方法包括在硅衬底的背表面上形成氮化硅自支撑膜窗，其两面被抛光，然后用电子束在衬底的前表面上旋涂氮化硅膜抵制HSQ。然后，在HSQ上执行电子束直接写入曝光，显影和固定以形成围绕光栅线图案的多个光栅线图案和环形图案。然后通过磁控溅射在基板的前表面上沉积铬材料。然后，移除环形图案内的铬材料。然后，通过原子层沉积在基板的前表面上生长金材料。最后，除去环形图案之外的铬材料上的金材料以及光栅线图案之间和之间的金材料，从而仅将金材料保留在光栅线图案的侧壁上。

52. 发明授权

US09419112B2 Method for manufacturing fin structure 有权
标题翻译：制造翅片结构的方法
公开(公告)号：US09419112B2
公开(公告)日：2016-08-16
申请号：US14647360
申请日：2012-12-17
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Huilong Zhu , Jun Luo , Chunlong Li
IPC分类号： H01L21/265 , H01L21/306 , H01L29/66 , H01L29/78 , H01L21/3105 , H01L21/321 , H01L29/10 , H01L29/16 , H01L29/165
CPC分类号： H01L29/6681 , H01L21/265 , H01L21/30604 , H01L21/3086 , H01L21/31053 , H01L21/32115 , H01L29/1083 , H01L29/16 , H01L29/165 , H01L29/6656 , H01L29/66795 , H01L29/66803 , H01L29/7848 , H01L29/7851
摘要： A method for manufacturing a fin structure is provided. A method according to an embodiment may include: forming a patterned pattern transfer layer on a substrate; forming a first spacer on sidewalls of the pattern transfer layer; forming a second spacer on sidewalls of the first spacer; selectively removing the pattern transfer layer and the first spacer; and patterning the substrate with the second spacer as a mask, so as to form an initial fin.
摘要翻译：提供一种制造翅片结构的方法。根据实施例的方法可以包括：在衬底上形成图案化图案转移层; 在所述图案转移层的侧壁上形成第一间隔物; 在所述第一间隔件的侧壁上形成第二间隔件; 选择性地去除图案转印层和第一间隔物; 并用第二间隔物作为掩模图案化衬底，以形成初始鳍。

53. 发明授权

US09418843B2 Method for manufacturing ordered nanowire array of NiO doped with Pt in situ 有权
标题翻译：用于原位掺杂Pt的NiO有序纳米线阵列的制备方法
公开(公告)号：US09418843B2
公开(公告)日：2016-08-16
申请号：US14760890
申请日：2013-01-17
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Dongmei Li , Xin Chen , Shengfa Liang , Jiebin Niu , Peiwen Zhang , Yu Liu , Xiaojing Li , Shuang Zhan , Hao Zhang , Qing Luo , Changqing Xie , Ming Liu
IPC分类号： H01L21/00 , H01L21/02 , H01L21/465 , G01N33/00 , B82Y10/00 , B82Y40/00
CPC分类号： H01L21/02565 , B82Y10/00 , B82Y40/00 , G01N33/004 , G01N33/005 , H01L21/02422 , H01L21/02581 , H01L21/02603 , H01L21/02614 , H01L21/465 , Y02A50/243
摘要： The present disclosure provides a method for manufacturing ordered nanowires array of NiO doped with Pt in situ, comprising: growing a Ni layer on a high-temperature resistant and insulated substrate; applying a photoresist on the Ni layer, pattering a pattern region of the ordered nanowires array by applying electron beam etching on the photoresist, growing Ni on the pattern region of the ordered nanowires array, peeling off the photoresist by acetone and etching the surface of the Ni layer by ion beam etching so as to etch off the Ni layer grown on the surface of the substrate and to leave the Ni on the pattern region of the ordered nanowires array to form the ordered Ni nanowires array; dipping the ordered Ni nanowires array into a solution of H2PtCl6 so as to displace Pt on the Ni nanowires array by a displacement reaction; and oxidizing the Ni nanowires array attached with Pt in an oxidation oven to obtain the ordered nanowires array of NiO doped with Pt. The present invention is simple and practical and the sensitivity and reliability of the doped sensor on the gas of CO and H2 are greatly improved.
摘要翻译：本公开提供了一种用于制造原位掺杂有Pt的NiO的有序纳米线阵列的方法，包括：在耐高温和绝缘的衬底上生长Ni层; 在Ni层上施加光致抗蚀剂，通过在光致抗蚀剂上施加电子束蚀刻来图案化有序纳米线阵列的图案区域，在有序纳米线阵列的图案区域上生长Ni，用丙酮剥离光致抗蚀剂并蚀刻 Ni层，以便蚀刻生长在衬底表面上的Ni层，并将Ni留在有序纳米线阵列的图案区上以形成有序的Ni纳米线阵列; 将有序的Ni纳米线阵列浸入H2PtCl6溶液中，通过置换反应置换Ni纳米线阵列上的Pt; 并在氧化炉中氧化附着有Pt的Ni纳米线阵列，以获得掺杂有Pt的NiO的有序纳米线阵列。本发明简单实用，掺杂传感器对CO和H2气体的灵敏度和可靠性大大提高。

54. 发明授权

US09418835B2 Methods for manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09418835B2
公开(公告)日：2016-08-16
申请号：US14662963
申请日：2015-03-19
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Guilei Wang , Jinbiao Liu , Junfeng Li
IPC分类号： H01L21/02 , H01L21/265
CPC分类号： H01L21/0217 , H01L21/02211 , H01L21/02274 , H01L21/02312 , H01L21/02329 , H01L21/0234 , H01L21/265
摘要： The present disclosure provides a method of manufacturing a semiconductor device having silicon nitride with a tensile stress, the method comprising: c1) introducing and pre-stabilizing NH3 gas and N2 gas; c2) introducing silane; c3) igniting the gases by a radio-frequency source; c4) depositing SiN; and c5) processing the SiN by using a nitrogen ion implantation. According to the present disclosure, the nitrogen content in the SiN film can be enhanced by the nitrogen ion implantation and impinging, thereby increasing the density of the film. In this way, the acid resistance of the SiN with tensile stress is enhanced, so that the SiN with tensile stress may be integrated in a dual-strained liner of a gate-last process, so as to effectively improve the properties and reliability of the device.
摘要翻译：本公开提供一种制造具有拉伸应力的氮化硅的半导体器件的方法，所述方法包括：c1）引入和预稳定NH 3气体和N 2气体; c2）引入硅烷; c3）用射频源点燃气体; c4）沉积SiN; 和c5）通过使用氮离子注入来处理SiN。根据本公开，通过氮离子注入和冲击，可以提高SiN膜中的氮含量，从而提高膜的密度。以这种方式，具有拉伸应力的SiN的耐酸性得到提高，使得具有拉伸应力的SiN可以集成在最后工艺的双应变衬里中，从而有效地提高了最终工艺的性能和可靠性设备。

55. 发明授权

US09401425B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09401425B2
公开(公告)日：2016-07-26
申请号：US14437755
申请日：2012-11-27
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L29/78 , H01L29/10 , H01L21/8234 , H01L29/66 , H01L29/06 , H01L21/02 , H01L21/306 , H01L21/308 , H01L21/762 , H01L29/16 , H01L29/161 , H01L29/165
CPC分类号： H01L29/7848 , H01L21/02381 , H01L21/02529 , H01L21/02532 , H01L21/30604 , H01L21/308 , H01L21/3086 , H01L21/762 , H01L21/76224 , H01L21/823412 , H01L21/823425 , H01L21/823481 , H01L29/0653 , H01L29/1054 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/6656 , H01L29/66628 , H01L29/66636
摘要： A semiconductor structure is disclosed. The semiconductor structure comprises: a substrate (130), a support structure (131), a base region (100), a gate stack, a spacer (240), and a source/drain region, wherein the gate stack is located on the base region (100), and the base region (100) is supported on the substrate (130) by the support structure (131), wherein the sidewall cross-section of the support structure (131) is in a shape of a concave curve; an isolation structure (123) is formed beneath the edges on both sides of the base region (100), wherein a portion of the isolation structure (123) is connected to the substrate (130); a cavity (112) is formed between the isolation structure (123) and the support structure (131); and there exists a source/drain region at least on both sides of the base region (100) and the isolation structure (123). Accordingly, a method for manufacturing the semiconductor structure is also disclosed.
摘要翻译：公开了半导体结构。半导体结构包括：衬底（130），支撑结构（131），基极区（100），栅极堆叠，间隔物（240）和源极/漏极区，其中栅极堆叠位于基部区域（100），并且所述基部区域（100）由所述支撑结构（131）支撑在所述基板（130）上，其中所述支撑结构（131）的侧壁横截面为凹曲线 ; 隔离结构（123）形成在基部区域（100）的两侧的边缘之下，其中隔离结构（123）的一部分连接到基板（130）; 在隔离结构（123）和支撑结构（131）之间形成空腔（112）; 并且至少在基极区域（100）和隔离结构（123）的两侧存在源极/漏极区域。因此，还公开了一种用于制造半导体结构的方法。

56. 发明授权

US09397104B2 SRAM cell and method for manufacturing the same 有权
标题翻译： SRAM单元及其制造方法
公开(公告)号：US09397104B2
公开(公告)日：2016-07-19
申请号：US13509891
申请日：2011-11-23
申请人： Huilong Zhu , Qingqing Liang
发明人： Huilong Zhu , Qingqing Liang
IPC分类号： H01L21/70 , H01L27/11 , H01L21/84 , H01L27/12
CPC分类号： H01L27/1104 , H01L21/845 , H01L27/1211
摘要： In one embodiment, a SRAM cell may include a substrate and a first Fin Field Effect Transistor (FinFET) and a second FinFET formed on the substrate. The first FinFET may include a first fin which is formed in a semiconductor layer provided on the substrate and abuts the semiconductor layer, and the second FinFET may include a second fin which is formed in the semiconductor layer and abuts the semiconductor layer. The semiconductor layer may include a plurality of semiconductor sub-layers. The first and second fins can include different number of the semiconductor sub-layers and have different heights from each other.
摘要翻译：在一个实施例中，SRAM单元可以包括衬底和形成在衬底上的第一Fin场效应晶体管（FinFET）和第二FinFET。第一FinFET可以包括形成在衬底上的半导体层中，并与该半导体层相邻的第一鳍片，并且第二鳍片FET可以包括形成在半导体层中并邻接半导体层的第二鳍片。半导体层可以包括多个半导体子层。第一和第二散热片可以包括不同数量的半导体子层，并且彼此具有不同的高度。

57. 发明申请

US20160204199A1 MOSFET STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
标题翻译： MOSFET结构及其制造方法
公开(公告)号：US20160204199A1
公开(公告)日：2016-07-14
申请号：US14904871
申请日：2013-10-22
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Haizhou Yin
IPC分类号： H01L29/10 , H01L29/161 , H01L29/66 , H01L29/78 , H01L29/49 , H01L29/08 , H01L29/165
CPC分类号： H01L29/1033 , H01L29/0847 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/66492 , H01L29/6653 , H01L29/66545 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A MOSFET structure and a method for manufacturing the same are disclosed. The method comprises: a. providing a substrate (100); b. forming a silicon germanium channel layer (101), a dummy gate structure (200) and a sacrificial spacer (102); c. removing the silicon germanium channel layer and portions of the substrate which are not covered by the dummy gate structure (200) and located under both sides of the dummy gate structure 200, so as to form vacancies (201); d. selectively epitaxially growing a first semiconductor layer (300) on the semiconductor structure to fill bottom and sidewalls of the vacancies (201); and e. removing the sacrificial spacer (102) and filling a second semiconductor layer (400) in the vacancies which are not filled by the first semiconductor layer (300). In the semiconductor structure of the present disclosure, carrier mobility in the channel can be increased, negative effects induced by the short channel effects can be suppressed, and device performance can be enhanced.
摘要翻译：公开了一种MOSFET结构及其制造方法。该方法包括：a。提供衬底（100）; b。形成硅锗沟道层（101），伪栅极结构（200）和牺牲间隔物（102）; C。去除未被所述虚拟栅极结构（200）覆盖并位于所述虚拟栅极结构200的两侧的所述硅锗沟道层和所述衬底的部分，以形成空位（201）; d。在所述半导体结构上选择性地外延生长第一半导体层（300）以填充所述空位（201）的底部和侧壁; 和e。去除所述牺牲间隔物（102）并在未被所述第一半导体层（300）填充的空位中填充第二半导体层（400）。在本公开的半导体结构中，可以增加通道中的载流子迁移率，可以抑制由短通道效应引起的负面影响，并且可以提高器件性能。

58. 发明授权

US09379056B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09379056B2
公开(公告)日：2016-06-28
申请号：US14423020
申请日：2012-09-17
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Huicai Zhong , Qingqing Liang
IPC分类号： H01L21/311 , H01L21/3213 , H01L23/528 , H01L21/768 , H01L23/532
CPC分类号： H01L23/528 , H01L21/31111 , H01L21/32133 , H01L21/76802 , H01L21/76831 , H01L21/76838 , H01L21/76841 , H01L21/76877 , H01L21/76892 , H01L23/53209 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for manufacturing a semiconductor structure, comprising: a) forming metal interconnect liners on a substrate; b) forming a mask layer to cover the metal interconnect liners and forming openings, which expose the metal interconnect liners, on the mask layer; c) etching and disconnecting the metal interconnect liners via the openings, thereby insulating and isolating the metal interconnect liners. The present invention further provides a semiconductor structure, which comprises a substrate and metal interconnect liners, wherein ends of the metal interconnect liners are disconnected by insulating walls formed within the substrate. The structure and the method provided by the present invention are favorable for shortening distance between ends of adjacent metal interconnect liners, saving device area and suppressing short circuits happening to metal interconnect liners.
摘要翻译：本发明提供一种制造半导体结构的方法，包括：a）在衬底上形成金属互连衬垫; b）形成掩模层以覆盖金属互连衬里并在掩模层上形成露出金属互连衬套的开口; c）经由开口蚀刻和断开金属互连衬套，由此绝缘和隔离金属互连衬套。本发明还提供一种半导体结构，其包括衬底和金属互连衬套，其中金属互连衬里的端部通过在衬底内形成的绝缘壁而断开。本发明提供的结构和方法有利于缩短相邻金属互连衬套的端部之间的距离，节省器件面积并抑制金属互连衬套发生的短路。

59. 发明授权

US09373622B2 CMOS device with improved accuracy of threshold voltage adjustment and method for manufacturing the same 有权
标题翻译：具有提高阈值电压调整精度的CMOS器件及其制造方法
公开(公告)号：US09373622B2
公开(公告)日：2016-06-21
申请号：US14721386
申请日：2015-05-26
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Huaxiang Yin , Hong Yang , Qingzhu Zhang , Qiuxia Xu
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L27/092 , H01L21/823821 , H01L21/823828 , H01L21/823842 , H01L27/0924
摘要： An CMOS device comprises a plurality of NMOS transistors and a plurality of PMOS transistors, each of which comprises a gate stack constituted of a gate insulating layer and a gate metal layer on a substrate, a source/drain region in the substrate on both sides of the gate stack and a channel region below the gate stack, wherein the gate metal layer of each NMOS transistor comprising a first barrier layer, an NMOS work function adjusting layer, a second barrier layer, and a filling layer, and wherein the gate metal layer of each PMOS transistor comprising a first barrier layer, a PMOS work function adjusting layer, an NMOS work function adjusting layer, a second barrier layer, and a filling layer, and wherein the first barrier layer in the gate metal layer of the NMOS transistor and the first barrier layer in the gate metal layer of the PMOS transistor contain a doping ion to finely adjust the work function. The semiconductor device and the method for manufacturing the same according to the present disclosure utilize the sacrificial layer to diffuse impurity to the barrier layer so that the adjusting accuracy of the threshold voltage may be effectively improved, thereby facilitating in improving the whole performance of the device.
摘要翻译： CMOS器件包括多个NMOS晶体管和多个PMOS晶体管，每个PMOS晶体管包括由衬底上的栅极绝缘层和栅极金属层构成的栅极堆叠，在衬底的两侧的衬底中的源极/漏极区域栅极堆叠和栅极堆叠下方的沟道区，其中每个NMOS晶体管的栅极金属层包括第一势垒层，NMOS功函数调节层，第二势垒层和填充层，并且其中栅极金属层每个PMOS晶体管包括第一阻挡层，PMOS功函数调整层，NMOS功函数调整层，第二势垒层和填充层，并且其中NMOS晶体管的栅极金属层中的第一势垒层和 PMOS晶体管的栅极金属层中的第一势垒层含有掺杂离子以微调功函数。根据本公开的半导体器件及其制造方法利用牺牲层将杂质扩散到阻挡层，从而可以有效地提高阈值电压的调整精度，从而有助于提高器件的整体性能。

60. 发明授权

US09350380B2 Sigma-delta modulator and analog-to-digital converter 有权
标题翻译： Σ-Δ调制器和模数转换器
公开(公告)号：US09350380B2
公开(公告)日：2016-05-24
申请号：US14425095
申请日：2013-02-28
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Lan Chen
IPC分类号： H03M3/00 , H03M1/00
CPC分类号： H03M3/324 , H03M1/002 , H03M3/38 , H03M3/424 , H03M3/438 , H03M3/50
摘要： A Sigma-Delta modulator and an analog-to-digital converter. The Sigma-Delta modulator comprises a quantizer, a correction module and an RC integrator. The correction module comprises a predetermined resistance through which a correction level is generated. The correction module is used to compare the correction level with a predetermined reference voltage by using a comparator in the quantizer, so as to generate a digital correction signal, based on which the resistance in a resistance correction array in the RC integrator is corrected. The predetermined resistance is of the same type as the resistance in the resistance correction array in the RC integrator. The Sigma-Delta modulator and the analog-to-digital converter can correct the resistance deviation in the RC integrator.
摘要翻译： Σ-Δ调制器和模数转换器。 Sigma-Delta调制器包括量化器，校正模块和RC积分器。校正模块包括产生校正水平的预定电阻。校正模块用于通过使用量化器中的比较器将校正电平与预定参考电压进行比较，以产生数字校正信号，基于该校正信号校正RC积分器中的电阻校正阵列中的电阻。预定电阻与RC积分器中的电阻校正阵列中的电阻相同。 Sigma-Delta调制器和模数转换器可以校正RC积分器中的电阻偏差。

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