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51. 发明授权

US5418750A Semiconductor memory device for suppressing noises occurring on bit and word lines 失效
标题翻译：用于抑制位和字线上发生的噪声的半导体存储器件
公开(公告)号：US5418750A
公开(公告)日：1995-05-23
申请号：US200107
申请日：1994-02-22
申请人： Shinichiro Shiratake , Takehiro Hasegawa , Daisaburo Takashima , Ryu Ogiwara , Ryo Fukuda
发明人： Shinichiro Shiratake , Takehiro Hasegawa , Daisaburo Takashima , Ryu Ogiwara , Ryo Fukuda
IPC分类号： G11C11/407 , G11C11/405 , G11C11/4091 , G11C11/4096 , G11C11/4097 , G11C7/00
CPC分类号： G11C11/4096 , G11C11/4091 , G11C11/4097
摘要： A semiconductor memory device includes a series of memory cells, a series of bit lines respectively connected to the memory cells, a series of sense amplifiers, connected to corresponding bit line groups including predetermined number of bit lines of the series of bit lines, for reading out data of memory cells connected to bit lines of the bit line group, the bit line groups including at least adjacent first and second bit line groups, at least first and second transistors allocated between the bit lines and the sense amplifiers and having gates, for selectively connecting the bit lines and the sense amplifiers, and a series of control signal lines commonly connected to the first transistors connected to the first bit line groups and the second transistors connected to the second bit line groups, such that the first transistors connected to the first bit line groups are regularly arranged in one direction, and second transistors connected to the second bit line groups adjacent to the first bit line groups are regularly arranged in an opposite direction.
摘要翻译：半导体存储器件包括一系列存储器单元，分别连接到存储器单元的一系列位线，一系列读出放大器，连接到包括一系列位线的预定数量位线的相应位线组，用于读取连接到位线组的位线的存储器单元的输出数据，位线组包括至少相邻的第一和第二位线组，分配在位线和读出放大器之间并具有门的至少第一和第二晶体管，用于选择性地连接位线和读出放大器，以及一系列控制信号线，共同连接到连接到第一位线组的第一晶体管和连接到第二位线组的第二晶体管，使得连接到第一位线组的第一晶体管第一位线组在一个方向上规则地排列，第二晶体管连接到第二位线组第一位线组以相反的方向规则地布置。

52. 发明授权

US08558602B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08558602B2
公开(公告)日：2013-10-15
申请号：US12884533
申请日：2010-09-17
申请人： Ryo Fukuda , Masaru Koyanagi
发明人： Ryo Fukuda , Masaru Koyanagi
IPC分类号： H03L5/00
CPC分类号： H03K3/356113
摘要： According to one embodiment, a semiconductor integrated circuit includes first and second level shift circuits. The first level shifter includes a plurality of transistors and is connected to a power source voltage supply node of a first power source system and to which a first signal of a second power source system and a level inversion signal of the first signal are input. The second level shifter includes a plurality of transistors and is connected to the power source voltage supply node of the first power source system and to which the level inversion signal of the first signal of the second power source system and an output signal of the first level shifter are input. The first and second level shifters have substantially the same circuit configuration and driving abilities of corresponding ones of the transistors in the first and second level shifters are substantially set equal.
摘要翻译：根据一个实施例，半导体集成电路包括第一和第二电平移位电路。第一电平移位器包括多个晶体管，并连接到第一电源系统的电源电压供应节点，第二电源系统的第一信号和第一信号的电平反转信号被输入到该第一电源系统。第二电平移位器包括多个晶体管，并连接到第一电源系统的电源电压供应节点，并且第二电源系统的第一信号的电平反转信号和第一电平系统的输出信号移位器被输入。第一和第二电平移位器具有基本上相同的电路配置，并且第一和第二电平移位器中对应的晶体管的驱动能力基本上相等。

53. 发明授权

US08502300B2 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US08502300B2
公开(公告)日：2013-08-06
申请号：US13232492
申请日：2011-09-14
申请人： Ryo Fukuda , Yoshihisa Iwata
发明人： Ryo Fukuda , Yoshihisa Iwata
IPC分类号： H01L29/792
CPC分类号： H01L27/11578 , G11C16/0416 , H01L27/11565 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： An dielectric film is formed above the semiconductor substrate. A first conductive layer is formed in the dielectric film and extending in a first direction. The first conductive layer is connected to a first select transistor. A second conductive layer formed in the dielectric film and extending in the first direction. The second conductive layer is connected to a second select transistor. A semiconductor layer is connected to both the first and second conductive layers and functioning as a channel layer of a memory transistor. A gate-insulating film is formed on the semiconductor layer. The gate-insulating film includes a charge accumulation film as a portion thereof. A third conductive layer is surrounded by the gate-insulating film.
摘要翻译：在半导体衬底上方形成绝缘膜。在电介质膜中形成第一导电层并沿第一方向延伸。第一导电层连接到第一选择晶体管。形成在电介质膜中并沿第一方向延伸的第二导电层。第二导电层连接到第二选择晶体管。半导体层连接到第一和第二导电层两者并用作存储晶体管的沟道层。在半导体层上形成栅极绝缘膜。栅极绝缘膜包括作为其一部分的电荷累积膜。第三导电层被栅极绝缘膜包围。

54. 发明授权

US08027216B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08027216B2
公开(公告)日：2011-09-27
申请号：US12550663
申请日：2009-08-31
申请人： Ryo Fukuda , Yohji Watanabe
发明人： Ryo Fukuda , Yohji Watanabe
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C8/04 , G11C11/406 , G11C11/40615 , G11C2211/4016 , G11C2211/4067
摘要： A memory may includes: word lines; bit lines; memory array blocks including memory cells, each memory array block being a unit of a data read operation or a data write operation; a row decoder configured to selectively drive the word lines; sense amplifiers configured to detect data; and an access counter provided for each memory cell block, the access counter counting the number of times of accessing the memory array blocks in order to read data or write data, and activating a refresh request signal when the number of times of access reaches a predetermined number of times, wherein during an activation period of the refresh request signal of the access counter, the row decoder periodically and sequentially activates the word lines of the memory array blocks corresponding to the access counter, and the sense amplifier performs a refresh operation of the memory cells connected to the activated word lines.
摘要翻译：存储器可以包括：字线; 位线存储器阵列块，包括存储器单元，每个存储器阵列块是数据读取操作或数据写入操作的单元; 行解码器，被配置为选择性地驱动所述字线; 配置成检测数据的感测放大器; 以及为每个存储器单元块提供的访问计数器，所述访问计数器对访问所述存储器阵列块的次数进行计数，以便读取数据或写入数据，以及当所述访问次数达到预定的次数时激活刷新请求信号次数，其中在访问计数器的刷新请求信号的激活周期期间，行解码器周期性地并且顺序地激活对应于访问计数器的存储器阵列块的字线，并且读出放大器执行刷新操作存储单元连接到激活的字线。

55. 发明授权

US07995369B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07995369B2
公开(公告)日：2011-08-09
申请号：US12332595
申请日：2008-12-11
申请人： Yoshihiro Minami , Ryo Fukuda , Takeshi Hamamoto
发明人： Yoshihiro Minami , Ryo Fukuda , Takeshi Hamamoto
IPC分类号： G11C17/00
CPC分类号： H01L27/101 , H01L27/1021 , H01L27/112 , H01L27/1203
摘要： This disclosure concerns a semiconductor memory device including bit lines; word lines; semiconductor layers arranged to correspond to crosspoints of the bit lines and the word lines; bit line contacts connecting between a first surface region and the bit lines, the first surface region being a part of a surface region of the semiconductor layers directed to the word lines and the bit lines; and a word-line insulating film formed on a second surface region adjacent to the first surface region, the second surface region being a part of out of the surface region, the word-line insulating film electrically insulating the semiconductor layer and the word line, wherein the semiconductor layer, the word line and the word-line insulating film form a capacitor, and when a potential difference is given between the word line and the bit line, the word-line insulating film is broken in order to store data.
摘要翻译：本公开涉及包括位线的半导体存储器件; 字线布置成对应于位线和字线的交叉点的半导体层; 连接在第一表面区域和位线之间的位线触点，第一表面区域是半导体层指向字线和位线的表面区域的一部分; 以及形成在与所述第一表面区域相邻的第二表面区域上的字线绝缘膜，所述第二表面区域是所述表面区域之外的一部分，所述字线绝缘膜使所述半导体层和所述字线电绝缘，其中半导体层，字线和字线绝缘膜形成电容器，并且当在字线和位线之间给出电位差时，字线绝缘膜被破坏以便存储数据。

56. 发明授权

US07548472B2 Logic embedded memory having registers commonly used by macros 失效
标题翻译：逻辑嵌入式存储器具有通常由宏使用的寄存器
公开(公告)号：US07548472B2
公开(公告)日：2009-06-16
申请号：US11190008
申请日：2005-07-27
申请人： Ryo Fukuda
发明人： Ryo Fukuda
IPC分类号： G11C7/00
CPC分类号： G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C2207/104 , G11C2207/105
摘要： A semiconductor integrated circuit device includes a plurality of memory macros, macro-common register block, and memory macro operation setting circuits. The macro-common register block has macro-common registers which are provided outside the plurality of memory macros and supply memory macro operation specifying signals to the plurality of memory macros. The memory macro operation setting circuits are respectively provided in the plurality of memory macros and are each configured to set an operating state of the memory macro in response to the memory macro operation specifying signal supplied from the macro-common register.
摘要翻译：半导体集成电路器件包括多个存储器宏，宏公共寄存器块和存储器宏操作设置电路。宏公共寄存器块具有宏公共寄存器，其设置在多个存储器宏之外，并且向多个存储器宏提供存储器宏操作指定信号。存储器宏操作设置电路分别设置在多个存储器宏中，并且分别被配置为响应于从宏公共寄存器提供的存储器宏操作指定信号来设置存储器宏的操作状态。

57. 发明申请

US20080239789A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20080239789A1
公开(公告)日：2008-10-02
申请号：US11934337
申请日：2007-11-02
申请人： Tomoaki SHINO , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
发明人： Tomoaki SHINO , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
IPC分类号： G11C11/24 , H01L27/108 , G11C11/34
CPC分类号： G11C11/404 , G11C11/409 , G11C11/4091 , G11C11/4097 , G11C11/4099 , G11C2211/4016 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： The disclosure concerns a semiconductor memory device comprising a semiconductor layer; a charge trap film in contact with a first surface of the semiconductor layer; a gate insulating film in contact with a second surface of the semiconductor layer, the second surface being opposite to the first surface; a back gate electrode in contact with the charge trap film; a gate electrode in contact with the gate insulating film; a source and a drain formed in the semiconductor layer; and a body region provided between the drain and the source, the body region being in an electrically floating state, wherein a threshold voltage or a drain current of a memory cell including the source, the drain, and the gate electrode is adjusted by changing number of majority carriers accumulated in the body region and a quantity of charges trapped into the charge trap film.
摘要翻译：本公开涉及包括半导体层的半导体存储器件; 与所述半导体层的第一表面接触的电荷陷阱膜; 与所述半导体层的第二表面接触的栅极绝缘膜，所述第二表面与所述第一表面相对; 与电荷陷阱膜接触的背栅电极; 与栅极绝缘膜接触的栅电极; 在半导体层中形成的源极和漏极; 以及设置在所述漏极和源极之间的体区，所述体区域处于电浮置状态，其中通过改变数量来调整包括所述源极，漏极和所述栅电极的存储单元的阈值电压或漏极电流的多数载体积聚在身体区域中，并且一定量的电荷被捕获到电荷陷阱膜中。

58. 发明申请

US20070230255A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20070230255A1
公开(公告)日：2007-10-04
申请号：US11487514
申请日：2006-07-17
申请人： Ryo Fukuda
发明人： Ryo Fukuda
IPC分类号： G11C7/00
CPC分类号： G11C7/20 , G11C29/802 , G11C2029/3202
摘要： A semiconductor memory device operating using initialization data, includes a first latch circuit which latches the initialization data, a memory cell array including a plurality of memory cells and having a first region and a second region, the first region storing data, and a buffer circuit having a function for accessing the first latch circuit, the buffer circuit transferring, to the second region, the initialization data transferred from the first latch circuit, and transferring, to the first latch circuit, the initialization data transferred form the second region.
摘要翻译：使用初始化数据操作的半导体存储器件包括锁存初始化数据的第一锁存电路，包括多个存储器单元并具有第一区域和第二区域的存储单元阵列，第一区域存储数据，以及缓冲电路具有访问第一锁存电路的功能，缓冲电路向第二区域传送从第一锁存电路传送的初始化数据，并将从第二区域传送的初始化数据传送到第一锁存电路。

59. 发明授权

US07146546B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07146546B2
公开(公告)日：2006-12-05
申请号：US10683357
申请日：2003-10-14
申请人： Ryo Fukuda
发明人： Ryo Fukuda
IPC分类号： G11C29/00
CPC分类号： G11C29/26 , G11C2029/1802
摘要： A semiconductor device has a least one logic circuit and at least one memory macro cell having a plurality of memory cell array blocks each composed of a plurality of memory cells. Addresses for designating the memory cell array blocks in test are selected among external addresses by a switching signal. The semiconductor device may have a plurality of memory macro calls having a plurality of memory cell array blocks each composed of a plurality of memory cells. The memory macro cells are switched in configuration as having the same length of rows or columns between the memory macro cells in test. The configuration is different from a configuration of row and column for a regular operation.
摘要翻译：半导体器件具有至少一个逻辑电路和至少一个具有由多个存储器单元组成的多个存储单元阵列块的存储器宏单元。通过切换信号在外部地址中选择用于指定测试中的存储单元阵列块的地址。半导体器件可以具有多个存储器宏调用，具有多个存储单元阵列块，每个存储单元阵列块由多个存储器单元组成。存储器宏单元被配置为在测试中的存储器宏单元之间具有相同长度的行或列。该配置与常规操作的行和列的配置不同。

60. 发明申请

US20060161744A1 Logic embedded memory having registers commonly used by macros 失效
公开(公告)号：US20060161744A1
公开(公告)日：2006-07-20
申请号：US11190008
申请日：2005-07-27
申请人： Ryo Fukuda
发明人： Ryo Fukuda
IPC分类号： G06F13/00
CPC分类号： G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C2207/104 , G11C2207/105
摘要： A semiconductor integrated circuit device includes a plurality of memory macros, macro-common register block, and memory macro operation setting circuits. The macro-common register block has macro-common registers which are provided outside the plurality of memory macros and supply memory macro operation specifying signals to the plurality of memory macros. The memory macro operation setting circuits are respectively provided in the plurality of memory macros and are each configured to set an operating state of the memory macro in response to the memory macro operation specifying signal supplied from the macro-common register.

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