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51. 发明授权

US08334532B2 IGZO-based oxide material and method of producing IGZO-based oxide material 有权
标题翻译： IGZO系氧化物材料及IGZO系氧化物材料的制造方法
公开(公告)号：US08334532B2
公开(公告)日：2012-12-18
申请号：US12815414
申请日：2010-06-15
申请人： Kenichi Umeda , Masayuki Suzuki , Atsushi Tanaka
发明人： Kenichi Umeda , Masayuki Suzuki , Atsushi Tanaka
IPC分类号： H01L29/12 , H01L21/26 , H01L21/324 , H01L21/42 , H01L21/477
CPC分类号： H01L29/7869 , C01G15/006 , C01P2002/34 , C01P2002/52 , C01P2002/72 , C01P2006/32 , C01P2006/40 , C30B29/22 , H01L21/02554 , H01L21/02565 , H01L21/02664
摘要： The invention provides an IGZO-based oxide material and a method of producing the same, the IGZO-based oxide material being represented by a composition formula of In2-xGaxZnO4-δ, where 0.75
摘要翻译：本发明提供了一种基于IGZO的氧化物材料及其制造方法，该IGZO系氧化物材料由In2-xGaxZnO4-δ的组成式表示，其中0.75

52. 发明授权

US08298925B2 Mechanisms for forming ultra shallow junction 有权
标题翻译：形成超浅结的机理
公开(公告)号：US08298925B2
公开(公告)日：2012-10-30
申请号：US12941509
申请日：2010-11-08
申请人： Chii-Ming Wu , Yu Lien Huang , Chun Hsiung Tsai
发明人： Chii-Ming Wu , Yu Lien Huang , Chun Hsiung Tsai
IPC分类号： H01L21/26 , H01L21/425 , H01L21/02
CPC分类号： H01L29/7831 , H01L21/2236 , H01L21/823418 , H01L21/823431 , H01L29/66795 , H01L29/66803
摘要： The embodiments of methods and structures are for doping fin structures by plasma doping processes to enable formation of shallow lightly doped source and drain (LDD) regions. The methods involve a two-step plasma doping process. The first step plasma process uses a heavy carrier gas, such as a carrier gas with an atomic weight equal to or greater than about 20 amu, to make the surfaces of fin structures amorphous and to reduce the dependence of doping rate on crystalline orientation. The second step plasma process uses a lighter carrier gas, which is lighter than the carrier gas for the first step plasma process, to drive the dopants deeper into the fin structures. The two-step plasma doping process produces uniform dopant profile beneath the outer surfaces of the fin structures.
摘要翻译：方法和结构的实施例用于通过等离子体掺杂工艺掺杂鳍结构，以形成浅掺杂的源极和漏极（LDD）区域。该方法涉及两步等离子体掺杂工艺。第一级等离子体工艺使用重载气，例如原子量等于或大于约20amu的载气，以使翅片结构的表面无定形并且降低掺杂速率对晶体取向的依赖性。第二级等离子体处理使用比用于第一级等离子体处理的载气轻的载气，以将掺杂剂更深地驱动到鳍结构中。两级等离子体掺杂工艺在翅片结构的外表面下方产生均匀的掺杂剂分布。

53. 发明申请

US20120258606A1 E-Beam Enhanced Decoupled Source for Semiconductor Processing 有权
标题翻译：用于半导体处理的电子束增强去耦源
公开(公告)号：US20120258606A1
公开(公告)日：2012-10-11
申请号：US13356962
申请日：2012-01-24
申请人： John Patrick Holland , Peter L. G. Ventzek , Harmeet Singh , Jun Shinagawa , Akira Koshiishi
发明人： John Patrick Holland , Peter L. G. Ventzek , Harmeet Singh , Jun Shinagawa , Akira Koshiishi
IPC分类号： H01L21/26 , H01L21/3065
CPC分类号： H01J37/32357 , H01J37/32376 , H01J37/32449 , H01J37/32596
摘要： A semiconductor substrate processing system includes a processing chamber and a substrate support defined to support a substrate in the processing chamber. The system also includes a plasma chamber defined separate from the processing chamber. The plasma chamber is defined to generate a plasma. The system also includes a plurality of fluid transmission pathways fluidly connecting the plasma chamber to the processing chamber. The plurality of fluid transmission pathways are defined to supply reactive constituents of the plasma from the plasma chamber to the processing chamber. The system further includes an electron injection device for injecting electrons into the processing chamber to control an electron energy distribution within the processing chamber so as to in turn control an ion-to-radical density ratio within the processing chamber. In one embodiment, an electron beam source is defined to transmit an electron beam through the processing chamber above and across the substrate support.
摘要翻译：半导体基板处理系统包括处理室和限定为在处理室中支撑基板的基板支撑件。该系统还包括与处理室分开限定的等离子体室。等离子体室被定义为产生等离子体。该系统还包括将等离子体室流体连接到处理室的多个流体传输路径。多个流体传输路径被限定为将等离子体的反应性组分从等离子体室提供给处理室。该系统还包括用于将电子注入到处理室中以控制处理室内的电子能量分布的电子注入装置，从而控制处理室内的离子 - 自由基密度比。在一个实施例中，电子束源被定义为将电子束透过衬底支撑件上方并穿过衬底支撑件的处理室。

54. 发明申请

US20120199953A1 SEMICONDUCTOR STRUCTURE WITH SMOOTHED SURFACE AND PROCESS FOR OBTAINING SUCH A STRUCTURE 有权
标题翻译：具有平滑表面的半导体结构和获得这种结构的工艺
公开(公告)号：US20120199953A1
公开(公告)日：2012-08-09
申请号：US13349263
申请日：2012-01-12
申请人： Michel Bruel
发明人： Michel Bruel
IPC分类号： H01L29/30 , H01L21/26
CPC分类号： H01L21/302 , H01L21/268 , H01L21/3247 , H01L21/76254
摘要： The present invention relates to a process for smoothing the surface of a semiconductor wafer by fusion. The process includes defining a reference length which dimensions wafer surface roughness that is to be reduced or removed, and scanning the surface with a fusion beam while adjusting parameters of the fusion beam so as to fuse, during the scanning of the surface, a local surface zone of the wafer whose length is greater than or equal to the reference length, with the scanning continued to smooth the entire surface of the wafer by eliminating surface roughnesses of period lower than the reference length. The present invention also relates to a semiconductor wafer having a surface layer made of a semiconducting material that is smoothed by the process and that does not exhibit any roughness of period lower than the reference length.
摘要翻译：本发明涉及通过熔化来平滑半导体晶片的表面的工艺。该过程包括定义参考长度，其缩小待削减或去除的晶片表面粗糙度，以及在调整熔合束的参数的同时用熔融光束扫描表面，从而在扫描表面期间熔化局部表面长度大于或等于参考长度的晶片的区域，扫描通过消除低于参考长度的周期的表面粗糙度，继续平滑晶片的整个表面。本发明还涉及一种半导体晶片，其具有由半导体材料制成的表面层，该表面层通过该工艺平滑，并且不显示比参考长度低的周期的粗糙度。

55. 发明申请

US20120129358A1 SUBSTRATE PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：基板加工装置及制造半导体装置的方法
公开(公告)号：US20120129358A1
公开(公告)日：2012-05-24
申请号：US13240545
申请日：2011-09-22
申请人： Unryu OGAWA , Masahisa OKUNO , Tokunobu AKAO , Shinji YASHIMA , Atsushi UMEKAWA , Kaichiro MINAMI
发明人： Unryu OGAWA , Masahisa OKUNO , Tokunobu AKAO , Shinji YASHIMA , Atsushi UMEKAWA , Kaichiro MINAMI
IPC分类号： H01L21/26 , H05B6/80
CPC分类号： H01L21/67109 , H01L21/67115 , H01L21/6875 , H05B6/806
摘要： Provided are a substrate processing apparatus and a method of manufacturing a semiconductor device that are capable of uniformly heating a substrate while reducing an increase in substrate temperature to reduce a thermal budget. The substrate processing apparatus includes a process chamber configured to process a substrate; a substrate support unit installed in the process chamber to support the substrate; a microwave supply unit configured to supply a microwave toward a process surface of the substrate supported by the substrate support unit, the microwave supply unit including a microwave radiating unit radiating the microwave supplied from a microwave source to the process chamber while rotating; a partition installed between the microwave supply unit and the substrate support unit; a cooling unit installed at the substrate support unit; and a control unit configured to control at least the substrate support unit, the microwave supply unit and the cooling unit.
摘要翻译：提供了一种能够均匀加热衬底同时减少衬底温度增加以降低热量预算的衬底处理设备和半导体器件的制造方法。基板处理装置包括：处理室，被配置为处理基板; 安装在所述处理室中以支撑所述基板的基板支撑单元; 微波供给单元，被配置为向由所述基板支撑单元支撑的所述基板的处理表面供给微波，所述微波供给单元包括微波辐射单元，所述微波辐射单元在旋转的同时将从微波源供应的微波辐射到所述处理室; 安装在所述微波供给单元和所述基板支撑单元之间的隔板; 安装在所述基板支撑单元处的冷却单元; 以及控制单元，被配置为至少控制所述基板支撑单元，所述微波提供单元和所述冷却单元。

56. 发明申请

US20120088329A1 SEMICONDUCTOR MULTI-PROJECT OR MULTI-PRODUCT WAFER PROCESS 审中-公开
标题翻译：半导体多项目或多产品流程
公开(公告)号：US20120088329A1
公开(公告)日：2012-04-12
申请号：US13228237
申请日：2011-09-08
申请人： Weng-Dah Ken
发明人： Weng-Dah Ken
IPC分类号： H01L21/50 , H01L21/30 , H01L21/265 , H01L21/26 , H01L21/302
CPC分类号： H01L25/50 , G03F1/50 , G03F7/0035 , H01L21/263 , H01L21/283 , H01L21/304 , H01L21/76802 , H01L21/78 , H01L22/26 , H01L22/32 , H01L23/544 , H01L24/11 , H01L24/16 , H01L24/48 , H01L24/81 , H01L24/85 , H01L24/89 , H01L24/94 , H01L25/0657 , H01L25/18 , H01L2223/5446 , H01L2224/16145 , H01L2224/16146 , H01L2224/48145 , H01L2224/94 , H01L2225/06506 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/13091 , H01L2924/14 , H01L2924/37001 , H01L2924/3701 , H01L2224/81 , H01L2224/85 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： The embodiment provides a semiconductor MP wafer process including processing a plurality of MP wafers in a lot or batch with a first process step. The plurality of the MP wafers is split into an MP wafer group-1 and an MP wafer group-2. At least one of the MP wafers of the MP wafer group-1 is processed with a second process step-1 and at least one of the MP wafers of the MP wafer group-2 is processed with a second process step-2 to form different device components on the MP wafers of the MP wafer group-1 and group-2, respectively. At least one of the MP wafers of the MP wafer group-1 is processed with a third process step-3 and at least one of the MP wafers of the MP wafer group-2 is processed with a third process step-4 to form a substantially same device component on the MP wafers.
摘要翻译：该实施例提供了一种半导体MP晶片工艺，包括用第一工艺步骤在批或批中处理多个MP晶片。多个MP晶片被分成MP晶片组-1和MP晶片组-2。 MP晶片组-1的MP晶片中的至少一个用第二工艺步骤-1进行处理，并且MP晶片组-2的至少一个MP晶片用第二工艺步骤2处理以形成不同的分别在MP晶片组-1和组-2的MP晶片上的器件组件。 MP晶片组-1的MP晶片中的至少一个用第三工艺步骤-3处理，MP晶片组-2的MP晶片中的至少一个用第三工艺步骤-4处理，以形成在MP晶片上基本相同的器件部件。

57. 发明申请

US20120083135A1 ASYMMETRIC RAPID THERMAL ANNEALING TO REDUCE PATTERN EFFECT 有权
标题翻译：不对称快速热退火以减少图案效应
公开(公告)号：US20120083135A1
公开(公告)日：2012-04-05
申请号：US12898037
申请日：2010-10-05
申请人： Chun Hsiung TSAI , Chii-Ming WU , Da-Wen LIN
发明人： Chun Hsiung TSAI , Chii-Ming WU , Da-Wen LIN
IPC分类号： H01L21/26
CPC分类号： H01L21/324 , H01L21/26513 , H01L21/67248
摘要： Rapid thermal annealing methods and systems for annealing patterned substrates with minimal pattern effect on substrate temperature non-uniformity are provided. The rapid thermal annealing system includes a front-side heating source and a backside heating source. The backside heating source of the rapid thermal annealing system supplies a dominant amount of heat to bring the substrate temperature to the peak annealing temperature. The front-side heating source contributes to heat up the environment near the front-side of the substrate to a temperature lower than about 100° C. to about 200° C. less than the peak annealing temperature. The asymmetric front-side and backside heating for rapid thermal annealing reduce or eliminate pattern effect and improve WIW and WID device performance uniformity.
摘要翻译：提供了用于退火图案化衬底的快速热退火方法和系统，对衬底温度的不均匀性具有最小的图案效应。快速热退火系统包括前侧加热源和背面加热源。快速热退火系统的背面加热源提供显着的热量以使衬底温度达到峰值退火温度。前侧加热源有助于将基板前侧附近的环境加热到低于峰值退火温度的约100℃至约200℃的温度。用于快速热退火的不对称前侧和后侧加热减少或消除图案效应，并提高WIW和WID器件的性能均匀性。

58. 发明申请

US20120071007A1 SUBSTRATE PROCESSING WITH REDUCED WARPAGE AND/OR CONTROLLED STRAIN 审中-公开
标题翻译：具有降低的温度和/或控制应变的基板加工
公开(公告)号：US20120071007A1
公开(公告)日：2012-03-22
申请号：US13245778
申请日：2011-09-26
申请人： Yun Wang , Shaoyin Chen
发明人： Yun Wang , Shaoyin Chen
IPC分类号： H01L21/26 , G21K5/00
CPC分类号： H01L21/263 , B23K26/0006 , B23K26/082 , B23K26/0823 , B23K26/352 , B23K2103/56 , C30B1/06 , H01L21/02532 , H01L21/02675 , H01L21/02691
摘要： Provided are systems and methods for processing the surface of substrates that scan a laser beam at one or more selected orientation angles. The orientation angle or angles may be selected to reduce substrate warpage. When the substrates are semiconductor wafers having microelectronic devices, the orientation angles may be selected to produce controlled strain and to improve electronic performance of the devices.
摘要翻译：提供了用于处理以一个或多个选定取向角度扫描激光束的基板表面的系统和方法。可以选择取向角或角度以减少基板翘曲。当衬底是具有微电子器件的半导体晶片时，可以选择取向角以产生受控应变并改善器件的电子性能。

59. 发明申请

US20110299317A1 INTEGRATED CIRCUIT HEATING TO EFFECT IN-SITU ANNEALING 有权
标题翻译：集成电路加热来影响现场退火
公开(公告)号：US20110299317A1
公开(公告)日：2011-12-08
申请号：US12859554
申请日：2010-08-19
申请人： Ian P. Shaeffer , Gary B. Bronner , Brent S. Haukness , Kevin S. Donnelly , Frederick A. Ware , Mark A. Horowitz
发明人： Ian P. Shaeffer , Gary B. Bronner , Brent S. Haukness , Kevin S. Donnelly , Frederick A. Ware , Mark A. Horowitz
IPC分类号： G11C13/00 , H01L21/26
CPC分类号： G11C16/26 , G11C7/04 , G11C13/0002 , G11C13/0033 , G11C13/0035 , G11C16/06 , H01L21/324
摘要： In a system having a memory device, an event is detected during system operation. The memory device is heated to reverse use-incurred degradation of the memory device in response to detecting the event. In another system, the memory device is heated to reverse use-incurred degradation concurrently with execution of a data access operation within another memory device of the system. In another system having a memory controller coupled to first and second memory devices, data is evacuated from the first memory device to the second memory device in response to determining that a maintenance operation is needed within the first memory device.
摘要翻译：在具有存储器件的系统中，在系统操作期间检测到事件。响应于检测到事件，存储器件被加热以反转存储器件的使用中的劣化。在另一系统中，存储器件被加热以与系统的另一个存储器件内的数据访问操作的执行同时反向使用所引起的降级。在具有耦合到第一和第二存储器设备的存储器控制器的另一系统中，响应于确定在第一存储器设备内需要维护操作，将数据从第一存储器设备撤出到第二存储器设备。

60. 发明授权

US08067302B2 Defect-free junction formation using laser melt annealing of octadecaborane self-amorphizing implants 有权
标题翻译：使用十八硼烷自身无定形植入物的激光熔融退火的无缺陷结形成
公开(公告)号：US08067302B2
公开(公告)日：2011-11-29
申请号：US12563746
申请日：2009-09-21
申请人： Jiping Li
发明人： Jiping Li
IPC分类号： H01L21/26
CPC分类号： H01L21/265 , H01J37/32357 , H01J37/32412 , H01L21/26513 , H01L21/324
摘要： A method and apparatus for implanting a semiconductor substrate with boron clusters. A substrate is implanted with octadecaborane by plasma immersion or ion beam implantation. The substrate surface is then melted, resolidified, and annealed to completely dissociate and activate the boron clusters.
摘要翻译：一种用硼簇植入半导体衬底的方法和装置。通过等离子体浸渍或离子束注入，注入十八硼烷衬底。然后将衬底表面熔化，重新固化和退火，以完全解离并活化硼簇。

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