会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 58. 发明授权
    • Gate driving circuit and display device having the same
    • 栅极驱动电路及其显示装置
    • US09564889B2
    • 2017-02-07
    • US14296421
    • 2014-06-04
    • AU Optronics Corp.
    • Chen-Chi LinChun-Hsin Liu
    • G09G5/00H03K17/56G09G3/32
    • H03K17/56G09G3/3266G09G2310/0286
    • A gate driving circuit includes plural-stage output circuits, an Nth stage output circuit of the plural-stage output circuits includes an Nth stage shift register and a mixer. The Nth stage shift register is configured to output an Nth pulse signal. The mixer is coupled to the Nth stage shift register and an (N+M)th stage shift register, for respectively outputting a first clock signal and a predetermined pulse signal during different periods according to the Nth pulse signal and an (N+M)th pulse signal of the (N+M)th stage shift register. Wherein pulse widths or phases of the first clock signal and the predetermined pulse signal are different, and N and M are positive integers.
    • 门驱动电路包括多级输出电路,多级输出电路的第N级输出电路包括第N级移位寄存器和混频器。 第N级移位寄存器被配置为输出第N个脉冲信号。 混频器耦合到第N级移位寄存器和第(N + M)级移位寄存器,用于根据第N个脉冲信号在不同周期内分别输出第一时钟信号和预定脉冲信号,并且(N + M) (N + M)级移位寄存器的脉冲信号。 其中第一时钟信号和预定脉冲信号的脉冲宽度或相位不同,并且N和M是正整数。