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61. 发明授权

US08222065B1 Method and system for forming a capacitive micromachined ultrasonic transducer 有权
标题翻译：用于形成电容微加工超声换能器的方法和系统
公开(公告)号：US08222065B1
公开(公告)日：2012-07-17
申请号：US12587139
申请日：2009-10-02
申请人： Peter Smeys , Peter Johnson , Gokhan Percin
发明人： Peter Smeys , Peter Johnson , Gokhan Percin
IPC分类号： H01L29/72
CPC分类号： B06B1/0292 , H01L27/0688
摘要： A method for forming a capacitive micromachined ultrasonic transducer (CMUT) is provided that includes forming oxide features outwardly of a CMUT control chip in a silicon wafer. The oxide features are planarized. A silicon-on-insulator (SOI) wafer is bonded to the planarized oxide features. For a particular embodiment, the SOI wafer comprises a single crystal epitaxial layer, a buried oxide layer and a silicon layer, and the single crystal epitaxial layer is bonded to the planarized oxide features, after which the silicon layer and the buried oxide layer of the SOI wafer are removed, leaving the single crystal epitaxial layer bonded to the oxide layer.
摘要翻译：提供一种用于形成电容微加工超声换能器（CMUT）的方法，其包括在硅晶片中的CMUT控制芯片外部形成氧化物特征。氧化物的特征被平坦化。绝缘体上硅（SOI）晶片与平坦化的氧化物特征结合。对于特定实施例，SOI晶片包括单晶外延层，掩埋氧化物层和硅层，并且单晶外延层结合到平坦化的氧化物特征，之后硅层和掩埋氧化物层去除SOI晶片，留下单晶外延层与氧化物层结合。

62. 发明授权

US08207578B2 Method of forming a region of graded doping concentration in a semiconductor device and related apparatus 有权
标题翻译：在半导体器件和相关装置中形成渐变掺杂浓度区域的方法
公开(公告)号：US08207578B2
公开(公告)日：2012-06-26
申请号：US13156184
申请日：2011-06-08
申请人： William French , Erika Mazotti , Yuri Mirgorodski
发明人： William French , Erika Mazotti , Yuri Mirgorodski
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L21/2253 , H01L29/0653 , H01L29/1045 , H01L29/66659 , H01L29/7835
摘要： A method for forming a doped region of a semiconductor device includes masking a portion of a substrate with a mask. The mask is configured to create a graded doping profile within the doped region. The method also includes performing an implant using the mask to create doped areas and undoped areas in the substrate. The method further includes diffusing the doped areas to create the graded doping profile in the doped region. The mask could include a first region having openings distributed throughout a photo-resist material, where the openings vary in size and spacing. The mask could also include a second region having blocks of photo-resist material distributed throughout an open region, where the photo-resist blocks vary in size and spacing. Diffusing the doped areas could include applying a high temperature anneal to smooth the doped and undoped areas to produce a linearly graded doping profile.
摘要翻译：用于形成半导体器件的掺杂区域的方法包括用掩模掩蔽衬底的一部分。掩模被配置为在掺杂区域内产生渐变掺杂分布。该方法还包括使用掩模执行植入物以在衬底中产生掺杂区域和未掺杂区域。该方法还包括扩散掺杂区域以在掺杂区域中产生渐变掺杂分布。掩模可以包括具有分布在整个光致抗蚀剂材料中的开口的第一区域，其中开口的尺寸和间隔变化。掩模还可以包括具有分布在整个开放区域中的光致抗蚀剂材料块的第二区域，其中光刻胶块的尺寸和间距变化。扩散掺杂区域可以包括施加高温退火以使掺杂和未掺杂区域平滑以产生线性渐变的掺杂分布。

63. 发明申请

US20120146819A1 SIGMA-DELTA DIFFERENCE-OF-SQUARES LOG-RMS TO DC CONVERTER WITH FORWARD PATH MULTIPLIER AND CHOPPER STABILIZATION 有权
标题翻译： SIGMA-DELTA差分差分直流转换器与前进路径乘法器和CHOPPER稳定
公开(公告)号：US20120146819A1
公开(公告)日：2012-06-14
申请号：US12963265
申请日：2010-12-08
申请人： Paulo Gustavo Raymundo Silva , Michael Hendrikus Laurentius Kouwenhoven
发明人： Paulo Gustavo Raymundo Silva , Michael Hendrikus Laurentius Kouwenhoven
IPC分类号： H03M1/02 , H03M3/00
CPC分类号： H03M3/34 , G01R19/02 , G01R19/25 , G06J1/00 , H03M3/424 , H03M3/476
摘要： A sigma-delta (ΣΔ) difference-of-squares LOG-RMS to digital converter for true RMS detection by merging a ΣΔ modulator with an analog LOG-RMS to DC converter based on a difference-of-squares. Chopper-stabilization, implemented through commutators running at two different frequencies, can be employed to reduce sensitivity to DC offsets and low-frequency errors, resulting in an extension of the useful input-referred dynamic range. High-order ΣΔ LOG-RMS converters can be implemented with a loop filter containing multiple integrators and feedforward and/or feedback paths for frequency compensation. The resulting implementations are ΣΔ difference-of-squares LOG-RMS to DC converters with a natural digital output and a logarithmically compressed dynamic range.
摘要翻译：一个Σ-Δ（＆Sgr＆amp; Dgr）的差分方向LOG-RMS到数字转换器，用于通过合并＆Sgr＆Dgr进行真实RMS检测; 基于平方差的模拟LOG-RMS到DC转换器的调制器。可以采用通过以两个不同频率运行的换向器实现的斩波稳定，以降低对直流偏移和低频误差的敏感性，从而导致有用的输入参考动态范围的扩展。高等学校 LOG-RMS转换器可以使用包含多个积分器的环路滤波器和用于频率补偿的前馈和/或反馈路径来实现。最终的实现是＆Sgr;＆Dgr; 具有自然数字输出和对数压缩的动态范围的方差的LOG-RMS到DC转换器。

64. 发明授权

US08200879B1 Memory interface including an efficient variable-width bus 有权
标题翻译：存储器接口包括有效的可变宽度总线
公开(公告)号：US08200879B1
公开(公告)日：2012-06-12
申请号：US10934111
申请日：2004-09-03
申请人： Ohad Falik , Leonid Azriel
发明人： Ohad Falik , Leonid Azriel
IPC分类号： G06F13/40
CPC分类号： G11C5/02 , H01L24/05 , H01L25/0657 , H01L2224/48145 , H01L2224/49171 , H01L2225/06562 , H01L2924/01087 , H01L2924/14 , H01L2924/19043 , H01L2924/3011 , H01L2924/00012
摘要： A semiconductor device includes an interface controller for communication with a memory device over a communication link. The link includes a plurality of data lines for transmitting data. A plurality of bus width values are defined, each being a selectable number of data lines over which data are to be transmitted. The number of data lines is in the range between one and the number of the plurality of data lines. The interface controller is dynamically configurable to any of the defined bus width values, which becomes the current bus width. The transmission over each data line may be selectably in either direction. The transmission over all data lines corresponding to the current bus width may collectively carry, in at least one direction, command codes, memory addresses, and data in an intermixed manner.
摘要翻译：半导体器件包括用于通过通信链路与存储器件通信的接口控制器。链路包括用于发送数据的多条数据线。定义了多个总线宽度值，每个总线宽度值是数据要发送的可选数量的数据线。数据线的数量在多个数据线的一个和数量之间的范围内。接口控制器可动态配置为任何定义的总线宽度值，这将成为当前的总线宽度。每条数据线上的传输可以任意方向选择。对应于当前总线宽度的所有数据线上的传输可以在至少一个方向上以混合方式共同携带命令代码，存储器地址和数据。

65. 发明申请

US20120105032A1 SYSTEM AND METHOD FOR PROVIDING AN ACTIVE CURRENT ASSIST WITH ANALOG BYPASS FOR A SWITCHER CIRCUIT 审中-公开
标题翻译：用于为切换电路提供模拟旁路的有源电流辅助系统和方法
公开(公告)号：US20120105032A1
公开(公告)日：2012-05-03
申请号：US13344428
申请日：2012-01-05
申请人： Jeffry Mark Huard
发明人： Jeffry Mark Huard
IPC分类号： G05F1/10
CPC分类号： H02M3/158 , H02M2003/1566
摘要： A system and method are disclosed for providing an active current assist with analog bypass for a switcher circuit. An active current assist circuit is coupled to a buck regulator circuit, which includes a switcher circuit, an inductor circuit and a capacitor circuit. The active current assist circuit includes an active current analog bypass control circuit and a current source. The active current analog bypass control circuit receives and uses current limit information, voltage error information, and drop out information to determine a value of assist current that is appropriate for a current operational state of the buck regulator circuit. The active current analog bypass control circuit causes the current source to provide the appropriate value of assist current to the buck regulator circuit.
摘要翻译：公开了一种用于为切换器电路提供模拟旁路的有源电流辅助的系统和方法。有源电流辅助电路耦合到降压调节器电路，其包括开关电路，电感器电路和电容器电路。有源电流辅助电路包括有源电流模拟旁路控制电路和电流源。有源电流模拟旁路控制电路接收并使用限流信息，电压误差信息和丢失信息，以确定适合于降压调节器电路的当前工作状态的辅助电流值。有源电流模拟旁路控制电路使得电流源向降压调节器电路提供适当的辅助电流值。

66. 发明申请

US20120091501A1 Low triggering voltage DIAC structure 有权
标题翻译：低触发电压DIAC结构
公开(公告)号：US20120091501A1
公开(公告)日：2012-04-19
申请号：US12925277
申请日：2010-10-18
申请人： Vladislav Vashchenko , Antonio Gallerano , Peter J. Hopper
发明人： Vladislav Vashchenko , Antonio Gallerano , Peter J. Hopper
IPC分类号： H01L29/747 , H01L21/332
CPC分类号： H01L29/87 , H01L27/0262 , H01L29/66121
摘要： In a DIAC-like device that includes an n+ and a p+ region connected to the high voltage node, and an n+ and a p+ region connected to the low voltage node, at least two MOS devices are formed between the n+ and p+ region connected to the high voltage node, and the n+ and p+ region connected to the low voltage node.
摘要翻译：在包括连接到高压节点的n +和p +区以及连接到低电压节点的n +和p +区的DIAC类器件中，在连接到低电压节点的n +和p +区之间形成至少两个MOS器件高压节点，连接到低电压节点的n +和p +区域。

67. 发明授权

US08159877B2 Method of directly reading output voltage to determine data stored in a non-volatile memory cell 有权
标题翻译：直接读取输出电压以确定存储在非易失性存储单元中的数据的方法
公开(公告)号：US08159877B2
公开(公告)日：2012-04-17
申请号：US12731589
申请日：2010-03-25
申请人： Pavel Poplevine , Ernes Ho , Umer Khan , Andrew J. Franklin
发明人： Pavel Poplevine , Ernes Ho , Umer Khan , Andrew J. Franklin
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0441 , G11C16/06
摘要： An NVM cell design enables direct reading of cell output voltage to determine data stored in the cell, while providing low current consumption and a simple program sequence that utilizes reverse Fowler-Nordheim tunneling.
摘要翻译： NVM单元设计使得能够直接读取单元输出电压以确定存储在单元中的数据，同时提供低电流消耗和采用反向Fowler-Nordheim隧道的简单程序序列。

68. 发明申请

US20120086701A1 Combined digital modulation and current dimming control for light emitting diodes 有权
标题翻译：用于发光二极管的组合数字调制和电流调光控制
公开(公告)号：US20120086701A1
公开(公告)日：2012-04-12
申请号：US12925030
申请日：2010-10-12
申请人： Ari K. Väänänen , Mauri K. Määttä , T. Tapani Tuikkanen
发明人： Ari K. Väänänen , Mauri K. Määttä , T. Tapani Tuikkanen
IPC分类号： G06F3/038
CPC分类号： H05B33/0848 , G09G3/3406 , G09G2320/0633 , G09G2320/064 , G09G2320/0653 , G09G2360/144
摘要： A method includes providing an input signal identifying a desired brightness for one or more LEDs to first and second parallel control paths. The method also includes generating a digital modulation control signal using the first control path, generating a current control signal using the second control path, and driving the one or more LEDs using the control signals. The method further includes performing compensation in at least one of the control paths to compensate for an increased efficiency of the one or more LEDs. Generating the control signals could include (i) adjusting the digital modulation control signal while maintaining the current control signal at a substantially constant value for a range of lower LED brightness values and (ii) adjusting the current control signal while maintaining the digital modulation control signal at a maximum value or within a range of maximum values for a range of higher LED brightness values.
摘要翻译：一种方法包括向第一和第二并行控制路径提供将一个或多个LED标识期望亮度的输入信号。该方法还包括使用第一控制路径产生数字调制控制信号，使用第二控制路径产生电流控制信号，以及使用控制信号驱动一个或多个LED。该方法还包括在至少一个控制路径中执行补偿以补偿一个或多个LED的增加的效率。产生控制信号可以包括：（i）调节数字调制控制信号，同时将电流控制信号保持在较低LED亮度值的范围内基本上恒定的值，以及（ii）在保持数字调制控制信号的同时调节电流控制信号在最大值或在更高的LED亮度值的范围的最大值的范围内。

69. 发明申请

US20120074561A1 BACKMETAL REPLACEMENT FOR USE IN THE PACKAGING OF INTEGRATED CIRCUITS 审中-公开
标题翻译：用于集成电路封装的背面替换
公开(公告)号：US20120074561A1
公开(公告)日：2012-03-29
申请号：US12891440
申请日：2010-09-27
申请人： Nghia T. TU , Will K. WONG , Jamie A. BAYAN
发明人： Nghia T. TU , Will K. WONG , Jamie A. BAYAN
IPC分类号： H01L23/34 , H01L21/50
CPC分类号： H01L23/4334 , H01L21/561 , H01L21/566 , H01L23/3107 , H01L23/49548 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/30 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/93 , H01L24/97 , H01L2224/13 , H01L2224/131 , H01L2224/16245 , H01L2224/27416 , H01L2224/27418 , H01L2224/29 , H01L2224/29101 , H01L2224/2919 , H01L2224/2929 , H01L2224/29339 , H01L2224/30505 , H01L2224/48091 , H01L2224/48247 , H01L2224/73253 , H01L2224/73265 , H01L2224/81815 , H01L2224/93 , H01L2224/97 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01074 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/181 , H01L2924/18161 , H01L2924/18165 , H01L2224/27 , H01L2224/85 , H01L2224/81 , H01L2924/00 , H01L2924/01014 , H01L2924/01032 , H01L2924/01031 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： One aspect of the invention pertains to an arrangement for forming exposed die packages. The arrangement includes a semiconductor wafer having multiple integrated circuit dice whose back surfaces cooperate to form the back surface of the wafer. A thermally conductive adhesive layer is deposited on the back surface of the wafer. The metal foil is attached to the wafer with the adhesive layer. Methods of forming exposed die packages using the above arrangement are also described.
摘要翻译：本发明的一个方面涉及用于形成暴露的模头封装的布置。该装置包括具有多个集成电路芯片的半导体晶片，其后表面协作以形成晶片的后表面。导热粘合剂层沉积在晶片的背面上。金属箔用粘合剂层附着到晶片上。还描述了使用上述布置形成暴露的模头封装的方法。

70. 发明授权

US08115196B2 High performance SiGe:C HBT with phosphorous atomic layer doping 有权
标题翻译：高性能SiGe：C HBT具有磷原子层掺杂
公开(公告)号：US08115196B2
公开(公告)日：2012-02-14
申请号：US13031496
申请日：2011-02-21
申请人： Janial Ramdani , Craig Richard Printy , Thanas Budri
发明人： Janial Ramdani , Craig Richard Printy , Thanas Budri
IPC分类号： H01L31/00
CPC分类号： H01L29/7378 , H01L21/02381 , H01L21/02529 , H01L21/02532 , H01L21/02579 , H01L21/02617
摘要： A base structure for high performance Silicon Germanium:Carbon (SiGe:C) based heterojunction bipolar transistors (HBTs) with phosphorus atomic layer doping (ALD) is disclosed. The ALD process subjects the base substrate to nitrogen gas (in ambient temperature approximately equal to 500 degrees Celsius) and provides an additional SiGe:C spacer layer. During the ALD process, the percent concentrations of Germanium (Ge) and carbon (C) are substantially matched and phosphorus is a preferred dopant. The improved SiGe:C HBT is less sensitive to process temperature and exposure times, and exhibits lower dopant segregation and sharper base profiles.
摘要翻译：公开了具有磷原子层掺杂（ALD）的高性能硅锗：基于碳（SiGe：C）的异质结双极晶体管（HBT）的基础结构。 ALD工艺使基底衬底受氮气（在大约等于500摄氏度的环境温度下），并提供另外的SiGe：C间隔层。在ALD过程中，锗（Ge）和碳（C）的百分比浓度基本匹配，磷是优选的掺杂剂。改进的SiGe：C HBT对工艺温度和曝光时间较不敏感，并且显示较低的掺杂剂偏析和更尖锐的基体分布。

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