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61. 发明申请

US20090228690A1 Early Exit Processing of Iterative Refinement Algorithm Using Register Dependency Disable 失效
标题翻译：使用寄存器依赖关系禁用的迭代优化算法的早期退出处理
公开(公告)号：US20090228690A1
公开(公告)日：2009-09-10
申请号：US12045313
申请日：2008-03-10
申请人： Adam James Muff , Matthew Ray Tubbs
发明人： Adam James Muff , Matthew Ray Tubbs
IPC分类号： G06F9/38
CPC分类号： G06F9/30014 , G06F7/4873 , G06F7/535 , G06F9/30065 , G06F9/3838 , G06F9/3851 , G06F9/3857 , G06F9/3859 , G06F2207/5355 , G06F2207/5356
摘要： An “early exit” of an iterative refinement algorithm is implemented by effectively disabling read after write dependency stalls of newer instructions, as well as disabling the register write enable of these instructions, for the remainder of the algorithm, in addition to disabling the register write enable of these instructions. By doing so, the latency of the algorithm is reduced and the performance is increased without the complexity and potential poor performance of compare and branch instructions that might otherwise be required.
摘要翻译：迭代细化算法的“提前退出”除了禁用寄存器写入之外，还通过有效禁用更新指令的写依赖性停止之后的读取以及禁止这些指令的寄存器写使能，对于算法的其余部分启用这些指令。通过这样做，降低了算法的等待时间，并且性能得到提高，而没有另外需要的比较和分支指令的复杂性和潜在的差的性能。

62. 发明申请

US20090228689A1 Early Exit Processing of Iterative Refinement Algorithm Using Register Dependency Disable and Programmable Early Exit Condition 失效
标题翻译：使用寄存器依赖关闭和可编程提前退出条件的迭代优化算法的早期退出处理
公开(公告)号：US20090228689A1
公开(公告)日：2009-09-10
申请号：US12045243
申请日：2008-03-10
申请人： Adam James Muff , Matthew Ray Tubbs
发明人： Adam James Muff , Matthew Ray Tubbs
IPC分类号： G06F9/38
CPC分类号： G06F9/30014 , G06F7/4873 , G06F7/535 , G06F9/30065 , G06F9/3838 , G06F9/3851 , G06F9/3857 , G06F9/3859 , G06F2207/5355 , G06F2207/5356
摘要： A programmable “early exit” of an iterative refinement algorithm is implemented by effectively disabling read after write dependency stalls of newer instructions, as well as disabling the register write enable of these instructions, for the remainder of the algorithm, in addition to disabling the register write enable of these instructions. In addition, programmable logic is provided to enable a custom early exit condition to be specified for the iterative refinement algorithm so that the underlying hardware can be configured for optimal execution of particular iterative refinement algorithms. By doing so, the latency of the algorithm is reduced and the performance is increased without the complexity and potential poor performance of compare and branch instructions that might otherwise be required.
摘要翻译：迭代细化算法的可编程的“提前退出”是通过有效禁用更新指令的写依赖性停止之后的读取，以及禁用这些指令的其余部分的这些指令的寄存器写使能，除了禁止寄存器写这些指令的使能。此外，提供可编程逻辑以使得能够为迭代细化算法指定定制的早期退出条件，使得可以配置底层硬件以优化特定迭代细化算法的执行。通过这样做，降低了算法的等待时间，并且性能得到提高，而没有另外需要的比较和分支指令的复杂性和潜在的差的性能。

63. 发明申请

US20090182987A1 Processing Unit Incorporating Multirate Execution Unit 失效
标题翻译：加工单元并入多速率执行单元
公开(公告)号：US20090182987A1
公开(公告)日：2009-07-16
申请号：US11972746
申请日：2008-01-11
申请人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
发明人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
IPC分类号： G06F9/30
CPC分类号： G06F9/3869 , G06F1/3203 , G06F1/324 , G06F9/3836 , G06F9/3838 , G06F9/3851 , G06F9/3885 , Y02D10/126
摘要： A multirate execution unit is capable of being operated in a plurality of modes, with the execution unit being capable of clocked at multiple different rates relative to a multithreaded issue unit such that, in applications where maximum performance is desired, the execution unit can be clocked at a rate that is faster than the clock rate for the multithreaded issue unit, and in applications where a lower power profile is desired, the execution unit can be throttled back to a slower rate to reduce the power consumption of the execution unit. When the execution unit is clocked at a faster rate than the multithreaded issue unit, the issue unit is permitted to issue more instructions per cycle than when the execution unit is throttled to the slower rate to increase overall instruction throughput.
摘要翻译：多速率执行单元能够以多种模式操作，其中执行单元能够以相对于多线程发布单元的多个不同速率进行计时，使得在需要最大性能的应用中，执行单元可被计时以比多线程发布单元的时钟速率快的速率，以及在需要较低功率配置的应用中，执行单元可以被限制回到较慢的速率以降低执行单元的功耗。当执行单元以比多线程发布单元更快的速度进行计时时，允许发布单元每循环发出更多指令，而不是执行单元被限制到较慢的速率以增加总体指令吞吐量。

64. 发明申请

US20090182944A1 Processing Unit Incorporating L1 Cache Bypass 失效
标题翻译：结合L1缓存旁路的处理单元
公开(公告)号：US20090182944A1
公开(公告)日：2009-07-16
申请号：US11972221
申请日：2008-01-10
申请人： Miguel Comparan , Eric Oliver Mejdrich , Adam James Muff
发明人： Miguel Comparan , Eric Oliver Mejdrich , Adam James Muff
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F12/0811
摘要： A circuit arrangement and method bypass the storage of requested data in a higher level cache of a multi-level memory architecture during the return of the requested data to a requester, while caching the requested data in a lower level cache. For certain types of data, e.g., data that is only used once and/or that is rarely modified or written back to memory, bypassing storage in a higher level cache reduces the likelihood of the requested data casting out frequently used data from the higher level cache. By caching the data in a lower level cache, however, the lower level cache can still snoop data requests and return requested data in the event the data is already cached in the lower level cache.
摘要翻译：在将所请求的数据返回到请求者的同时，在将所请求的数据缓存在较低级别的高速缓存中的同时，电路装置和方法将所请求的数据的存储绕过多层存储器体系结构的更高级缓存。对于某些类型的数据，例如仅使用一次和/或很少被修改或写回存储器的数据，绕过较高级别高速缓存中的存储降低了请求的数据从较高级别投出常用数据的可能性缓存。然而，通过将数据缓存在较低级别的缓存中，低级缓存仍然可以窥探数据请求，并在数据已经缓存在较低级别缓存中的情况下返回请求的数据。

65. 发明申请

US20090063608A1 Full Vector Width Cross Product Using Recirculation for Area Optimization 审中-公开
标题翻译：全矢量宽度交叉产品使用再循环进行区域优化
公开(公告)号：US20090063608A1
公开(公告)日：2009-03-05
申请号：US11849495
申请日：2007-09-04
申请人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
发明人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
IPC分类号： G06F7/32
CPC分类号： G06F17/16 , G06F9/30014 , G06F9/30036 , G06F9/3824 , G06F9/3826 , G06F9/3885 , G06T15/005
摘要： Embodiments of the invention are generally related to the field of image processing, and more specifically to vector units for supporting image processing. A vector unit may comprise a plurality of operand multiplexers associated with each vector processing lane of the vector unit. The operand multiplexers may select vector operands from one or more register files for performing a cross product operation. A first multiply operation may be performed in a first pipeline stage by multiplying a first set of operands in a multiplier. In a second pipeline stage, a second multiply operation may be performed by multiplying a second set of operands. The results of the first multiply operation and the second multiply operation may be transferred to an adder to complete the cross product instruction.
摘要翻译：本发明的实施例通常涉及图像处理领域，更具体地涉及用于支持图像处理的矢量单元。矢量单元可以包括与矢量单元的每个矢量处理通道相关联的多个操作数复用器。操作数复用器可以从一个或多个寄存器文件中选择矢量操作数，以执行交叉产品操作。可以在第一流水线级中通过乘法乘法器中的第一组操作数来执行第一乘法运算。在第二流水线级中，可以通过乘以第二组操作数来执行第二乘法运算。可以将第一乘法运算和第二乘法运算的结果传送到加法器以完成交叉乘积指令。

66. 发明申请

US20080126745A1 Operand Multiplexor Control Modifier Instruction in a Fine Grain Multithreaded Vector Microprocessor 审中-公开
标题翻译：精细多线程向量微处理器中的操作数多路复用器控制修改器指令
公开(公告)号：US20080126745A1
公开(公告)日：2008-05-29
申请号：US11925278
申请日：2007-10-26
申请人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
发明人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
IPC分类号： G06F15/76
CPC分类号： G06T1/20
摘要： The present invention is generally related to integrated circuit devices, and more particularly, to methods, systems and design structures for the field of image processing, and more specifically to an instruction set for processing images. Vector processing may involve rearranging vector operands in one or more source registers prior to performing vector operations. Typically, rearranging of operands in source registers is done by issuing a plurality of permute instructions that require excessive usage of temporary registers. Furthermore, the permute instructions may cause dependencies between instructions executing in a pipeline, thereby adversely affecting performance. Embodiments of the invention provide a level of muxing between a register file and a vector unit that allow for rearrangement of vector operands in source registers prior to providing the operands to the vector unit, thereby obviating the need for permute instructions.
摘要翻译：本发明通常涉及集成电路装置，更具体地涉及图像处理领域的方法，系统和设计结构，更具体地涉及用于处理图像的指令集。矢量处理可以包括在执行向量操作之前在一个或多个源寄存器中重新排列向量操作数。通常，通过发出需要临时寄存器过度使用的多个置换指令来完成源寄存器中操作数的重新排列。此外，置换指令可能导致在流水线中执行的指令之间的相关性，从而不利地影响性能。本发明的实施例提供了一种在寄存器文件和向量单元之间的复用水平，其允许在将操作数提供给向量单元之前重新排列源寄存器中的向量操作数，从而避免了对置换指令的需要。

67. 发明申请

US20080079713A1 Area Optimized Full Vector Width Vector Cross Product 审中-公开
标题翻译：区域优化全矢量宽度矢量交叉乘积
公开(公告)号：US20080079713A1
公开(公告)日：2008-04-03
申请号：US11536156
申请日：2006-09-28
申请人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
发明人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
IPC分类号： G06T1/00
CPC分类号： G06T15/06 , G06T2200/28
摘要： The present invention is generally related to the field of image processing, and more specifically to vector units for supporting image processing. A dual vector unit implementation is described wherein two vector units are configured receive data from a common register file. The vector units may independently and simultaneously process instructions. Furthermore, the vector units may be adapted to perform scalar operations thereby integrating the vector and scalar processing. The vector units may also be configured to share resources to perform an operation, for example, a cross product operation.
摘要翻译：本发明通常涉及图像处理领域，更具体地涉及用于支持图像处理的矢量单元。描述了双向量单元实现，其中配置了两个向量单元从公共寄存器文件接收数据。向量单元可以独立地并且同时处理指令。此外，矢量单元可以适于执行标量运算，从而整合向量和标量处理。矢量单元还可以被配置为共享资源以执行操作，例如交叉产品操作。

68. 发明授权

US07234017B2 Computer system architecture for a processor connected to a high speed bus transceiver 有权
标题翻译：用于连接到高速总线收发器的处理器的计算机系统架构
公开(公告)号：US07234017B2
公开(公告)日：2007-06-19
申请号：US11064745
申请日：2005-02-24
申请人： Giora Biran , Matthew Adam Cushing , Robert Allen Drehmel , Allen James Gavin , Mark E. Kautzman , Jamie Randall Kuesel , Ming-I Mark Lin , David Arnold Luick , James Anthony Marcella , Mark Owen Maxson , Eric Oliver Mejdrich , Adam James Muff , Clarence Rosser Ogilvie , Charles S. Woodruff
发明人： Giora Biran , Matthew Adam Cushing , Robert Allen Drehmel , Allen James Gavin , Mark E. Kautzman , Jamie Randall Kuesel , Ming-I Mark Lin , David Arnold Luick , James Anthony Marcella , Mark Owen Maxson , Eric Oliver Mejdrich , Adam James Muff , Clarence Rosser Ogilvie , Charles S. Woodruff
IPC分类号： G06F13/36
CPC分类号： G06F13/4059
摘要： A high speed computer processor system has a high speed interface for a graphics processor. A preferred embodiment combines a PowerPC microprocessor called the Giga-Processor Ultralite (GPUL) 110 from International Business Machines Corporation (IBM) with a high speed interface on a multi-chip module.
摘要翻译：高速计算机处理器系统具有用于图形处理器的高速接口。优选实施例将来自国际商业机器公司（IBM）的称为Giga-Processor Ultralite（GPUL）110的PowerPC微处理器与多芯片模块上的高速接口相结合。

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