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    • 64. 发明申请
    • CLOCK GENERATOR, PULSE GENERATOR UTILIZING THE CLOCK GENERATOR, AND METHODS THEREOF
    • 时钟发生器,利用时钟发生器的脉冲发生器及其方法
    • US20110194575A1
    • 2011-08-11
    • US13091154
    • 2011-04-21
    • Hong-Ching ChenChang-Po Ma
    • Hong-Ching ChenChang-Po Ma
    • H01S3/10H03H11/26
    • H03K5/15013G06F1/06G06F1/10
    • A clock generator for generating a target clock signal, comprising: a control circuit, receiving a reference clock signal, and for generating a clock enable signal and a delay selecting signal according to the reference clock signal; a delay module, coupled to the control circuit, for delaying the reference clock signal according to the delay selecting signal to generate a delayed reference clock signal; and a clock gating unit, coupled to the delay module and the control circuit, for receiving the delayed reference clock signal and the clock enable signal, and for passing the delayed reference clock signal according to the clock enable signal, to generate the target clock signal.
    • 一种用于产生目标时钟信号的时钟发生器,包括:控制电路,接收参考时钟信号,并用于根据参考时钟信号产生时钟使能信号和延迟选择信号; 延迟模块,耦合到所述控制电路,用于根据所述延迟选择信号延迟所述参考时钟信号以产生延迟的参考时钟信号; 以及时钟门控单元,耦合到延迟模块和控制电路,用于接收延迟的参考时钟信号和时钟使能信号,并且用于根据时钟使能信号传送延迟的参考时钟信号,以产生目标时钟信号 。
    • 67. 发明申请
    • FLASH DEVICE AND METHOD FOR IMPROVING PERFORMANCE OF FLASH DEVICE
    • 用于提高闪存器件性能的闪存器件和方法
    • US20100077134A1
    • 2010-03-25
    • US12481764
    • 2009-06-10
    • Hong-Ching CHEN
    • Hong-Ching CHEN
    • G06F12/00G06F12/02
    • G11C16/10
    • The invention provides a flash device. In one embodiment, the flash device comprises a first NAND flash integrated circuit, a second NAND flash integrated circuit, and a control integrated circuit. The control integrated circuit generates a plurality of first access signals with first timings to access the first NAND flash IC, and generates a plurality of second access signals with second timings to access the second NAND flash IC, wherein the first timings are different from the second timings. The first NAND flash integrated circuit then accesses data stored therein according to the first access signals. The second NAND flash integrated circuit then accesses data stored therein according to the second access signals.
    • 本发明提供一种闪光装置。 在一个实施例中,闪存器件包括第一NAND闪存集成电路,第二NAND闪存集成电路和控制集成电路。 控制集成电路产生具有第一定时的多个第一存取信号以访问第一NAND闪存IC,并且产生具有第二定时的多个第二存取信号以访问第二NAND闪存IC,其中第一定时不同于第二 时间 然后,第一NAND闪存集成电路根据第一接入信号访问存储在其中的数据。 然后,第二NAND闪存集成电路根据第二访问信号访问存储在其中的数据。
    • 69. 发明授权
    • Phase locked loop for generating an output signal
    • 用于产生输出信号的锁相环
    • US07274636B2
    • 2007-09-25
    • US10905132
    • 2004-12-17
    • Hong-Ching ChenWen-Yi Wu
    • Hong-Ching ChenWen-Yi Wu
    • G11B7/00
    • G11B27/24G11B20/10425G11B20/1403G11B2220/216G11B2220/218G11B2220/2562H03L7/085H03L7/0891H03L7/191
    • A phase locked loop (PLL) for generating an output signal according to an input signal is disclosed. The PLL of the present invention includes a detector for generating a detection signal according to the logical difference between the input signal and a feedback signal, a signal mixer electrically connected to the detector for generating a control signal according to the detection signal and a mixing reference signal, a filtering device electrically connected to the signal mixer for generating an adjust signal according to the control signal, a controllable oscillator electrically connected to the filtering device for generating the output signal according to the adjust signal, and a frequency divider electrically connected to the controllable oscillator for generating the feedback signal and the mixing reference signal according to the output signal. The frequency of the output signal is at least twice the frequency of the input signal.
    • 公开了一种用于根据输入信号产生输出信号的锁相环(PLL)。 本发明的PLL包括:检测器,用于根据输入信号和反馈信号之间的逻辑差产生检测信号;电连接到检测器的信号混合器,用于根据检测信号产生控制信号;以及混频参考 信号,电连接到所述信号混合器的滤波装置,用于根据所述控制信号产生调整信号;电连接到所述滤波装置的可控振荡器,用于根据所述调整信号产生所述输出信号;以及分频器,电连接到所述滤波装置, 可控振荡器,用于根据输出信号产生反馈信号和混合参考信号。 输出信号的频率至少是输入信号频率的两倍。