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61. 发明申请

US20220155361A1 IMAGE TEST SYSTEM, TEST ASSEMBLY AND IMAGE CAPTURE CARD 有权
公开(公告)号：US20220155361A1
公开(公告)日：2022-05-19
申请号：US17472746
申请日：2021-09-13
申请人： King Yuan Electronics Co., Ltd.
发明人： Pin-Yan TSAI , Kuang-Che CHENG
IPC分类号： G01R31/26 , G01R31/308 , G01R31/28
摘要： An image test system includes a test assembly and an image capture card. The test assembly is provided for obtaining a test signal from a test object, and includes an interface conversion circuit for converting signal transmission form of the test signal. The image capture card is provided for obtaining the test signal from the test assembly, and obtaining an image data from the test signal. The image test system further includes a test signal clock generation circuit for obtaining a test signal clock from the test signal, or the image capture card further includes a pair of clock input pins for obtaining the test signal clock directly from the test object.

62. 发明授权

US09116064B2 Structure of built-in self-test for pressure tester and method thereof 有权
标题翻译：压力测试仪内置自检结构及其方法
公开(公告)号：US09116064B2
公开(公告)日：2015-08-25
申请号：US13728915
申请日：2012-12-27
申请人： King Yuan Electronics Co., LTD
发明人： Wei-Jen Cheng
IPC分类号： G01L27/00
CPC分类号： G01L27/00
摘要： A built-in self-test structure for a pressure tester and a method thereof are provided. The built-in self-test structure includes a substrate, a plurality of membrane layers, a fixing portion, an electrical heating unit and a sensing circuit unit. The membrane layers are formed on the substrate. The fixing portion is configured on the membrane layers and includes a notch. The notch and the membrane layers define a cavity. The electrical heating unit is configured on one membrane layer, and the sensing circuit unit is configured on another membrane layer. The electrical heating unit heats up to increase the pressure in the cavity according to an input voltage, so that the membrane layers have a small deformation. The sensing circuit unit outputs a test signal according to the small deformation.
摘要翻译：提供了一种用于压力测试仪的内置自检结构及其方法。内置的自检结构包括基板，多个膜层，固定部，电加热单元和感测电路单元。膜层形成在基板上。固定部构造在膜层上并且包括凹口。凹口和膜层限定一个空腔。电加热单元配置在一个膜层上，感测电路单元配置在另一个膜层上。电加热单元根据输入电压加热以增加空腔中的压力，使得膜层具有小的变形。感测电路单元根据小的变形输出测试信号。

63. 发明授权

US08751178B2 Method and apparatus for determining disposition of via hole on printed circuit board 有权
标题翻译：用于确定印刷电路板上的通孔的布置的方法和装置
公开(公告)号：US08751178B2
公开(公告)日：2014-06-10
申请号：US13233121
申请日：2011-09-15
申请人： Ming-Chin Tsai
发明人： Ming-Chin Tsai
IPC分类号： G01N37/00
CPC分类号： H05K3/0005 , H05K1/0262 , H05K1/115 , H05K2201/093 , H05K2201/09663
摘要： A method for determining disposition of via hole on printed circuit board (PCB) includes the steps of: providing a PCB on which is disposed with a geometric layout and a via hole; providing a line on the PCB for intersecting the geometric layout to form a plurality of points of intersection; defining line segments by segmenting the line at each of the points of intersection to form a plurality of line segments; deleting some of the line segments having one end not being point of intersection for the geometric layout to form a plurality of segmented regions; searching a closed region by repeatedly searching region from any one of the points in the plurality of segmented regions; determining whether a closed region is a smallest closed region; determining whether a via hole is located within the smallest closed region.
摘要翻译：一种用于确定印刷电路板（PCB）上的通孔布置的方法包括以下步骤：提供PCB，其上布置有几何布局和通孔; 在PCB上提供与几何布局相交的线以形成多个交点; 通过在每个相交点处分割线来定义线段以形成多个线段; 删除一些线段，其一端不是几何布局的交点，以形成多个分段区域; 通过从所述多个分割区域中的任一点反复搜索区域来搜索封闭区域; 确定封闭区域是否是最小的封闭区域; 确定通孔是否位于最小封闭区域内。

64. 发明申请

US20140083158A1 STRUCTURE OF BUILT-IN SELF-TEST FOR PRESSURE TESTER AND METHOD THEREOF 有权
标题翻译：用于压力测试仪的内置自检结构及其方法
公开(公告)号：US20140083158A1
公开(公告)日：2014-03-27
申请号：US13728915
申请日：2012-12-27
申请人： KING YUAN ELECTRONICS CO., LTD
发明人： Wei-Jen Cheng
IPC分类号： G01L27/00
CPC分类号： G01L27/00
摘要： A built-in self-test structure for a pressure tester and a method thereof are provided. The built-in self-test structure includes a substrate, a plurality of membrane layers, a fixing portion, an electrical heating unit and a sensing circuit unit. The membrane layers are formed on the substrate. The fixing portion is configured on the membrane layers and includes a notch. The notch and the membrane layers define a cavity. The electrical heating unit is configured on one membrane layer, and the sensing circuit unit is configured on another membrane layer. The electrical heating unit heats up to increase the pressure in the cavity according to an input voltage, so that the membrane layers have a small deformation. The sensing circuit unit outputs a test signal according to the small deformation.
摘要翻译：提供了一种用于压力测试仪的内置自检结构及其方法。内置的自检结构包括基板，多个膜层，固定部，电加热单元和感测电路单元。膜层形成在基板上。固定部构造在膜层上并且包括凹口。凹口和膜层限定一个空腔。电加热单元配置在一个膜层上，感测电路单元配置在另一个膜层上。电加热单元根据输入电压加热以增加空腔中的压力，使得膜层具有小的变形。感测电路单元根据小的变形输出测试信号。

65. 发明授权

US08248090B2 ZIF connectors and semiconductor testing device and system using the same 有权
标题翻译： ZIF连接器和半导体测试装置和系统使用相同
公开(公告)号：US08248090B2
公开(公告)日：2012-08-21
申请号：US12413553
申请日：2009-03-28
申请人： Cheng-Chin Ni , Pei-Luen Hsu
发明人： Cheng-Chin Ni , Pei-Luen Hsu
IPC分类号： G01R31/00
CPC分类号： G01R1/0416 , H01R2201/20
摘要： A ZIF connector and a semiconductor testing device using the ZIF connectors are provided. The ZIF connector comprises a body portion and a clamping portion. The body portion is a print circuit board provided with circuit patterns, and further comprises a plurality of signal holes disposed on an upper part of the body portion for electrically connecting a plurality of corresponding signal cables, and a plurality of electrical terminals disposed on a lower part of the body portion and arranged on two lateral sides of the body portion for electrically connecting a plurality of corresponding electrical pads of a substrate. The circuit patterns are provided in the body portion to connect to the electrical terminals through the signal holes accordingly. The clamping portion is horizontally extended on one lateral side of the body portion for securing the ZIF connector in a connector board.
摘要翻译：提供ZIF连接器和使用ZIF连接器的半导体测试装置。 ZIF连接器包括主体部分和夹紧部分。主体部分是设置有电路图案的印刷电路板，并且还包括多个信号孔，其设置在主体部分的上部，用于电连接多个相应的信号电缆，以及设置在下部的多个电端子主体部分的一部分并且布置在主体部分的两个侧面上，用于电连接衬底的多个对应的电焊盘。电路图案设置在主体部分中，以通过信号孔相应地连接到电气端子。夹持部分在主体部分的一个侧面上水平延伸，用于将ZIF连接器固定在连接器板中。

66. 发明申请

US20120206157A1 Structure of burn-in oven 审中-公开
标题翻译：老化炉结构
公开(公告)号：US20120206157A1
公开(公告)日：2012-08-16
申请号：US13137802
申请日：2011-09-14
申请人： Yen-Chang Liu
发明人： Yen-Chang Liu
IPC分类号： G01R31/10
CPC分类号： G01R31/2862 , G01R31/2875
摘要： An improved structure of a burn-in oven includes a housing, a loading support, a cooling-fan assembly, and a motor-fan assembly. A circuit-board-space and an exhaust channel are defined inside of the housing, wherein the exhaust channel is provided with a plurality of venting holes such that the circuit-board-space and the exhaust channel are communicated with each other through the venting holes. The loading support is disposed in the circuit-board-space for loading a plurality of circuit boards. The cooling-fan assembly is arranged at one side of the loading support and beside the exhaust channel. The motor-fan assembly is arranged at the exhaust channel. Thereby, a phenomenon of heat accumulation locally at a back panel side of the oven can be improved so as to enhance cooling effect of the oven, let alone the number of fans installed on the oven can be decreased.
摘要翻译：老化炉的改进结构包括壳体，装载支架，冷却风扇组件和电动机 - 风扇组件。电路板空间和排气通道限定在壳体的内部，其中，排气通道设置有多个排气孔，使得电路板空间和排气通道通过排气孔彼此连通。负载支撑件设置在用于装载多个电路板的电路板空间中。冷却风扇组件布置在负载支撑件的一侧并且在排气通道旁边。电机风扇组件布置在排气通道处。因此，可以提高局部在烘箱的后面板侧的热积聚现象，从而提高烤箱的冷却效果，更不用说可以减少安装在烤箱上的风扇的数量。

67. 发明授权

US08193819B2 Method and apparatus for improving yield ratio of testing 有权
标题翻译：提高试验屈服比的方法和装置
公开(公告)号：US08193819B2
公开(公告)日：2012-06-05
申请号：US12610270
申请日：2009-10-30
申请人： Wei-Ping Wang , Hsuan-Chung Ko
发明人： Wei-Ping Wang , Hsuan-Chung Ko
IPC分类号： G01R27/28
CPC分类号： G01R31/2894 , G01R31/2879
摘要： A method and apparatus for improving yield ratio of testing are disclosed. The method includes the following steps. First of all, devices are tested and electromagnetic interference is measured. Next, the test results are examined for whether the devices pass the test or not. Then, electromagnetic interference data are examined for whether the electromagnetic interference data are over a predetermined standard if the devices fail the test. The above-mentioned steps are performed again if the electromagnetic interference data are over a predetermined standard. The test is terminated if the devices still fail the test and the values of electromagnetic interference are still over a predetermined standard.
摘要翻译：公开了一种用于提高测试屈服比的方法和装置。该方法包括以下步骤。首先，测试设备并测量电磁干扰。接下来，检查测试结果是否通过测试。然后，如果设备未通过测试，则检查电磁干扰数据是否超过预定标准。如果电磁干扰数据超过预定标准，则再次执行上述步骤。如果设备仍然测试失败并且电磁干扰值仍然超过预定标准，则测试终止。

68. 发明授权

US08030944B2 Method for continuity test of integrated circuit 有权
标题翻译：集成电路连续性测试方法
公开(公告)号：US08030944B2
公开(公告)日：2011-10-04
申请号：US12143557
申请日：2008-06-20
申请人： Cheng-Chin Ni
发明人： Cheng-Chin Ni
IPC分类号： G01R31/02 , G01R31/28
CPC分类号： G01R31/2853 , G01R31/026
摘要： The present invention provides a method for continuity test of integrated circuit. By using both pins of integrated circuit to measure a current of an electrostatic discharge device, the contact resistance of the integrated circuit can be obtained by calculating. The method comprises the steps: First, a DUT (device under test) is provided, and the DUT includes a second pin and the second pin connecting zero reference potential. Then, a voltage is applied to a first pin of DUT. Finally, the current through said first pin and said second pin would be measured. Therefore, the testing result of the DUT could be more precise and the quality of the DUT would be made sure.
摘要翻译：本发明提供一种集成电路的连续性测试方法。通过使用集成电路的两个引脚来测量静电放电装置的电流，可以通过计算获得集成电路的接触电阻。该方法包括以下步骤：首先，提供DUT（待测设备），DUT包括第二引脚，第二引脚连接零参考电位。然后，将电压施加到DUT的第一引脚。最后，将测量通过所述第一引脚和所述第二引脚的电流。因此，DUT的测试结果可能更精确，并且可以确保DUT的质量。

69. 发明授权

US08009896B2 Coplanarity inspection device for printed circuit boards 有权
标题翻译：印刷电路板共面检查装置
公开(公告)号：US08009896B2
公开(公告)日：2011-08-30
申请号：US12073285
申请日：2008-03-04
申请人： Chiu-Fang Chang
发明人： Chiu-Fang Chang
IPC分类号： G06K9/00
CPC分类号： G01B11/306
摘要： A coplanarity inspection device for a printed circuit board includes a base, a supporting disk, a driver, a printed circuit board, a light source, an image acquisition means, and a controller. The supporting disk is arranged on the base, and the driver rotates the supporting disk. The printed circuit board is placed on the supporting disk, and includes a to-be measured side facing downward. The light source projects light beams on the to-be measured side of the printed circuit board. The image acquisition means aims at a specific area of the to-be measured side for image acquisition. The controller is to control the driver, and to store image taken by the image acquisition means. As such, the coplanarity inspection device for a printed circuit board can be employed to inspect whether the coplanarity of the printed circuit board satisfies the standard of setting values in a certain range.
摘要翻译：用于印刷电路板的共平面检查装置包括基座，支撑盘，驱动器，印刷电路板，光源，图像获取装置和控制器。支撑盘布置在基座上，驱动器旋转支撑盘。印刷电路板被放置在支撑盘上，并且包括朝向下方的待测量侧。光源将待测光侧的光束投射到印刷电路板的一侧。图像获取装置针对要被测量侧的特定区域进行图像采集。控制器是控制驱动器，并存储由图像获取装置拍摄的图像。因此，可以使用用于印刷电路板的共面性检查装置来检查印刷电路板的共面性是否满足一定范围内的设定值的标准。

70. 发明授权

US07890820B2 Semiconductor test system with self-inspection of memory repair analysis 有权
标题翻译：半导体测试系统具有自检内存修复分析
公开(公告)号：US07890820B2
公开(公告)日：2011-02-15
申请号：US12585016
申请日：2009-09-01
申请人： Chia-Ching Peng
发明人： Chia-Ching Peng
IPC分类号： G11C29/00
CPC分类号： G11C29/44 , G11C29/02 , G11C29/4401
摘要： A semiconductor test system with self-inspection of memory repair analysis is disclosed, comprising a memory repair analysis device, an analysis fail memory and a self-inspection controller. The self-inspection controller controls storing a set of simulated fail bit addresses and a set of simulated repair line addresses, provided from outside, into the analysis fail memory in advance, controls the memory repair analysis device to execute a particular repair analysis operation with respect to the set of simulated fail bit addresses to produce repair line address information, and compares the repair line address information, obtained after calculation, directly with the set of simulated repair line addresses in the analysis fail memory. Thus, before physically proceeding with the operation of testing, the invention is capable of self-inspecting if there is an abnormal condition of the memory repair analysis device and the analysis fail memory contained therein.
摘要翻译：公开了一种具有记忆修复分析自检的半导体测试系统，包括存储器修复分析设备，分析失败存储器和自检控制器。自检控制器控制存储从外部提供的一组模拟故障位地址和一组模拟修复线地址到预先分析故障存储器中，控制存储器修复分析设备执行特定的修复分析操作到一组模拟故障位地址以产生修理线地址信息，并将计算后获得的修复线地址信息与分析失败存储器中的一组模拟维修线地址直接进行比较。因此，在物理进行测试操作之前，如果存储器修复分析装置的异常状况和其中包含的分析失败存储器，本发明能够进行自检。

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