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    • 61. 发明授权
    • Configurable nanoscale crossbar electronic circuits made by electrochemical reaction
    • 通过电化学反应制造的可配置的纳米级横梁电子电路
    • US06891744B2
    • 2005-05-10
    • US10289703
    • 2002-11-06
    • Yong ChenR. Stanley Williams
    • Yong ChenR. Stanley Williams
    • G11C13/02G11C13/00H01L21/31H01L21/44
    • G11C13/0009B82Y10/00G11C13/025G11C2213/34G11C2213/77G11C2213/81Y10S438/957Y10S977/936
    • Configurable electronic circuits comprise arrays of cross-points of one layer of metal/semiconductive nanoscale lines crossed by a second layer of metal/semiconductive nanoscale lines, with a configurable layer between the lines. Methods are provided for altering the thickness and/or resistance of the configurable layer by oxidation or reduction methods, employing a solid material as the configurable layer. Specifically a method is provided for configuring nanoscale devices in a crossbar array of configurable devices comprising arrays of cross-points of a first layer of nanoscale lines comprising a first metal or a first semiconductor material crossed by a second layer of nanoscale lines comprising a second metal or a second semiconductor material. The method comprises: (a) forming the first layer on a substrate; (b) forming a solid phase of a configurable material on the first layer at least in areas where the second layer is to cross the first layer; (c) forming the second layer on the configurable material, over the first layer; and (d) changing a property of the configurable material to thereby configure the nanoscale devices.
    • 可配置电子电路包括由第二层金属/半导体纳米级线交叉的一层金属/半导体纳米级线的交叉点阵列,其中线之间具有可配置层。 提供了通过使用固体材料作为可配置层的氧化或还原方法来改变可配置层的厚度和/或电阻的方法。 具体地,提供一种用于在可配置设备的交叉开关阵列中配置纳米级器件的方法,其包括第一纳米级线层的交点的阵列,其包括第一金属或第一半导体材料,所述第一金属或第一半导体材料由第二纳米级线交叉,所述第二金属或第二半导体材料包括第二金属 或第二半导体材料。 该方法包括:(a)在衬底上形成第一层; (b)至少在所述第二层与所述第一层交叉的区域中,在所述第一层上形成可配置材料的固相; (c)在所述可配置材料上形成在所述第一层上的所述第二层; 和(d)改变可配置材料的特性,从而配置纳米级器件。
    • 62. 发明申请
    • Storage device
    • 储存设备
    • US20050097257A1
    • 2005-05-05
    • US10851897
    • 2004-05-21
    • Minoru IshidaKatsuhisa ArataniAkira Kouchiyama
    • Minoru IshidaKatsuhisa ArataniAkira Kouchiyama
    • G11C13/00G11C7/00G11C11/409G11C13/02G11C16/02H01L27/10G06F12/00
    • G11C13/0011G11C13/0064G11C13/0069G11C16/3459G11C2013/009
    • A storage device comprises a memory element and an applying means for applying a voltage to the memory element wherein the memory element changes its characteristic to record thereon information with application of a voltage to the memory element by the applying means, the memory element further changing its characteristic when the same information is recorded on the memory element continuously. The memory element has a recording method which comprises the steps of detecting content of information that has already been recorded on the memory element when the information is recorded, comparing the information that has already been recorded on the memory element with information to be recorded on the memory element, applying a voltage to the memory element to make an ordinary information recording process if the two information are different from each other and disabling the ordinary information recording process when the two information are identical to each other. Thus, the storage device according to the present invention can satisfactorily carry out recording operations even when information is recorded continuously.
    • 存储装置包括存储元件和用于向存储元件施加电压的施加装置,其中存储元件改变其特性以便通过施加装置向存储元件施加电压来记录信息,存储元件进一步改变其 当相同的信息被连续记录在存储元件上时的特性。 存储元件具有记录方法,其包括以下步骤:当记录信息时已经记录在存储元件上的信息的内容,将已经记录在存储元件上的信息与要记录在存储元件上的信息进行比较 存储元件,如果两个信息彼此不同,则向存储元件施加电压以进行普通信息记录处理,并且当两个信息彼此相同时禁用普通信息记录处理。 因此,即使当连续记录信息时,根据本发明的存储装置也能令人满意地执行记录操作。
    • 63. 发明申请
    • NONVOLATILE MEMORY AND ERASING METHOD
    • 非易失性存储器和擦除方法
    • US20050093045A1
    • 2005-05-05
    • US10782916
    • 2004-02-23
    • Tsuyoshi Tsujioka
    • Tsuyoshi Tsujioka
    • G11C16/02G11C13/02G11C13/04H01L27/105H01L27/115H01L27/28H01L51/05G11C11/24
    • G11C13/041B82Y10/00G11C13/0014G11C13/02G11C13/04
    • There is provided a nonvolatile memory including memory cells each of which includes a storage element including a bistable molecular layer, wherein the bistable molecular layer contains a bistable molecule which brings about isomerization from a first isomer into a second isomer by injecting a hole and an electron into the bistable molecular layer, and brings about isomerization from the second isomer into the first isomer by irradiating the bistable molecular layer with erase light, and the memory is configured to irradiate the bistable molecular layers of all the memory cells with the erase light while applying an electric field to the bistable molecular layer of only a part of the memory cells that stores information to be held when erasing information stored in the rest of the memory cells.
    • 提供了包括存储单元的非易失性存储器,每个存储单元包括包含双稳态分子层的存储元件,其中双稳态分子层含有双稳态分子,其通过注入空穴和电子使第一异构体进一步异构化成第二异构体 进入双稳态分子层,通过用擦除光照射双稳态分子层,将异构化从第二异构体引入第一异构体,并且存储器被配置为在施加时用擦除光照射所有存储单元的双稳态分子层 仅存储单元的一部分的双稳态分子层的电场,其存储当擦除存储在其余存储单元中的信息时要保持的信息。
    • 65. 发明申请
    • AC sensing for a resistive memory
    • 用于电阻式存储器的交流感测
    • US20050078505A1
    • 2005-04-14
    • US10681161
    • 2003-10-09
    • Thomas Voshell
    • Thomas Voshell
    • G11C7/06G11C11/16G11C13/00G11C13/02G11C16/26G11C11/00
    • G11C13/0061G11C7/06G11C11/1673G11C13/0004G11C13/0011G11C13/004G11C2013/0054G11C2013/0057G11C2213/79
    • Alternating current is used to sense a logic state of a memory cell that has a resistive memory element. The memory element can be in an array and a memory device can include the array and peripheral circuitry for reading or sensing each memory cell in the array. The peripheral circuitry can include a clock/control circuit providing a control signal, which controls when a row of memory cells are sensed, a switching circuit for receiving a cellplate count signal and a bit count signal provided by the clock/control circuit, a cellplate line signal and a bit line signal from the memory cell, the switching circuit producing a first output signal and a second output signal, wherein one of the first output signal and the second output signal is at a supply voltage and the other of the first output signal and the second output signal alternates polarity with each sensing operation and a comparison circuit receiving the first output signal and the second output signal and outputting a signal corresponding to the logic sate of the memory cell.
    • 交流电用于检测具有电阻性存储元件的存储单元的逻辑状态。 存储器元件可以是阵列,并且存储器件可以包括用于读取或感测阵列中的每个存储器单元的阵列和外围电路。 外围电路可以包括提供控制信号的时钟/控制电路,该控制信号控制何时检测一行存储器单元,用于接收单元板计数信号的开关电路和由时钟/控制电路提供的位计数信号,单元板 所述开关电路产生第一输出信号和第二输出信号,其中所述第一输出信号和所述第二输出信号中的一个处于电源电压,并且所述第一输出中的另一个输出信号 信号和第二输出信号与每个感测操作交替极性,并且比较电路接收第一输出信号和第二输出信号,并输出与存储器单元的逻辑状态对应的信号。