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    • 61. 发明授权
    • Load drive circuit
    • 负载驱动电路
    • US09444447B2
    • 2016-09-13
    • US14972803
    • 2015-12-17
    • SANKEN ELECTRIC CO., LTD.
    • Yuta Ozono
    • H03B1/00H03K3/00H03K17/56H01F7/06
    • H03K17/56H01F7/064H02H11/002H02M2001/0025H03K17/08148H03K2217/0081
    • A switch electrically connected to a first terminal and a second terminal. A first comparator detects a load open state where the switch is off and a load is not connected to the second terminal. Upon detecting, a clamp circuit clamps the voltage of the second terminal to a clamp voltage higher than a first reference voltage and lower than an input voltage. A second comparator detects an output-to-supply short circuit state where the switch is off and the second terminal is connected to the power supply. A capacitor with one terminal connected to the second terminal and another terminal connected to a third terminal. A bootstrap circuit supplies a charge current to the third terminal at a constant voltage. A clamp voltage rise prevention circuit prevents the clamp voltage of the clamp circuit from rising, when the first comparator detects the load open state.
    • 电连接到第一端子和第二端子的开关。 第一比较器检测开关断开并且负载未连接到第二端子的负载打开状态。 检测时,钳位电路将第二端子的电压钳位到高于第一参考电压并低于输入电压的钳位电压。 第二比较器检测开关断开并且第二端子连接到电源的输出电源短路状态。 一个电容器,其一个端子连接到第二端子,另一个端子连接到第三端子。 自举电路以恒定电压向第三端提供充电电流。 当第一比较器检测到负载打开状态时,钳位电压上升防止电路防止钳位电路的钳位电压上升。
    • 62. 发明授权
    • Switching control circuit for target switching element
    • 目标开关元件的开关控制电路
    • US09444446B2
    • 2016-09-13
    • US14323562
    • 2014-07-03
    • DENSO CORPORATION
    • Junichi Fukuta
    • H03K3/00H03K17/16H03K17/082H03K17/687H03K3/012H03K17/56H03K19/0175
    • H03K17/168H03K3/012H03K17/0828H03K17/166H03K17/56H03K17/687H03K19/017509
    • In a switching control circuit, a determiner determines whether there is one of a first type of abnormality and a second type of abnormality different therefrom in a target switching element and/or the switching control circuit. A controller controls a second switching element to close a low-impedance discharge path for discharging a control terminal of the target switching element when it is determined that there is the first type of abnormality, and disables closing of a high-impedance discharge path for discharging the control terminal while the low-impedance discharge path is closed by the second switching element. The controller controls a third switching element to close the high-impedance discharge path when it is determined that there is the second type of abnormality; and disables closing of the low-impedance discharge path while the high-impedance discharge path is closed by the third switching element.
    • 在开关控制电路中,确定器确定在目标开关元件和/或开关控制电路中是否存在与其不同的第一类型的异常和第二类型的异常中的一种。 当确定存在第一类异常时,控制器控制第二开关元件以闭合用于对目标开关元件的控制端子进行放电的低阻抗放电路径,并且禁止关闭用于放电的高阻抗放电路径 控制端子,同时低阻抗放电路径被第二开关元件闭合。 当确定存在第二种类型的异常时,控制器控制第三开关元件以闭合高阻抗放电路径; 并且在高阻抗放电路径被第三开关元件闭合的同时禁止闭合低阻抗放电路径。
    • 66. 发明授权
    • Reverse current blocking comparator
    • 反向电流阻塞比较器
    • US09294080B2
    • 2016-03-22
    • US14228614
    • 2014-03-28
    • Fairchild Semiconductor Corporation
    • Tyler DaigleJulie Lynn Stultz
    • H03K17/56H03K17/06H02J7/00
    • H03K17/063H02J7/0029H03K2217/0018H03K2217/0054
    • An apparatus comprises at least one transistor configured as analog switch, a well biasing circuit configured to provide a dynamic electrical bias to a bulk region of the at least one transistor, and a comparator circuit in electrical communication with the well biasing circuit and the transistor. The comparator circuit is configured to detect a first operating condition of the transistor and a second operating condition of the transistor. The well biasing circuit is configured to apply a first electrical bias to the bulk region of a transistor when the first operating condition is detected and apply a second electrical bias to the bulk region of the transistor when the second operating condition is detected, and wherein the comparator is configured to apply hysteresis to detection of the first and second operating conditions.
    • 一种装置包括配置为模拟开关的至少一个晶体管,阱偏置电路,其被配置为向至少一个晶体管的体区提供动态电偏置,以及与阱偏置电路和晶体管电连通的比较器电路。 比较器电路被配置为检测晶体管的第一工作状态和晶体管的第二工作状态。 阱偏置电路被配置为当检测到第一操作条件时将第一电偏压施加到晶体管的主体区域,并且当检测到第二操作条件时将第二电偏压施加到晶体管的主体区域,并且其中, 比较器被配置为对第一和第二操作条件的检测应用滞后。
    • 70. 发明申请
    • CONSTANT PERIOD SIGNAL MONITORING CIRCUIT AND LOAD CONTROL BACKUP SIGNAL GENERATING CIRCUIT
    • 恒定周期信号监测电路和负载控制备用信号发生电路
    • US20150355250A1
    • 2015-12-10
    • US14729485
    • 2015-06-03
    • YAZAKI CORPORATION
    • Kazuhisa WATARU
    • G01R23/02H03K17/56
    • G01R23/02H03K17/56Y02T10/40
    • A constant period signal monitoring circuit for monitoring a constant period signal that is output periodically when a control processor operating according to a program is normal, includes a signal input terminal that receives the constant period signal, an edge detection section that detects a change of the constant period signal appearing at the signal input terminal from a low level to a high level or from a high level to a low level as an edge of the constant period signal, and a time measuring section that measures a length of the time during which a state of not detecting the edge continues on the basis of an output of the edge detection section and outputs an abnormality detection signal in a case that the measured time exceeds a threshold value.
    • 一种恒定周期信号监视电路,用于监视当根据程序操作的控制处理器是正常的周期性输出的恒定周期信号时,包括一个接收恒定周期信号的信号输入端,一个边缘检测部分, 恒定周期信号出现在信号输入端子处,从低电平到高电平,或者从高电平出现到恒定周期信号的边沿;时间测量部分,其测量时间长度, 基于边缘检测部的输出,不检测边缘的状态继续,并且在测量时间超过阈值的情况下输出异常检测信号。