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71. 发明申请

US20150134976A1 EVENT-BASED APPARATUS AND METHOD FOR SECURING BIOS IN A TRUSTED COMPUTING SYSTEM DURING EXECUTION 有权
标题翻译：基于事件的设备和在执行期间保护计算机系统中的BIOS的方法
公开(公告)号：US20150134976A1
公开(公告)日：2015-05-14
申请号：US14079145
申请日：2013-11-13
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry
IPC分类号： G06F21/57
CPC分类号： G06F21/572 , G06F9/4401 , G06F13/24 , G06F13/4282 , G06F21/554 , G06F2221/2107 , H04L9/06 , H04L9/0618 , H04L9/0869 , H04L9/3231 , H04L9/3242 , H04L63/0435 , H04L63/0876 , H04L63/123
摘要： An apparatus including a ROM, an event detector, and a tamper detector. The ROM has BIOS contents stored as plaintext, and an encrypted digest. The encrypted digest is an encrypted version of a first digest corresponding to the BIOS contents. The event detector generates an interrupt that interrupts operation of the system upon occurrence of an event. The tamper detector is operatively coupled to the ROM and accesses the BIOS contents and the encrypted digest upon assertion of the interrupt, and directs a microprocessor to generate a second digest corresponding to the BIOS contents and a decrypted digest corresponding to the encrypted digest using the same algorithms and key that were employed to generate the first digest and the encrypted digest, and compares the second message digest with the decrypted message digest, and precludes the operation of the microprocessor if the second digest and the decrypted digest are not equal.
摘要翻译：一种包括ROM，事件检测器和篡改检测器的装置。 ROM具有存储为明文的BIOS内容和加密摘要。加密摘要是对应于BIOS内容的第一摘要的加密版本。事件检测器产生中断事件发生时系统的操作。篡改检测器可操作地耦合到ROM，并且在断言中访问BIOS内容和加密的摘要，并引导微处理器生成对应于BIOS内容的第二摘要和对应于加密摘要的解密摘要用于生成第一摘要和加密摘要的算法和密钥，并将第二消息摘要与解密的消息摘要进行比较，并且如果第二摘要和解密的摘要不相等，则排除微处理器的操作。

72. 发明授权

US09018986B2 Output buffers 有权
标题翻译：输出缓冲区
公开(公告)号：US09018986B2
公开(公告)日：2015-04-28
申请号：US13745991
申请日：2013-01-21
申请人： VIA Technologies, Inc.
发明人： Yeong-Sheng Lee
IPC分类号： H03K3/00 , G05F3/24
CPC分类号： G05F3/24
摘要： An output buffer is provided. The output buffer is coupled to a first voltage source providing a first supply voltage and used for generating an output signal at an output terminal according to an input signal. The output buffer includes first and second transistors and a self-bias circuit. The first and second transistors are cascaded between the output terminal and a reference voltage. The self-bias circuit is coupled to the output terminal and the control electrode of the first transistor. When the output buffer does not receive the first supply voltage, the self-bias circuit provides a first bias voltage to the control electrode of the first transistor according to the output signal to decrease voltage differences between the control electrode and the input and output electrodes of the first transistor to be lower than a predetermined voltage.
摘要翻译：提供输出缓冲区。输出缓冲器耦合到提供第一电源电压并用于根据输入信号在输出端产生输出信号的第一电压源。输出缓冲器包括第一和第二晶体管和自偏置电路。第一和第二晶体管级联在输出端和参考电压之间。自偏置电路耦合到第一晶体管的输出端和控制电极。当输出缓冲器没有接收到第一电源电压时，自偏置电路根据输出信号向第一晶体管的控制电极提供第一偏置电压，以减小控制电极与输入和输出电极之间的电压差第一晶体管低于预定电压。

73. 发明申请

US20150112679A1 METHOD FOR BUILDING LANGUAGE MODEL, SPEECH RECOGNITION METHOD AND ELECTRONIC APPARATUS 有权
标题翻译：语言模型建立方法，语音识别方法和电子设备
公开(公告)号：US20150112679A1
公开(公告)日：2015-04-23
申请号：US14499261
申请日：2014-09-29
申请人： VIA Technologies, Inc.
发明人： Guo-Feng Zhang
IPC分类号： G10L15/06 , G10L15/00
CPC分类号： G10L15/187 , G10L15/063 , G10L15/14 , G10L15/26 , G10L2015/0633
摘要： A method for building a language model, a speech recognition method and an electronic apparatus are provided. The speech recognition method includes the following steps. Phonetic transcriptions of a speech signal are obtained from an acoustic model. Phonetic spellings matching the phonetic transcriptions are obtained according to the phonetic transcriptions and a syllable acoustic lexicon. According to the phonetic spellings, a plurality of text sequences and a plurality of text sequence probabilities are obtained from a language model. Each phonetic spelling is matched to a candidate sentence table; a word probability of each phonetic spelling matching a word in a sentence of the sentence table are obtained; and the word probabilities of the phonetic spellings are calculated so as to obtain the text sequence probabilities. The text sequence corresponding to a largest one of the sequence probabilities is selected as a recognition result of the speech signal.
摘要翻译：提供了一种构建语言模型，语音识别方法和电子设备的方法。语音识别方法包括以下步骤。从声学模型获得语音信号的语音转录。根据语音转录和音节声学词典获得与语音转录匹配的拼音。根据语音拼写，从语言模型中获得多个文本序列和多个文本序列概率。每个语音拼写与候选句表匹配; 获得与句子表的句子中的单词匹配的每个语音拼写的单词概率; 并计算语音拼写的单词概率，以获得文本序列概率。选择与序列概率中最大的一个对应的文本序列作为语音信号的识别结果。

74. 发明授权

US09009380B2 USB transaction translator with SOF timer and USB transaction translation method for periodically sending SOF packet 有权
标题翻译：具有SOF定时器的USB事务转换器和用于周期性发送SOF数据包的USB事务转换方法
公开(公告)号：US09009380B2
公开(公告)日：2015-04-14
申请号：US14038717
申请日：2013-09-26
申请人： VIA Technologies, Inc.
发明人： Jiin Lai , Chin-Sung Hsu , Terrance Shiyang Shih , Jinkuan Tang , Buheng Xu , Hui Jiang
IPC分类号： G06F13/36 , G06F13/40
CPC分类号： G06F13/4059
摘要： A universal serial bus (USB) transaction translator is provided along with a micro-frame synchronization method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus. At least two buffers are configured to store data. A controller stores the data in the buffers alternately. A start-of-frame (SOF) counter is used to count the SOF packets, with the counting value of the SOF counter being compared to a predefined value. Specifically, the controller resets a SOF timer for sending the SOF packet when the counting value achieves or exceeds the predefined value, such that the SOF packet and an isochronous timestamp packet (ITP) from the host are sent at the same time. Further, the controller delays the sending of the SOF packet for a period of time according to the ITP from the host.
摘要翻译：提供通用串行总线（USB）事务转换器以及微帧同步方法。设备接口经由设备总线耦合到设备，并且主机接口经由主机总线耦合到主机。至少两个缓冲区被配置为存储数据。控制器交替地将数据存储在缓冲器中。使用起始帧（SOF）计数器对SOF数据包进行计数，将SOF计数器的计数值与预定义的值进行比较。具体地说，当计数值达到或超过预定值时，控制器复位用于发送SOF分组的SOF定时器，使得来自主机的SOF分组和等时时间戳分组（ITP）同时被发送。此外，控制器根据来自主机的ITP延迟SOF分组的发送一段时间。

75. 发明授权

US09007122B2 Digital power gating with state retention 有权
标题翻译：数字电源门控与状态保持
公开(公告)号：US09007122B2
公开(公告)日：2015-04-14
申请号：US14202275
申请日：2014-03-10
申请人： Via Technologies, Inc.
发明人： James R. Lundberg
IPC分类号： G05F1/10 , H03K17/22 , G06F1/32 , H03K19/00 , H03K17/16
CPC分类号： H03K17/22 , G06F1/3234 , G06F1/324 , G06F1/3243 , G06F1/3287 , G06F1/3296 , H03K17/16 , H03K19/0008 , H03K19/0016 , H03K2217/0036 , Y02D10/126 , Y02D10/152 , Y02D10/171 , Y02D10/172 , Y02D50/20
摘要： A digital power gating system for performing power gating to reduce a voltage of a gated supply bus to a state retention voltage level that reduces leakage current while retaining a digital state of a functional circuit. The power gating system includes gating devices and a power gating control system. Each gating device has current terminals coupled between a global supply bus and the gated supply bus, and a control terminal controlled by a bit of a digital control value. The power gating control system successively adjusts the digital control value to reduce a voltage of the gated supply bus to the state retention voltage level. Adjustment gain and/or adjustment periods may be changed, such as when the digital control value reaches certain values or when the gated supply reaches certain voltage levels. Various parameters are programmable to adjust for particular configurations or to achieve desired operation.
摘要翻译：一种用于执行电力门控以将门控电源总线的电压降低到保持功能电路的数字状态的同时降低漏电流的状态保持电压电平的数字电源门控系统。电源门控系统包括门控设备和电源门控控制系统。每个选通装置具有耦合在全局电源总线和门控电源总线之间的电流端子，以及由位数位控制值控制的控制端子。电源门控控制系统连续调整数字控制值，将门控电源总线的电压降至状态保持电压电平。可以改变调节增益和/或调整周期，例如当数字控制值达到某些值时或当门控电源达到一定的电压电平时。可以对各种参数进行编程以针对特定配置进行调整或实现期望的操作。

76. 发明申请

US20150067369A1 MULTI-CORE SYNCHRONIZATION MECHANISM 有权
标题翻译：多核同步机制
公开(公告)号：US20150067369A1
公开(公告)日：2015-03-05
申请号：US14281434
申请日：2014-05-19
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F1/04 , G06F1/32
CPC分类号： G06F1/3287 , G06F1/04 , G06F1/32 , G06F9/522 , G06F12/0891 , G06F2212/1028 , G06F2212/60
摘要： A microprocessor includes a control unit configured to selectively control a respective clock signal to each of a plurality of processing cores. Each of the processing cores is configured to separately write a value to the control unit. For each core of the plurality of processing cores, the control unit is configured to turn off the respective clock signal to the core in response to the core writing a value to the control unit. The control unit is configured to detect a condition has occurred when all of the processing cores have written a value to the control unit and the control unit has turned off the respective clock signal to all of the processing cores. The control unit is configured to simultaneously turn on the respective clock signal to all of the processing cores in response to detecting the condition has occurred.
摘要翻译：微处理器包括控制单元，该控制单元被配置为选择性地将各个时钟信号控制到多个处理核心中的每一个。每个处理核心被配置为分别向控制单元写入一个值。对于所述多个处理核心的每个核心，所述控制单元被配置为响应于所述核心向所述控制单元写入值而将相应的时钟信号关断到所述核心。控制单元被配置为检测当所有处理核心已经向控制单元写入值并且控制单元已经将各个时钟信号截止到所有处理核心时发生的状况。控制单元被配置为响应于检测到所发生的状况，同时将各个时钟信号接通到所有处理核心。

77. 发明申请

US20150067367A1 METHOD FOR REDUCING POWER CONSUMPTION IN ELECTRONIC APPARATUS 有权
标题翻译：降低电子设备功耗的方法
公开(公告)号：US20150067367A1
公开(公告)日：2015-03-05
申请号：US14057277
申请日：2013-10-18
申请人： VIA TECHNOLOGIES, INC.
发明人： Cheng-Ming HUANG
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3212 , Y02D10/126 , Y02D10/174
摘要： An electronic apparatus is provided. The electronic apparatus includes a serial advanced technology attachment (SATA) physical layer, a clock generator and a control unit. The SATA physical layer is configured to provide connection with an SATA device and perform data transmission with the SATA device is performed at a first clock frequency. The clock generator is configured to provide a clock signal having the first clock frequency to the SATA physical layer. When at least one specific event is detected by the control unit, the control unit controls the clock generator to provide the clock signal having a second clock frequency to the SATA physical layer, so that the SATA physical layer performs data transmission with the SATA device at the second clock frequency. The second clock frequency is lower than the first clock frequency.
摘要翻译：提供电子设备。电子设备包括串行高级技术附件（SATA）物理层，时钟发生器和控制单元。 SATA物理层配置为提供与SATA设备的连接并执行数据传输，SATA设备以第一时钟频率执行。时钟发生器被配置为向SATA物理层提供具有第一时钟频率的时钟信号。当由控制单元检测到至少一个特定事件时，控制单元控制时钟发生器以向SATA物理层提供具有第二时钟频率的时钟信号，使得SATA物理层与SATA设备进行数据传输第二个时钟频率。第二个时钟频率低于第一个时钟频率。

78. 发明申请

US20150067318A1 SELECTIVE DESIGNATION OF MULTIPLE CORES AS BOOTSTRAP PROCESSOR IN A MULTI-CORE MICROPROCESSOR 有权
标题翻译：多核指示器作为多核微处理器中的BOOTSTRAP处理器
公开(公告)号：US20150067318A1
公开(公告)日：2015-03-05
申请号：US14281709
申请日：2014-05-19
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry , Stephan Gaskins
IPC分类号： G06F9/44
CPC分类号： G06F9/3885 , G06F1/04 , G06F1/12 , G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/30032 , G06F9/30047 , G06F9/30079 , G06F9/30087 , G06F9/30105 , G06F9/30145 , G06F9/3802 , G06F9/3861 , G06F9/4403 , G06F9/4405 , G06F9/4411 , G06F9/4418 , G06F12/0808 , G06F12/084 , G06F12/0875 , G06F13/24 , G06F13/364 , G06F13/42 , G06F21/53 , G06F21/57 , G06F2212/452 , G06F2212/6028 , G06F2212/62 , H01L22/34 , H04L9/0877 , H04L9/0897 , Y02B70/12 , Y02B70/123 , Y02B70/126 , Y02B70/30 , Y02D10/10 , Y02D10/126 , Y02D10/128 , Y02D10/13 , Y02D10/171 , Y02D10/172 , Y02D10/30 , Y02D50/20
摘要： A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to sample the indicator. When the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate multiple of the plurality of processing cores to be a bootstrap processor. When the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate a single processing core of the plurality of processing cores to be the bootstrap processor.
摘要翻译：微处理器包括指示器和多个处理核心。多个处理核心中的每一个被配置为对指示器进行采样。当指示符指示第一预定值时，多个处理核被配置为将多个处理核中的多个共同指定为自举处理器。当指示符指示与第一预定值不同的第二预定值时，多个处理核被配置为将多个处理核中的单个处理核共同地指定为引导处理器。

79. 发明申请

US20150067306A1 INTER-CORE COMMUNICATION VIA UNCORE RAM 有权
标题翻译：内核通信通过核心RAM
公开(公告)号：US20150067306A1
公开(公告)日：2015-03-05
申请号：US14281551
申请日：2014-05-19
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker , Stephan Gaskins
IPC分类号： G06F9/30
CPC分类号： G06F9/3885 , G06F1/04 , G06F1/12 , G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/30032 , G06F9/30047 , G06F9/30079 , G06F9/30087 , G06F9/30105 , G06F9/30145 , G06F9/3802 , G06F9/3861 , G06F9/4403 , G06F9/4405 , G06F9/4411 , G06F9/4418 , G06F12/0808 , G06F12/084 , G06F12/0875 , G06F13/24 , G06F13/364 , G06F13/42 , G06F21/53 , G06F21/57 , G06F2212/452 , G06F2212/6028 , G06F2212/62 , H01L22/34 , H04L9/0877 , H04L9/0897 , Y02B70/12 , Y02B70/123 , Y02B70/126 , Y02B70/30 , Y02D10/10 , Y02D10/126 , Y02D10/128 , Y02D10/13 , Y02D10/171 , Y02D10/172 , Y02D10/30 , Y02D50/20
摘要： A microprocessor includes a plurality of processing cores and an uncore random access memory (RAM) readable and writable by each of the plurality of processing cores. Each core of the plurality of processing cores comprises microcode run by the core that implements architectural instructions of an instruction set architecture of the microprocessor. The microcode is configured to both read and write the uncore RAM to accomplish inter-core communication between the plurality of processing cores.
摘要翻译：微处理器包括多个处理核心和由多个处理核心中的每一个可读和写的非随机存取存储器（RAM）。多个处理核心的每个核心包括实现微处理器的指令集架构的架构指令的由核心运行的微代码。微码被配置为读取和写入非空白RAM以实现多个处理核之间的核心间通信。

80. 发明申请

US20150067301A1 MICROPROCESSOR WITH BOOT INDICATOR THAT INDICATES A BOOT ISA OF THE MICROPROCESSOR AS EITHER THE X86 ISA OR THE ARM ISA 有权
标题翻译：具有引导指示器的微处理器显示了作为X86 ISA或ARM ISA的微处理器的引导ISA
公开(公告)号：US20150067301A1
公开(公告)日：2015-03-05
申请号：US14526029
申请日：2014-10-28
申请人： VIA TECHNOLOGIES, INC.
发明人： G. GLENN HENRY , TERRY PARKS , RODNEY E. HOOKER
IPC分类号： G06F15/82 , G06F9/38 , G06F9/30
CPC分类号： G06F9/441 , G06F9/265 , G06F9/30043 , G06F9/30072 , G06F9/30076 , G06F9/30105 , G06F9/30123 , G06F9/30145 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/30196 , G06F9/3802 , G06F9/4401 , G06F9/4403 , G06F15/82
摘要： A microprocessor includes a plurality of registers that holds an architectural state of the microprocessor and an indicator that indicates a boot instruction set architecture (ISA) of the microprocessor as either the x86 ISA or the Advanced RISC Machines (ARM) ISA. The microprocessor also includes a hardware instruction translator that translates x86 ISA instructions and ARM ISA instructions into microinstructions. The hardware instruction translator translates, as instructions of the boot ISA, the initial ISA instructions that the microprocessor fetches from architectural memory space after receiving a reset signal. The microprocessor also includes an execution pipeline, coupled to the hardware instruction translator. The execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions. In response to the reset signal, the microprocessor initializes its architectural state in the plurality of registers as defined by the boot ISA prior to fetching the initial ISA instructions.
摘要翻译：微处理器包括保持微处理器架构状态的多个寄存器和指示微处理器的引导指令集体系结构（ISA）作为x86 ISA或高级RISC机器（ARM）ISA的指示符。微处理器还包括硬件指令转换器，将x86 ISA指令和ARM ISA指令转换为微指令。作为引导ISA的指令，硬件指令转换器将转换为接收复位信号后微处理器从架构存储器空间中提取的初始ISA指令。微处理器还包括耦合到硬件指令转换器的执行流水线。执行流水线执行微指令以生成由x86 ISA和ARM ISA指令定义的结果。响应于复位信号，微处理器在获取初始ISA指令之前初始化由引导ISA定义的多个寄存器中的架构状态。

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