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71. 发明申请

US20150108470A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20150108470A1
公开(公告)日：2015-04-23
申请号：US14515993
申请日：2014-10-16
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Shunpei Yamazaki , Shuhei Nagatsuka , Tatsuya Onuki , Yutaka Shionoiri , Kiyoshi Kato , Hidekazu Miyairi
IPC分类号： H01L27/12 , H01L29/786
CPC分类号： H01L27/1225 , H01L29/42384 , H01L29/7869 , H01L29/78696
摘要： To provide a semiconductor device that is suitable for miniaturization. The semiconductor device includes a first transistor, a second transistor over the first transistor, a barrier layer between the first transistor and the second transistor, a first electrode between the first transistor and the barrier layer, and a second electrode between the hairier layer and the second transistor and overlapping the first electrode with the barrier layer therebetween. A gate electrode of the first transistor, the first electrode, one of a source electrode and a drain electrode of the second transistor are electrically connected to one another. A channel is formed in a first semiconductor layer including a single crystal semiconductor in the first transistor, A channel is formed in a second semiconductor layer including an oxide semiconductor in the second transistor.
摘要翻译：提供适合于小型化的半导体器件。半导体器件包括第一晶体管，第一晶体管上的第二晶体管，第一晶体管和第二晶体管之间的阻挡层，第一晶体管和阻挡层之间的第一电极，以及位于毛发层与第二晶体管之间的第二电极第二晶体管并且与第一电极重叠，其间具有阻挡层。第一晶体管的栅电极，第一电极，第二晶体管的源电极和漏极之一彼此电连接。在第一晶体管中的包括单晶半导体的第一半导体层中形成沟道，在第二晶体管中的包含氧化物半导体的第二半导体层中形成沟道。

72. 发明授权

US08988116B2 Method for driving semiconductor device 有权
标题翻译：半导体装置的驱动方法
公开(公告)号：US08988116B2
公开(公告)日：2015-03-24
申请号：US13721120
申请日：2012-12-20
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Hiroki Inoue , Tatsuya Onuki
IPC分类号： H03K3/00 , H03K17/06 , G11C11/403
CPC分类号： H03K17/063 , G11C11/403 , G11C2211/4016
摘要： Provided is a method for driving a semiconductor device, which allows a reduction in scale of a circuit, reduce the power consumption, and increase the speed of reading data. An H level (data “1”) potential or an L level (data “0”) potential is written to a node of a memory cell. Potentials of a source line and a bit line are set to the same potential at an M level (L level
摘要翻译：提供一种用于驱动半导体器件的方法，其允许减小电路的规模，降低功耗，并且提高读取数据的速度。将H电平（数据“1”）电位或L电平（数据“0”）电位写入存储单元的节点。源极线和位线的电位在M电平（L电平

73. 发明申请

US20140266379A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20140266379A1
公开(公告)日：2014-09-18
申请号：US14199584
申请日：2014-03-06
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Hiroki Inoue , Kei Takahashi , Tatsuya Onuki
IPC分类号： H03K5/003
CPC分类号： H03K5/2481 , G11C27/024 , G11C27/026 , H03K5/249
摘要： A sample-and-hold circuit including a transistor and a capacitor is connected to the differential circuit. The sample-and-hold circuit acquires voltage for correcting the offset voltage of the differential circuit by charging or discharging the capacitor through sampling operation. Then, it holds the potential of the capacitor through holding operation. In normal operation of the differential circuit, the output potential of the differential circuit is corrected by the potential held by the capacitor. The transistor in the sample-and-hold circuit is preferably a transistor whose channel is formed using an oxide semiconductor. An oxide semiconductor transistor has extremely low leakage current; thus, a change in the potential held in the capacitor of the sample-and-hold circuit can be minimized.
摘要翻译：包括晶体管和电容器的采样保持电路连接到差分电路。采样保持电路通过采样操作对电容器进行充电或放电来获取用于校正差分电路的偏移电压的电压。然后，它通过保持操作保持电容器的电位。在差分电路的正常工作中，差分电路的输出电位由电容器保持的电位进行校正。采样保持电路中的晶体管优选地是使用氧化物半导体形成沟道的晶体管。氧化物半导体晶体管具有极低的漏电流; 因此，可以使采样保持电路的电容器中保持的电位变化最小化。

74. 发明申请

US20130301332A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130301332A1
公开(公告)日：2013-11-14
申请号：US13890002
申请日：2013-05-08
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Tatsuya Onuki
IPC分类号： G11C5/06 , G11C5/10
CPC分类号： G11C5/063 , G11C5/10 , G11C14/0063
摘要： To provide a semiconductor device with high reliability in operation, in which data in a volatile memory can be saved to a non-volatile memory. For example, the semiconductor device includes an SRAM provided with first and second data storage portions and a non-volatile memory provided with third and fourth data storage portions. The first data storage portion is electrically connected to the fourth data storage portion through a transistor, and the second data storage portion is electrically connected to the third data storage portion through a transistor. The transistors are turned off when the SRAM operates, and the transistors are turned on when the SRAM does not operate, so that data in the SRAM is saved to the non-volatile memory. Precharge is performed when the SRAM is restored.
摘要翻译：为了提供在操作中具有高可靠性的半导体器件，其中易失性存储器中的数据可被保存到非易失性存储器。例如，半导体器件包括设置有第一和第二数据存储部分的SRAM和设置有第三和第四数据存储部分的非易失性存储器。第一数据存储部分通过晶体管电连接到第四数据存储部分，并且第二数据存储部分通过晶体管电连接到第三数据存储部分。当SRAM工作时晶体管截止，当SRAM不工作时，晶体管导通，使得SRAM中的数据被保存到非易失性存储器中。当SRAM恢复时，进行预充电。

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