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71. 发明授权

US09354882B2 Methods and apparatus to manage partial-commit checkpoints with fixup support 有权
公开(公告)号：US09354882B2
公开(公告)日：2016-05-31
申请号：US14041170
申请日：2013-09-30
申请人： Edson Borin , Youfeng Wu
发明人： Edson Borin , Youfeng Wu
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30145 , G06F9/3834 , G06F9/3842 , G06F9/3857 , G06F9/3863
摘要： Example methods and apparatus to manage partial commit-checkpoints are disclosed. A disclosed example method includes identifying a commit instruction associated with a region of instructions executed by a processor, identifying candidate instructions from the region of instructions, and generating a processor partial commit-checkpoint to save a current state of the processor, the checkpoint based on calculated register values associated with live instructions, and including instruction reference addresses to link the candidate instructions.

72. 发明授权

US09348796B2 Arithmetic operation in a data processing system 有权
标题翻译：数据处理系统中的算术运算
公开(公告)号：US09348796B2
公开(公告)日：2016-05-24
申请号：US14031854
申请日：2013-09-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Klaus M. Kroener , Christophe J. Layer , Silvia M. Mueller , Kerstin Schelm
IPC分类号： G06F7/38 , G06F17/10 , G06F7/535 , G06F7/537
CPC分类号： G06F17/10 , G06F7/535 , G06F7/5375
摘要： An arithmetic operation in a data processing unit, preferably by iterative digit accumulations, is proposed. An approximate result of the arithmetic operation is computed iteratively. Concurrently at least two supplementary values of the approximate result of the arithmetic operation are computed, and the final result selected from one of the values of the approximate result and the at least two supplementary values of the arithmetic operation depending on the results of the last iteration step.
摘要翻译：提出了数据处理单元中的优选地通过迭代数字积累的算术运算。迭代地计算算术运算的近似结果。同时计算算术运算的近似结果的至少两个补充值，并且根据最后一次迭代的结果从算术运算的近似结果和至少两个补充值中的一个值中选出最终结果步。

73. 发明授权

US09335996B2 Recycling error bits in floating point units 有权
标题翻译：浮点单位回收错误位
公开(公告)号：US09335996B2
公开(公告)日：2016-05-10
申请号：US13676796
申请日：2012-11-14
申请人： Intel Corporation
发明人： Helia Naeimi , Ralph Nathan , Daniel Sorin , Shih-Lien L. Lu
IPC分类号： G06F7/38 , G06F7/00 , G06F9/30
CPC分类号： G06F11/10 , G06F9/3001 , G06F9/30014 , G06F9/30101
摘要： A mechanism for recycling error bits in a floating point unit is disclosed. A system of the disclosure includes a memory and a processing device communicably coupled to the memory. In one embodiment, the processing device comprising a floating point unit (FPU) to generate a result value from applying an operation on floating point number inputs to the FPU and generate an error value using the result value. The FPU also writes the result value to a first register of the processing device dedicated to storing results from the operation of the FPU and writes the error value to a second register of the processing device dedicated to storing errors from the operation of the FPU.
摘要翻译：公开了一种用于回收浮点单元中的错误位的机构。本公开的系统包括可通信地耦合到存储器的存储器和处理装置。在一个实施例中，处理装置包括一个浮点单元（FPU），用于通过向FPU应用对浮点数输入的操作产生一个结果值，并使用该结果值产生一个误差值。 FPU还将结果值写入专用于从FPU的操作存储结果的处理装置的第一寄存器，并将该错误值写入专用于从FPU的操作存储错误的处理装置的第二寄存器。

74. 发明授权

US09323500B2 Reducing power consumption in a fused multiply-add (FMA) unit responsive to input data values 有权
公开(公告)号：US09323500B2
公开(公告)日：2016-04-26
申请号：US13785528
申请日：2013-03-05
申请人： Brian Hickmann , Dennis Bradford , Thomas Fletcher
发明人： Brian Hickmann , Dennis Bradford , Thomas Fletcher
IPC分类号： G06F7/38 , G06F7/60 , G06F7/48 , G06F7/57 , G06F7/483 , G06F7/544 , G06F9/30 , G06F1/32
CPC分类号： G06F7/60 , G06F1/324 , G06F1/3243 , G06F7/48 , G06F7/483 , G06F7/5443 , G06F7/57 , G06F9/30 , G06F9/3001 , G06F2207/3884 , Y02D10/126 , Y02D10/152
摘要： In an embodiment, a fused multiply-add (FMA) circuit is configured to receive a plurality of input data values to perform an FMA instruction on the input data values. The circuit includes a multiplier unit and an adder unit coupled to an output of the multiplier unit, and a control logic to receive the input data values and to reduce switching activity and thus reduce power consumption of one or more components of the circuit based on a value of one or more of the input data values. Other embodiments are described and claimed.

75. 发明授权

US09305381B1 Multi-threaded rasterisation 有权
标题翻译：多线程栅格化
公开(公告)号：US09305381B1
公开(公告)日：2016-04-05
申请号：US14011697
申请日：2013-08-27
申请人： Google Inc.
发明人： Adrienne Walker , Nathaniel Duca
IPC分类号： G09G5/00 , G06T1/00 , G06F15/00 , G06F9/30 , G06F7/38 , G06T11/20 , G06F9/38 , G06T15/00 , G06T11/00 , G06T11/60
CPC分类号： G06T11/20 , G06F9/30043 , G06F9/3802 , G06F9/3851 , G06T1/20 , G06T11/001 , G06T11/40 , G06T11/60 , G06T15/005 , G06T2210/52
摘要： Methods for drawing content to a display are provided. In one aspect, a method includes receiving input indicating content to be drawn to a display, and providing a request to prepare the content for display to a first thread. The method also includes receiving, in response to the provided request, instructions for drawing the content to the display, and providing the instructions for drawing the content to the display to a second thread. The method further includes executing, by the second thread, the instructions for drawing the content to the display. Systems and machine-readable media are also provided.
摘要翻译：提供了将内容绘制到显示器的方法。在一个方面，一种方法包括接收指示要绘制到显示器的内容的输入，以及提供准备用于显示给第一线程的内容的请求。所述方法还包括响应于所提供的请求，接收将内容绘制到显示器的指令，以及向第二线程提供用于将内容绘制到显示器的指令。该方法还包括由第二线程执行用于将内容绘制到显示器的指令。还提供系统和机器可读介质。

76. 发明授权

US09274969B2 Cache memory apparatus 有权
标题翻译：缓存存储器
公开(公告)号：US09274969B2
公开(公告)日：2016-03-01
申请号：US13950565
申请日：2013-07-25
申请人： MMAGIX TECHNOLOGY LIMITED
发明人： Daniel Shane O'Sullivan
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00 , G06F12/08 , G06F9/30 , G06F9/38 , G06F9/52
CPC分类号： G06F9/3867 , G06F9/3001 , G06F9/30036 , G06F9/3004 , G06F9/30083 , G06F9/30087 , G06F9/30101 , G06F9/3012 , G06F9/3013 , G06F9/30134 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30185 , G06F9/30189 , G06F9/3879 , G06F9/3885 , G06F9/526 , G06F12/0875 , G06F2212/452
摘要： A cache memory apparatus includes an L1 cache memory, an L2 cache memory coupled to the L1 cache memory, an arithmetic logic unit (ALU) within the L2 cache memory, the combined ALU and L2 cache memory being configured to perform therewithin at least one of: an arithmetic operation, a logical bit mask operation; the cache memory apparatus being further configured to interact with at least one processor such that atomic memory operations bypass the L1 cache memory and go directly to the L2 cache memory.
摘要翻译：高速缓冲存储器装置包括：L1高速缓存存储器，耦合到L1高速缓冲存储器的L2高速缓冲存储器，L2高速缓冲存储器内的算术逻辑单元（ALU），组合的ALU和L2高速缓存存储器，被配置为在其中进行至少一个：算术运算，逻辑位掩码运算; 高速缓冲存储器设备还被配置为与至少一个处理器交互，使得原子存储器操作绕过L1高速缓冲存储器并直接去往L2高速缓冲存储器。

77. 发明授权

US09268321B2 Digital tiggering using finite state machines 有权
标题翻译：数字化使用有限状态机
公开(公告)号：US09268321B2
公开(公告)日：2016-02-23
申请号：US14313884
申请日：2014-06-24
申请人： Keysight Technologies, Inc. , Agilent Technologies, Inc.
发明人： Andrew Robert Lehane , Antony J. A. Kirkham , Lee A. Barford
IPC分类号： G06F7/38 , G01R13/02 , G05B19/045 , G04F10/00
CPC分类号： G05B19/045 , G01R13/0272 , G04F10/005 , H03M1/1245 , H03M2201/192
摘要： An apparatus that can be configured for various functions such as a digital oscilloscope, logic analyzer or frequency analyzer is disclosed. The apparatus includes a symbol generator, a multi-symbol FSM, and a controller. The symbol generator generates an ordered sequence of symbols from an ordered sequence of digital values. The symbol generator generates one symbol corresponding to each of the digital values. The digital values have a greater number of possible values than the symbols. The controller causes the multi-symbol FSM to search for a pattern in the sequence of symbols that identifies a corresponding pattern in the sequence of digital values. A portion of the digital sequence is then displayed based on the location of the pattern in the sequence of symbols.
摘要翻译：公开了可以配置为诸如数字示波器，逻辑分析仪或频率分析器等各种功能的装置。该装置包括符号发生器，多符号FSM和控制器。符号生成器从数字值的有序序列生成有序的符号序列。符号发生器产生对应于每个数字值的一个符号。数字值比符号具有更多的可能值。控制器使多符号FSM在符号序列中搜索符号序列中的模式，以识别数字值序列中的对应模式。然后基于符号序列中的图案的位置显示数字序列的一部分。

78. 发明授权

US09239770B2 Apparatus and method for extracting restriction condition 有权
标题翻译：提取限制条件的装置和方法
公开(公告)号：US09239770B2
公开(公告)日：2016-01-19
申请号：US13973086
申请日：2013-08-22
申请人： FUJITSU LIMITED
发明人： Shinji Kikuchi , Yasuhide Matsumoto
IPC分类号： G06F9/46 , G06F7/38 , G06F11/30 , G06F9/445
CPC分类号： G06F11/30 , G06F8/65
摘要： A restriction condition extraction apparatus specifies operation targets including a first target and another target related thereto that are operated based on first procedure information in a first execution environment, extracts first procedures related to the specified operation targets from the first procedure information, generates first relation information indicating an execution order on related operation targets regarding the extracted first procedures, specifies operation targets including a second target and another target related thereto that are operated based on second procedure information in a second execution environment, extracts second procedures related to the specified operation targets from the second procedure information, generates second relation information indicating an execution order on related operation targets regarding the extracted second procedures, compares the first and the second relation information, and extracts relations of an execution order on related operation targets, which are common in the first and the second relation information.
摘要翻译：限制条件提取装置根据第一执行环境，根据第一过程信息指定包括第一目标和与其相关的另一目标的操作目标，从第一过程信息中提取与指定的操作目标有关的第一过程，生成第一关系信息指示关于所提取的第一过程的相关操作目标的执行顺序，指定包括第二目标和与其相关的另一目标的操作目标，其基于第二执行环境中的第二过程信息操作，提取与指定操作目标有关的第二过程第二过程信息生成表示关于所提取的第二过程的相关操作目标的执行顺序的第二关系信息，比较第一和第二关系信息，并且提取执行顺序的关系相关的操作目标，这在第一和第二关系信息中是常见的。

79. 发明授权

US09207964B1 Distributed batch matching of videos with dynamic resource allocation based on global score and prioritized scheduling score in a heterogeneous computing environment 有权
标题翻译：在异构计算环境中，基于全局分数和优先级调度得分的视频与动态资源分配的分布式批量匹配
公开(公告)号：US09207964B1
公开(公告)日：2015-12-08
申请号：US13717233
申请日：2012-12-17
申请人： Google Inc.
发明人： Pascal Gwosdek , Tawei Liao , Kathrin Paschen
IPC分类号： G06F9/46 , G06F17/30 , G06F15/80 , G06F7/38 , G06F9/50 , G06F7/76
CPC分类号： G06F9/5038 , G06F9/5027 , G06F9/5066 , G06F17/30017 , G06F17/30545 , G06F17/30743 , G06F17/30784 , G06F17/3082
摘要： Distribution of various processing tasks is performed for a plurality of comparison objects, such as videos and/or other media content in a matching system. The plurality of comparison objects can include at least one feature that is compared to at least one feature of a plurality of reference objects to determine whether a match occurs in the comparison. Task descriptions corresponding to the processing tasks are distributed with the different processing tasks to a task pool. Matching components select at least one task from the task pool based on the task descriptions.
摘要翻译：对于多个比较对象，例如匹配系统中的视频和/或其他媒体内容，执行各种处理任务的分配。多个比较对象可以包括与多个参考对象的至少一个特征进行比较的至少一个特征，以确定比较中是否发生匹配。与处理任务相对应的任务描述与不同的处理任务分配到任务池。匹配组件根据任务描述从任务池中选择至少一个任务。

80. 发明授权

US09177256B2 Method for solving linear programs 有权
标题翻译：求解线性程序的方法
公开(公告)号：US09177256B2
公开(公告)日：2015-11-03
申请号：US13559849
申请日：2012-07-27
申请人： Roland Wunderling
发明人： Roland Wunderling
IPC分类号： G06F7/38 , G06N7/00 , G06F17/16
CPC分类号： G06N7/00 , G06F17/11 , G06F17/16
摘要： The invention provides for a computer-implemented method for solving a linear program (LP), the method comprising the steps of: receiving (100) the linear program; determining (101) a kernel K and determining a kernel matrix G of the kernel K, wherein the kernel matrix is a non-singular submatrix of the original matrix; determining (102) a set of non-basic variable indices and a set of extra constraint indices; computing (103) a primal kernel vector (xK) from the determined kernel; computing (104) a dual kernel vector (yK) from the determined kernel; and evaluating (105) the feasibility of the primal kernel vector and of the dual kernel vector.
摘要翻译：本发明提供一种用于解决线性程序（LP）的计算机实现的方法，该方法包括以下步骤：接收（100）线性程序; 确定（101）核K并确定所述核K的核矩阵G，其中所述核矩阵是所述原始矩阵的非奇异子矩阵; 确定（102）一组非基本变量索引和一组额外的约束索引; 从所确定的内核计算（103）原始核向量（xK）; 从所确定的内核计算（104）双核向量（yK）; 并评估（105）原始核向量和双核向量的可行性。

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