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71. 发明申请

US20150333745A1 VOLTAGE COMPARATOR 审中-公开
标题翻译：电压比较器
公开(公告)号：US20150333745A1
公开(公告)日：2015-11-19
申请号：US14279677
申请日：2014-05-16
申请人： LSI Corporation
发明人： Naveen Kumar Cannankurichi Vijaya Mohan
IPC分类号： H03K5/125 , H03K17/56
CPC分类号： H03K5/2472 , H03K5/125 , H03K5/2481 , H03K17/302 , H03K17/56
摘要： A voltage comparator for comparing reference voltage applied to a first input node to an input voltage applied to a second input node. A first pair of transistors have output terminals coupled in series between the first input node and common node, and gate terminals connected together. A second pair of transistors, having both gate terminals of the pair connected to the gate terminals of the first pair of transistors, have output terminals coupled in series between a second input terminal, an intermediate node, and the common node. An inverter has an input coupled to the intermediate node and an output coupled to an output of the comparator. An optional feedback transistor might be used to latch the output of the comparator. Optional transistors might also be added to the first and second transistor pairs to selectively enable as the comparator and reset the latched output of the comparator.
摘要翻译：一种电压比较器，用于将施加到第一输入节点的参考电压与施加到第二输入节点的输入电压进行比较。第一对晶体管具有串联耦合在第一输入节点和公共节点之间的输出端子以及连接在一起的栅极端子。具有连接到第一对晶体管的栅极端子的对的两个栅极端子的第二对晶体管具有串联耦合在第二输入端子，中间节点和公共节点之间的输出端子。逆变器具有耦合到中间节点的输入和耦合到比较器的输出的输出。可以使用可选的反馈晶体管来锁存比较器的输出。可选的晶体管也可以被添加到第一和第二晶体管对以选择性地使能作为比较器并且复位比较器的锁存输出。

72. 发明申请

US20150280543A1 DUTY CYCLE BALANCE MODULE FOR SWITCH MODE POWER CONVERTER 审中-公开
标题翻译：用于开关模式电源转换器的占空比平衡模块
公开(公告)号：US20150280543A1
公开(公告)日：2015-10-01
申请号：US14738351
申请日：2015-06-12
申请人： Analog Devices Global
发明人： Yingyang Ou , Renjian Xie , Huailiang Sheng
IPC分类号： H02M1/08 , H03K17/56 , H02M3/335
CPC分类号： H02M1/08 , H02M1/40 , H02M3/33507 , H02M3/33576 , H02M2007/4803 , H03K17/56
摘要： A duty cycle balance module (DCBM) for use with a switch mode power converter. One possible half-bridge converter embodiment includes a transformer driven to conduct current in first and second directions by first and second signals during and second half-cycles, respectively. A current limiting mechanism adjusts the duty cycles of the first and second signals when a sensed current exceeds a predetermined limit threshold. The DCBM receives signals representative of the duty cycles which would be used if there were no modification by the current limiting mechanism and signals Dact—1 and Dact—2 representative of the duty cycles that are actually used for the first and second signals, and outputs signals Dbl—1 and Dbl—2 which modify signals Dact—1 and Dact—2 as needed to dynamically balance the duty cycles of the first and second signals and thereby reduce flux imbalance in the transformer that might otherwise arise.
摘要翻译：用于开关模式功率转换器的占空比平衡模块（DCBM）。一个可能的半桥转换器实施例包括分别被驱动以在第一和第二方向通过第一和第二信号在第一和第二半周期期间传导电流的变压器。当感测电流超过预定极限阈值时，电流限制机构调节第一和第二信号的占空比。 DCBM接收代表占空比的信号，如果没有通过电流限制机制进行修改，并且表示实际用于第一和第二信号的占空比的Dact-1和Dact-2信号，以及输出信号Dbl-1和Dbl-2，其根据需要修改信号Dact-1和Dact-2，以动态平衡第一和第二信号的占空比，从而减少可能出现的变压器中的通量不平衡。

73. 发明授权

US09148140B1 Integrated circuit with precision current source 有权
标题翻译：具有精密电流源的集成电路
公开(公告)号：US09148140B1
公开(公告)日：2015-09-29
申请号：US14170557
申请日：2014-01-31
申请人： MAXIM INTEGRATED PRODUCTS, INC.
发明人： Gabriel E. Tanase
IPC分类号： H03K17/56 , H03K17/687 , H05B33/08
CPC分类号： H03K17/6871 , G05F1/561 , H01L27/0207 , H01L27/0629 , H01L27/092 , H05B33/0809 , H05B33/0812
摘要： An integrated circuit with precision current source includes a first MOSFET, a second MOSFET, an op-amp and a resistor formed on a common semiconductor substrate. The first MOSFET is characterized by a first multiplier (xM1) and the second MOSFET is characterized by a second multiplier (xM2) where a ratio of xM2 to xM1 is greater than one. An inverting input of the op-amp is coupled to a drain of the first MOSFET and an output of the op-amp is coupled to a gate of the first MOSFET. A negative feedback circuit limits a rise in output current under low output voltage conditions.
摘要翻译：具有精密电流源的集成电路包括形成在公共半导体衬底上的第一MOSFET，第二MOSFET，运算放大器和电阻器。第一MOSFET的特征在于第一乘法器（xM1），第二MOSFET的特征在于xM2与xM1的比值大于1的第二乘法器（xM2）。运算放大器的反相输入耦合到第一MOSFET的漏极，并且运算放大器的输出耦合到第一MOSFET的栅极。负反馈电路限制了低输出电压条件下输出电流的上升。

74. 发明申请

US20150188520A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20150188520A1
公开(公告)日：2015-07-02
申请号：US14574884
申请日：2014-12-18
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Takeshi Aoki , Munehiro Kozuma , Yoshiyuki Kurokawa
IPC分类号： H03K3/012 , H03K17/56
CPC分类号： H03K3/012 , H03K17/56 , H03K19/173
摘要： A semiconductor device that can operate normally with lower power consumption is provided. The semiconductor device includes a pair of first circuits which each include a first transistor and a second transistor capable of controlling the supply of a first signal to a gate of the first transistor, and a second circuit which is capable of generating a second signal which is to be supplied to a gate of the second transistor and which has a larger amplitude than the first signal. One of a source and a drain of one of the first transistors included in the pair of first circuits is electrically connected to one of a source and a drain of the other of the first transistors. The first signals supplied to the gates of the first transistors in the pair of first circuits have potentials with different logic levels.
摘要翻译：提供了能够以较低功耗正常工作的半导体器件。半导体器件包括一对第一电路，每个第一电路都包括第一晶体管和能够控制向第一晶体管的栅极提供第一信号的第二晶体管，以及能够产生第二信号的第二电路，被提供给第二晶体管的栅极并且具有比第一信号更大的幅度。包括在该对第一电路中的第一晶体管之一的源极和漏极之一电连接到另一个第一晶体管的源极和漏极之一。提供给该对第一电路中的第一晶体管的栅极的第一信号具有不同逻辑电平的电位。

75. 发明申请

US20150188518A1 SEMICONDUTOR APPARATUS FOR CONTROLLING BACK BIAS 有权
标题翻译：用于控制背偏置的半自动装置
公开(公告)号：US20150188518A1
公开(公告)日：2015-07-02
申请号：US14267627
申请日：2014-05-01
申请人： SK hynix Inc.
发明人： Kie Bong KU
IPC分类号： H03K3/012 , H03K17/56
CPC分类号： H03K17/56 , H03K19/0027
摘要： A semiconductor apparatus includes a back bias control block, a first back bias switching block and second back bias switching block. The back bias control block is configured to generate a first P channel control signal and a second N channel control signal. The first back bias switching block is configured to provide one of first and second high voltages as a first P channel back bias of a first circuit in response to the first P channel control signal, and to provide one of first and second low voltages as a first N channel back bias of the first circuit in response to the first N channel control signal. The second back bias switching block is configured to provide one of the first and second high voltages as a second P channel back bias of a second circuit in response to the second P channel control signal, and to provide one of the first and second low voltages as a second N channel back bias of the second circuit in response to the second N channel control signal.
摘要翻译：半导体装置包括背偏置控制块，第一后偏置开关块和第二后偏置开关块。背偏置控制块被配置为产生第一P通道控制信号和第二N通道控制信号。第一背偏置开关块被配置为响应于第一P沟道控制信号而将第一和第二高电压中的一个提供为第一电路的第一P沟道反向偏置，并且将第一和第二低电压中的一个提供为响应于第一N沟道控制信号，第一电路的第一N沟道反向偏置。第二背偏置开关块被配置为响应于第二P沟道控制信号而将第一和第二高电压中的一个作为第二电路的第二P沟道反向偏置，并且提供第一和第二低电压中的一个作为响应于第二N沟道控制信号的第二电路的第二N沟道反向偏置。

76. 发明申请

US20150116024A1 COMPOSITE SEMICONDUCTOR SWITCHING DEVICE 有权
标题翻译：复合半导体开关器件
公开(公告)号：US20150116024A1
公开(公告)日：2015-04-30
申请号：US14390536
申请日：2012-04-06
申请人： Junichiro Ishikawa
发明人： Junichiro Ishikawa
IPC分类号： H03K17/56 , H02M1/08
CPC分类号： H03K17/56 , H02M1/08 , H02M1/088 , H02M2001/0054 , H03K17/164 , H03K2217/0036 , H03K2217/0054 , Y02B70/1491
摘要： A composite semiconductor switching device includes: a first semiconductor element that incurs switching losses when performing switching operation of turning on and off; a second semiconductor element that is parallelly connected to the first semiconductor element and incurs switching losses larger than the first semiconductor element when performing switching operations of turning on and off; and a controller that operates in order of giving a first on-command signal to the first semiconductor element, giving a second on-command signal to the second semiconductor element, deactivating the first on-command signal, giving a third on-command signal to the first semiconductor element, and deactivating the second on-command signal.
摘要翻译：一种复合半导体开关器件，包括：第一半导体元件，其在进行导通和截止的开关操作时产生开关损耗; 第二半导体元件，其在进行导通和截止的开关操作时并联连接到所述第一半导体元件并且导致大于所述第一半导体元件的开关损耗; 以及控制器，其按照给予第一半导体元件的第一命令信号的顺序操作，给予第二导通命令信号给第二半导体元件，停用第一导通命令信号，给第三导通命令信号第一半导体元件，以及去激活第二导通命令信号。

77. 发明授权

US09018985B2 Power module and output circuit 有权
标题翻译：电源模块和输出电路
公开(公告)号：US09018985B2
公开(公告)日：2015-04-28
申请号：US13814132
申请日：2011-08-04
申请人： Takashi Sawada , Masao Saito
发明人： Takashi Sawada , Masao Saito
IPC分类号： H03K3/00 , H03K17/16 , H03K17/56 , H02M1/08 , H02M1/38 , H02M7/538 , H03K17/06 , H01L25/07 , H01L27/088 , H01L23/00 , H02M7/00
CPC分类号： H03K17/56 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/85 , H01L25/072 , H01L27/088 , H01L2224/32225 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48137 , H01L2224/48227 , H01L2224/48472 , H01L2224/48624 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/48824 , H01L2224/48847 , H01L2224/4903 , H01L2224/49111 , H01L2224/49175 , H01L2224/49431 , H01L2224/73265 , H01L2224/85424 , H01L2224/85447 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/10253 , H01L2924/10272 , H01L2924/1203 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/19107 , H01L2924/3011 , H02M1/08 , H02M1/38 , H02M7/003 , H02M7/538 , H03K17/06 , H03K17/063 , H03K2017/066 , Y10T307/747 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： A power module (2) includes a first high-side main-circuit MOSFET (21) and a second low-side main-circuit MOSFET (22) connected in series thereto. The series circuit of the MOSFETs (21, 22) is connected in parallel to a power source (4). A first short-circuit MOSFET (25) is connected between the gate and the source of the first main-circuit MOSFET (21). A second short-circuit MOSFET (26) is connected between the gate and the source of the second main-circuit MOSFET (22).
摘要翻译：电源模块（2）包括串联连接的第一高侧主电路MOSFET（21）和第二低压侧主电路MOSFET（22）。 MOSFET（21,22）的串联电路与电源（4）并联连接。第一短路MOSFET（25）连接在第一主电路MOSFET（21）的栅极和源极之间。第二短路MOSFET（26）连接在第二主电路MOSFET（22）的栅极和源极之间。

78. 发明申请

US20150035583A1 FIELD DEVICE AND METHOD OF OPERATING HIGH VOLTAGE SEMICONDUCTOR DEVICE APPLIED WITH THE SAME 有权
标题翻译：现场设备及其应用的高电压半导体器件的操作方法
公开(公告)号：US20150035583A1
公开(公告)日：2015-02-05
申请号：US14519192
申请日：2014-10-21
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： An-Li Cheng , Miao-Chun Chung , Chih-Chia Hsu , Yin-Fu Huang
IPC分类号： H03K17/16 , H03K17/56
CPC分类号： H03K17/16 , H01L29/0696 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/402 , H01L29/404 , H01L29/7816 , H03K17/56
摘要： A field device and method of operating high voltage semiconductor device applied with the same are provided. The field device includes a first well having a second conductive type and second well having a first conductive type both formed in the substrate (having the first conductive type) and extending down from a surface of the substrate, the second well adjacent to one side of the first well and the substrate is at the other side of the first well; a first doping region having the first conductive type and formed in the second well, the first doping region spaced apart from the first well; a conductive line electrically connected to the first doping region and across the first well region; and a conductive body insulatively positioned between the conductive line and the first well, and the conductive body correspondingly across the first well region.
摘要翻译：提供了一种应用该高压半导体器件的现场设备和操作方法。现场设备包括具有第二导电类型的第一阱和具有第一导电类型的第二阱，所述第二阱具有形成在衬底（具有第一导电类型）中并且从衬底的表面向下延伸的第一导电类型，第一阱和衬底位于第一阱的另一侧; 具有第一导电类型并形成在第二阱中的第一掺杂区域，第一掺杂区域与第一阱间隔开; 电连接到第一掺杂区并横跨第一阱区的导线; 以及绝缘地定位在导电线和第一阱之间的导电体，并且导电体相应地穿过第一阱区。

79. 发明授权

US08933714B2 Level shift circuit using parasitic resistor in semiconductor substrate 有权
标题翻译：在半导体衬底中使用寄生电阻的电平移位电路
公开(公告)号：US08933714B2
公开(公告)日：2015-01-13
申请号：US13861488
申请日：2013-04-12
申请人： Fuji Electric Co., Ltd.
发明人： Masashi Akahane
IPC分类号： G01R27/28 , G11C19/00 , H03K17/56 , G01R27/02 , H03K17/0412 , H03K17/14 , H03K17/16
CPC分类号： H03K17/56 , G01R27/02 , H03K17/04123 , H03K17/145 , H03K17/162 , H03K2217/0063 , H03K2217/0072 , H03K2217/0081
摘要： A level shift circuit in which no adverse effect is produced on a delay time, regardless of the resistance values of resistors. The level shift circuit includes an operation detection circuit that outputs a nseten signal and a nresen signal in response to a state of output from first and second series circuits, a latch malfunction protection circuit connected to the operation detection circuit, a latch circuit connected through first to sixth resistors to first and second level shift output terminals of the first and second series circuits, first and second parasitic resistors, and third and fourth switching elements connected in parallel therewith, and fifth and sixth switching elements connected to a power source potential, a connection point of the first and second resistors or a connection point of the third and fourth resistors, and the operation detection circuit.
摘要翻译：不考虑电阻器的电阻值的电平移位电路，其在延迟时间上不产生不利影响。电平移位电路包括响应于来自第一和第二串联电路的输出状态而输出nseten信号和nresen信号的操作检测电路，连接到操作检测电路的闩锁故障保护电路，通过第一连接的锁存电路到第一和第二串联电路的第一和第二电平移位输出端的第六电阻器，第一和第二寄生电阻器以及并联连接的第三和第四开关元件，以及连接到电源电位的第五和第六开关元件，第一和第二电阻器的连接点或第三和第四电阻器的连接点以及操作检测电路。

80. 发明授权

US08922259B2 Gate drive circuit 有权
标题翻译：门驱动电路
公开(公告)号：US08922259B2
公开(公告)日：2014-12-30
申请号：US14200367
申请日：2014-03-07
申请人： Denso Corporation
发明人： Kazuki Yamauchi , Yasutaka Senda
IPC分类号： H03K3/00 , H03K17/56
CPC分类号： H03K17/08128
摘要： A gate drive circuit includes a power supply circuit that has an output switch function for switching a voltage value of a drive voltage between two levels, a gate-ON drive circuit that outputs a constant electric current toward a gate of an IGBT from an output terminal of the power supply circuit, and a control section performs a constant electric current drive of a gate of the IGBT at a time of a turn-ON by operating the gate-ON drive circuit. At a turn-ON start time, the control section sets the drive voltage to a relatively-high first set value, and then switches the drive voltage to a relatively-low second set value at a switch timing after a mirror period end time.
摘要翻译：栅极驱动电路包括电源电路，其具有用于切换两级之间的驱动电压的电压值的输出开关功能，从输出端子向IGBT的栅极输出恒定电流的栅极导通驱动电路并且控制部分通过操作所述栅极导通驱动电路来执行在导通时的IGBT的栅极的恒定电流驱动。在接通启动时，控制部将驱动电压设定为相对高的第一设定值，然后在镜面周期结束时间之后的切换定时将驱动电压切换为相对低的第二设定值。

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