专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明申请

US20090129459A1 DATA RECEIVER OF SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：半导体集成电路的数据接收器
公开(公告)号：US20090129459A1
公开(公告)日：2009-05-21
申请号：US12177829
申请日：2008-07-22
申请人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： H03K5/159
CPC分类号： H03K19/09425
摘要： A semiconductor integrated circuit equipped with an equalizer which has a circuit structure simpler than that of a related equalizer according to an FFE scheme or a DFE scheme and is capable of preventing a noise component from being amplified. The data receiver includes a plurality of receiver units, wherein each receiver unit includes a plurality of level detectors which detect different levels, and an encoder, in which the level detectors receive data according to a clock signal having a predetermined phase difference and perform an amplification operation including an equalization function based on feedback data, thereby outputting an amplification signal, and wherein level detectors of one receiver unit receive an amplification signal, as the feedback data, from level detectors of another receiver unit that receives a first clock signal having a phase more advanced than a phase of a second clock signal received in one receiver unit.
摘要翻译：一种配备有均衡器的半导体集成电路，其具有比根据FFE方案或DFE方案的相关均衡器的电路结构简单的电路结构，并且能够防止噪声分量被放大。数据接收机包括多个接收机单元，其中每个接收机单元包括检测不同电平的多个电平检测器和编码器，其中电平检测器根据具有预定相位差的时钟信号接收数据并执行放大操作包括基于反馈数据的均衡功能，从而输出放大信号，并且其中一个接收器单元的电平检测器从另一接收器单元的电平检测器接收作为反馈数据的放大信号，该接收器单元接收具有相位的第一时钟信号比在一个接收机单元中接收的第二时钟信号的相位更先进。

82. 发明申请

US20090067278A1 DATA OUTPUT CIRCUIT FOR SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：半导体存储器的数据输出电路
公开(公告)号：US20090067278A1
公开(公告)日：2009-03-12
申请号：US12169568
申请日：2008-07-08
申请人： Hae Rang Choi , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee
发明人： Hae Rang Choi , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee
IPC分类号： G11C8/08
CPC分类号： G11C7/1051 , G11C7/1057 , G11C29/028 , G11C29/1201 , G11C29/50
摘要： A data output circuit for a semiconductor memory apparatus includes a driver control signal generating unit that has a plurality of control signal generating units, each of which generates a driver unit control signal in response to a test signal during a test, and generates the driver unit control signal according to whether or not a fuse is cut after the test is completed, a first driver that has a plurality of driver units, each of which is activated in response to the driver unit control signal to drive a first data signal as an input signal and to output the driven first data signal to an output node, a signal combining unit that generates a first driver control signal in response to the driver unit control signal and an enable signal, and a second driver that has a plurality of driver units, each of which is activated in response to the first driver control signal to drive a second data signal as an input signal and to output the driven second data signal to the output node, and the number of driver units being two or more times as much as the number of driver units in the first driver. A voltage level on the output node is the voltage level of an output signal.
摘要翻译：一种用于半导体存储装置的数据输出电路，包括具有多个控制信号生成单元的驱动器控制信号生成单元，每个控制信号生成单元响应于测试期间的测试信号生成驱动单元控制信号，并且生成驱动单元根据在测试完成之后是否切断熔丝的控制信号，具有多个驱动单元的第一驱动器，每个驱动器单元响应于驱动单元控制信号被激活以驱动第一数据信号作为输入信号并将驱动的第一数据信号输出到输出节点;响应于驱动单元控制信号和使能信号产生第一驱动器控制信号的信号组合单元，以及具有多个驱动器单元的第二驱动器，其中的每一个响应于第一驱动器控制信号被激活，以驱动第二数据信号作为输入信号，并将驱动的第二数据信号输出到输出节点;以及驱动器单元的数量是第一驱动器中的驱动器单元的数量的两倍或更多倍。输出节点上的电压电平是输出信号的电压电平。

83. 发明申请

US20090045862A1 CLOCK GENERATING CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS 审中-公开
标题翻译：半导体存储器的时钟发生电路
公开(公告)号：US20090045862A1
公开(公告)日：2009-02-19
申请号：US12167066
申请日：2008-07-02
申请人： Yong Ju Kim , Kun Woo Park , Dae Han Kwon , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Yong Ju Kim , Kun Woo Park , Dae Han Kwon , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： H03K4/00
CPC分类号： H03K5/151
摘要： A clock generating circuit of a semiconductor memory apparatus includes a phase splitter that delays a clock to generate a delayed clock and inverts the clock to generate an inverted clock, and a clock buffer that buffers the delayed clock and the inverted clock and outputs a rising clock and a falling clock.
摘要翻译：半导体存储装置的时钟产生电路包括：相位分离器，其延迟时钟以产生延迟的时钟并使时钟反相以产生反相时钟;以及时钟缓冲器，缓冲延迟时钟和反相时钟，并输出上升时钟和一个下降的时钟。

84. 发明申请

US20090041154A1 APPARATUS FOR TRANSMITTING SIGNAL IN SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：用于在半导体集成电路中发送信号的装置
公开(公告)号：US20090041154A1
公开(公告)日：2009-02-12
申请号：US11966250
申请日：2007-12-28
申请人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang
发明人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang
IPC分类号： H04L25/49
CPC分类号： H04L25/4917
摘要： An apparatus for transmitting a signal in a semiconductor integrated circuit includes a multilevel transmission control block that outputs a plurality of bits of an input signal in serial or parallel according to whether a multilevel transmission operation is performed or not, and a signal processing block that selectively performs the multilevel transmission operation according to a form of the input signal, which are output in serial or parallel from the multilevel transmission control block.
摘要翻译：一种用于在半导体集成电路中发送信号的装置包括：多电平传输控制块，其根据是否执行多级传输操作来串行或并行输出输入信号的多个位;以及信号处理块，其选择性地根据从多级传输控制块串行或并行输出的输入信号的形式执行多级传输操作。

85. 发明申请

US20080191776A1 SIGNAL RECEIVER CIRCUIT CAPABLE OF IMPROVING AREA AND POWER EFFICIENCY IN SEMICONDUCTOR INTEGRATED CIRCUITS 有权
标题翻译：提高半导体集成电路面积和功率效率的信号接收电路
公开(公告)号：US20080191776A1
公开(公告)日：2008-08-14
申请号：US11959264
申请日：2007-12-18
申请人： Hee Woong Song , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang
发明人： Hee Woong Song , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang
IPC分类号： H03L5/00
CPC分类号： H03K5/08 , H03K3/356139 , H03K3/356191 , H04L25/062
摘要： A signal receiver circuit includes a first level detector for offset-controlling a first output node in response to a pair of first reference signals. A second level detector offset-controls a second output node in response to a pair of second reference signals.
摘要翻译：信号接收器电路包括第一电平检测器，用于响应于一对第一参考信号偏移控制第一输出节点。第二级检测器偏移 - 响应于一对第二参考信号来控制第二输出节点。

86. 发明申请

US20080061840A1 Receiver circuit having compensated offset voltage 失效
标题翻译：接收器电路具有补偿失调电压
公开(公告)号：US20080061840A1
公开(公告)日：2008-03-13
申请号：US11822503
申请日：2007-07-06
申请人： Tae Jin Hwang , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim
发明人： Tae Jin Hwang , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim
IPC分类号： H03F3/42
CPC分类号： H03F3/45766 , G11C7/02 , G11C7/065 , G11C7/08 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1078 , G11C7/109 , H03F3/45179 , H03F3/45475 , H03F3/45991 , H03F2203/45136 , H03F2203/45212 , H03F2203/45352 , H03F2203/45354
摘要： A receiver circuit includes an offset control signal generating unit that outputs a plurality of offset control signals using an offset voltage. A sense amplifier receives a first current and a second current generated on the basis of an up input signal and a down input signal, respectively, converts the first current and the second current into an up compensating signal and a down compensating signal having electric potentials compensating the offset voltage, and amplifies the up compensating signal and the down compensating signal to output an up output signal and a down output signal.
摘要翻译：接收器电路包括偏移控制信号生成单元，其使用偏移电压输出多个偏移控制信号。读出放大器分别接收基于上输入信号和下输入信号产生的第一电流和第二电流，将第一电流和第二电流分别转换成上补偿信号和具有补偿电位的下补偿信号偏移电压，并放大上补偿信号和下降补偿信号，以输出上输出信号和下输出信号。

87. 发明申请

US20070194818A1 Phase locked loop circuit having set initial locking level and control method thereof 失效
标题翻译：具有设定初始锁定电平的锁相环电路及其控制方法
公开(公告)号：US20070194818A1
公开(公告)日：2007-08-23
申请号：US11640965
申请日：2006-12-19
申请人： Yong-Ju Kim , Kun-Woo Park , Hyung-Soo Kim , Ic-Su Oh , Hee-Woong Song , Jong-Woon Kim , Tae-Jin Hwang
发明人： Yong-Ju Kim , Kun-Woo Park , Hyung-Soo Kim , Ic-Su Oh , Hee-Woong Song , Jong-Woon Kim , Tae-Jin Hwang
IPC分类号： H03L7/06
CPC分类号： H03L7/107 , H03L7/1075
摘要： A phase locked loop circuit and a control method thereof. A phase locked loop circuit includes a phase detecting and correcting block configured to detect a phase difference between a reference clock and a feedback clock, and to correct the phase of the feedback clock such that the phase of the reference clock and the phase of the feedback clock are consistent with each other, and an initial locking level setting block configured to set a locking level in a normal operation mode in the phase detecting and correcting block. The initial locking level setting block includes a digital-to-analog converting unit configured to generate an analog voltage according to a digital code corresponding to the set frequency, and charges the capacitive element with the analog voltage, and a switching unit configured to connect the digital-to-analog converting unit and the capacitive element in response to an input of an operation start signal.
摘要翻译：一种锁相环电路及其控制方法。锁相环电路包括相位检测和校正块，被配置为检测参考时钟和反馈时钟之间的相位差，并且校正反馈时钟的相位，使得参考时钟的相位和反馈的相位时钟彼此一致，并且初始锁定电平设置块被配置为在相位检测和校正块中将正常操作模式中的锁定电平设置为1。初始锁定电平设置块包括数模转换单元，被配置为根据与设定频率相对应的数字码产生模拟电压，并且用模拟电压对电容元件充电;以及开关单元，被配置为将数字模拟转换单元和电容元件，以响应于操作开始信号的输入。

88. 发明申请

US20050091781A1 Device for cleaning reticle box 审中-公开
标题翻译：用于清洁标线盒的装置
公开(公告)号：US20050091781A1
公开(公告)日：2005-05-05
申请号：US10980020
申请日：2004-11-03
申请人： Jae-Hyun Yang , Yo-Han Ahn , Tae-Jin Hwang
发明人： Jae-Hyun Yang , Yo-Han Ahn , Tae-Jin Hwang
IPC分类号： H01L21/027 , B08B5/00 , B08B5/02 , B08B11/00 , G03F7/20
CPC分类号： G03F1/66 , B08B5/00 , B08B5/02 , G03F7/70741 , G03F7/70933
摘要： The present invention relates to a reticule storage device. After the reticule storage device influxes external airs using a motor and a fan, it provides the external airs filtered by a filter to a reticule storage shelf in a chamber. According to the present invention, a nitrogen gas supply pipe is installed on one end of the chamber. In addition, the nitrogen gas supplier is installed to be connected from the nitrogen gas supplier to the reticule storage shelf. Several nitrogen gas supply nozzles are installed on an end portion of the nitrogen gas supply pipe, so that nitrogen gas is supplied to maintain a regular pressure in the chamber when a motor inflowing external airs is stopped. As a result, in case that an apparatus is stopped due to a problem of the apparatus for many hours, or an external voltage is not supplied due to a problem of the external problem, nitrogen gases may be purged in the apparatus. Accordingly, the purity in the apparatus can be maintained, so that it is possible to prevent a reticule kept in the apparatus from a particle contamination.
摘要翻译：本发明涉及网状存储装置。在网状存储装置使用马达和风扇冲入外部空气之后，它将由过滤器过滤的外部空气提供到腔室中的网状物存放架。根据本发明，氮气供给管安装在室的一端。此外，氮气供应器安装成从氮气供应器连接到网状物存放架。在氮气供给管的端部安装有若干个氮气供给喷嘴，在电动机流入外部空气停止时，供给氮气来维持室内的规定的压力。结果，由于设备由于该设备的问题停止了许多小时，或由于外部问题而不提供外部电压的情况，在设备中可以清除氮气。因此，可以保持装置中的纯度，使得可以防止保持在装置中的网状物免受颗粒污染。

89. 发明授权

US08213531B2 Apparatus for transmitting signal in semiconductor integrated circuit 失效
标题翻译：在半导体集成电路中传输信号的装置
公开(公告)号：US08213531B2
公开(公告)日：2012-07-03
申请号：US11966250
申请日：2007-12-28
申请人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang
发明人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang
IPC分类号： H04L25/34
CPC分类号： H04L25/4917
摘要： An apparatus for transmitting a signal in a semiconductor integrated circuit includes a multilevel transmission control block that outputs a plurality of bits of an input signal in serial or parallel according to whether a multilevel transmission operation is performed or not, and a signal processing block that selectively performs the multilevel transmission operation according to a form of the input signal, which are output in serial or parallel from the multilevel transmission control block.
摘要翻译：一种用于在半导体集成电路中发送信号的装置包括：多电平传输控制块，其根据是否执行多级传输操作来串行或并行输出输入信号的多个位;以及信号处理块，其选择性地根据从多级传输控制块串行或并行输出的输入信号的形式执行多级传输操作。

90. 发明授权

US08189400B2 Data alignment circuit of semiconductor memory apparatus 有权
标题翻译：半导体存储装置的数据对准电路
公开(公告)号：US08189400B2
公开(公告)日：2012-05-29
申请号：US12647174
申请日：2009-12-24
申请人： Hyung Soo Kim , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Hyung Soo Kim , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： G11C7/00
CPC分类号： G11C7/1006 , G11C7/1012 , G11C7/1078 , G11C7/1087
摘要： A data alignment circuit of a semiconductor memory apparatus for receiving and aligning parallel data group includes a first control unit, a second control unit, a first alignment unit and a second alignment unit. The first alignment unit generates a first control signal group in response to an address group, a clock signal, and a latency signal. The second control unit generates a second control signal group in response to the address group, the clock signal, and the latency signal. The first alignment unit aligns the parallel data group as a first serial data group in response to the first control signal group. The second alignment unit aligns the parallel data group as a second serial data group in response to the second control signal group.
摘要翻译：用于接收和对准并行数据组的半导体存储装置的数据对准电路包括第一控制单元，第二控制单元，第一对准单元和第二对准单元。第一对准单元响应于地址组，时钟信号和等待时间信号产生第一控制信号组。第二控制单元响应于地址组，时钟信号和等待时间信号产生第二控制信号组。第一对准单元响应于第一控制信号组将并行数据组对准为第一串行数据组。第二对准单元响应于第二控制信号组将并行数据组对准为第二串行数据组。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式