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81. 发明授权

US09158344B2 CPU with stacked memory 有权
标题翻译： CPU堆叠内存
公开(公告)号：US09158344B2
公开(公告)日：2015-10-13
申请号：US13689070
申请日：2012-11-29
申请人： Conversant Intellectual Property Management Inc.
发明人： Hong Beom Pyeon
IPC分类号： G06F1/20 , G06F1/18 , H01L25/18 , G06F15/78 , G11C11/401
CPC分类号： G06F1/18 , G06F1/203 , G06F15/78 , G11C11/401 , H01L25/18 , H01L2224/16225 , H01L2224/73253 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： A multi-chip package has a substrate with electrical contacts for connection to an external device. A CPU die is disposed on the substrate and is in communication with the substrate. The CPU die has a plurality of processor cores occupying a first area of the CPU die, and an SRAM cache occupying a second area of the CPU die. A DRAM cache is disposed on the CPU die and is in communication with the CPU die. The DRAM cache has a plurality of stacked DRAM die. The plurality of stacked DRAM dies are substantially aligned with the second area of the CPU die, and substantially do not overlap the first area of the CPU die. A multi-chip package having a DRAM cache disposed on the substrate and a CPU die disposed on the DRAM cache is also disclosed.
摘要翻译：多芯片封装具有具有用于连接到外部设备的电触点的基板。 CPU芯片设置在基板上并且与基板连通。 CPU管芯具有占用CPU管芯的第一区域的多个处理器核和占据CPU管芯的第二区域的SRAM缓存。 DRAM缓存器设置在CPU管芯上并与CPU管芯通信。 DRAM高速缓存具有多个堆叠的DRAM裸片。多个堆叠的DRAM裸片基本上与CPU裸片的第二区域对准，并且基本上不与CPU裸片的第一区域重叠。还公开了具有设置在基板上的DRAM高速缓存和设置在DRAM高速缓存上的CPU管芯的多芯片封装。

82. 发明授权

US09117527B2 Non-volatile memory device having configurable page size 有权
标题翻译：具有可配置页面大小的非易失性存储器件
公开(公告)号：US09117527B2
公开(公告)日：2015-08-25
申请号：US14158116
申请日：2014-01-17
申请人： MOSAID TECHNOLOGIES INCORPORATED
发明人： Jin-Ki Kim
IPC分类号： G11C16/04 , G11C16/08 , G11C8/08 , G11C8/10 , G11C16/10
CPC分类号： G11C16/08 , G11C8/08 , G11C8/10 , G11C15/046 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/26
摘要： A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted.
摘要翻译：具有至少一个存储体的闪速存储器件，其中每个存储体具有可独立配置的页面大小。每个存储体包括至少两个具有对应页面缓冲器的存储器平面，其中响应于配置数据和地址数据，同时选择性地访问存储器层的任何数量和组合。在上电时，可以将组态数据加载到存储设备中，以进行存储体的静态页面配置，或者可以通过每个命令接收配置数据以允许存储体的动态页面配置。通过选择性地调整存储体的页面大小，相应地调整块大小。

83. 发明申请

US20150161072A1 SEMICONDUCTOR MEMORY DEVICE WITH PLURAL MEMORY DIE AND CONTROLLER DIE 审中-公开
标题翻译：具有多个存储器和控制器的半导体存储器件
公开(公告)号：US20150161072A1
公开(公告)日：2015-06-11
申请号：US14625858
申请日：2015-02-19
申请人： Conversant Intellectual Property Management Inc.
发明人： Peter B. Gillingham
IPC分类号： G06F13/42 , G11C7/10
CPC分类号： G06F13/4234 , G06F1/3203 , G06F1/3237 , G06F1/3253 , G06F1/3275 , G06F1/3287 , G06F13/1689 , G11C7/1072 , H01L24/48 , H01L25/0657 , H01L2224/48145 , H01L2224/48227 , H01L2225/06506 , H01L2225/0651 , H01L2225/06555 , H01L2225/06562 , H01L2924/00014 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D10/17 , Y02D10/171 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： A semiconductor memory device including a plurality of memory die and a controller die. The controller die is connected to an internal control bus. The controller die is configured to provide to a selected one of the memory die an internal read command responsive to an external read command. The selected memory die is configured to provide read data to the controller in response to the internal read command; wherein latency between receipt by the controller die of the external read command and receipt of the read data from the selected memory die differs for at least two of the memory die when selected as the selected memory die.
摘要翻译：一种包括多个存储器管芯和一个控制器管芯的半导体存储器件。控制器管芯连接到内部控制总线。控制器管芯被配置为响应于外部读取命令向存储器管芯中的所选择的一个提供内部读取命令。所选择的存储器管芯被配置为响应于内部读取命令向控制器提供读取数据; 其中当被选择为所选择的存储器管芯时，由所述控制器管芯接收所述外部读取命令和从所选择的存储器管芯接收到所读取的数据的等待时间对于所述存储器管芯中的至少两个而言是不同的

84. 发明授权

US09030024B2 Semiconductor device with through-silicon vias 有权
标题翻译：具有通硅通孔的半导体器件
公开(公告)号：US09030024B2
公开(公告)日：2015-05-12
申请号：US13094619
申请日：2011-04-26
申请人： Jin-Ki Kim
发明人： Jin-Ki Kim
IPC分类号： H01L23/48 , H01L25/065 , G11C5/02 , G11C8/12 , G11C29/00
CPC分类号： H01L25/0657 , G11C5/02 , G11C8/12 , G11C29/702 , H01L23/481 , H01L2224/16145 , H01L2225/06513 , H01L2225/06544
摘要： Disclosed is a semiconductor device with through-silicon vias (TSVs) that comprises a primary TSV group, a plurality of signal lines connected to the primary TSV group, a redundant TSV group and connection circuitry responsive to a control signal having a predetermined value to electrically connect the signal lines to the redundant TSV group.
摘要翻译：公开了一种具有通硅通孔（TSV）的半导体器件，其包括主TSV组，连接到主TSV组的多条信号线，冗余TSV组和响应于具有预定值的控制信号的连接电路以电将信号线连接到冗余TSV组。

85. 发明授权

US08879351B2 Non-volatile memory bank and page buffer therefor 有权
标题翻译：非易失性存储器和页缓冲器
公开(公告)号：US08879351B2
公开(公告)日：2014-11-04
申请号：US13618022
申请日：2012-09-14
申请人： Jin-Ki Kim
发明人： Jin-Ki Kim
IPC分类号： G11C8/00 , G11C7/10 , G11C5/02 , G11C7/12 , G11C16/24 , G11C16/10 , G11C16/16
CPC分类号： G06F3/061 , G06F3/0629 , G06F3/0659 , G06F3/0679 , G11C5/025 , G11C7/1006 , G11C7/1033 , G11C7/1039 , G11C7/1042 , G11C7/1048 , G11C7/1051 , G11C7/1072 , G11C7/12 , G11C16/04 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/24 , G11C16/26 , G11C16/32 , G11C2207/107 , G11C2216/14 , G11C2216/20 , G11C2216/30
摘要： A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. Each half of the memory bank is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.
摘要翻译：一种具有串行数据接口和串行数据路径核心的存储器系统，用于从至少一个存储器组接收数据并将数据作为串行比特流提供给至少一个存储体。记忆库的每一半分为上部和下部。每个扇区使用集成的自列解码电路并行提供与共享的二维页面缓冲器的数据。存储器中的串行到并行数据转换器将并行数据从一半耦合到串行数据路径核心。具有集成自列解码电路的共享二维页面缓冲器使每个存储体的电路和芯片面积开销最小化，并且串行数据路径核心减少了芯片面积。因此，与具有相同密度的单个存储体系统相比，实现多存储体系统而没有显着相应的芯片面积增加。

86. 发明授权

US08860480B2 Circuit for clamping current in a charge pump 有权
标题翻译：用于在电荷泵中夹紧电流的电路
公开(公告)号：US08860480B2
公开(公告)日：2014-10-14
申请号：US13873503
申请日：2013-04-30
申请人： Conversant Intellectual Property Management Inc.
发明人： Peter Vlasenko , Huy Tuong Mai
IPC分类号： H03L7/06 , H02M3/07 , H03K5/08 , H02M1/34 , H03L7/089 , G05F3/02
CPC分类号： H02M3/07 , G05F1/625 , G05F3/02 , H02M1/34 , H02M3/073 , H03K5/086 , H03L7/0895
摘要： A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.
摘要翻译：公开了一种用于钳位电荷泵中的电流的电路。电荷泵包括具有多个开关电路晶体管的开关电路。电路中的第一和第二对晶体管中的每一个可以在该晶体管截止期间从其相关联的一个开关电路晶体管提供电流的附加路径，使得来自开关电路晶体管的电流尖峰仅部分地透过在开关电路晶体管和电荷泵的电容器之间延伸的路径。

87. 发明授权

US08842472B2 Partial block erase architecture for flash memory 有权
标题翻译：闪存的部分块擦除架构
公开(公告)号：US08842472B2
公开(公告)日：2014-09-23
申请号：US12785099
申请日：2010-05-21
申请人： Jin-Ki Kim
发明人： Jin-Ki Kim
IPC分类号： G11C16/06 , G11C16/34 , G11C16/04
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/3418 , G11C16/3427 , G11C16/344 , G11C16/349
摘要： A method and system for increasing the lifespan of a flash memory device by selectively erasing sub-blocks of a memory block. Each physical memory block of the flash memory device is dividable into at least two logical sub-blocks, where each of the at least two logical sub-blocks is erasable. Therefore, only the data of the logical sub-block is erased and reprogrammed while unmodified data in the other logical sub-block avoids unnecessary program/erase cycles. The logical sub-blocks to be erased are dynamically configurable in size and location within the block. A wear leveling algorithm is used for distributing data throughout the physical and logical sub-blocks of the memory array to maximize the lifespan of the physical blocks during programming and data modification operations.
摘要翻译：一种用于通过选择性地擦除存储器块的子块来增加闪存器件的寿命的方法和系统。闪速存储器件的每个物理存储器块可被分割成至少两个逻辑子块，其中至少两个逻辑子块中的每个逻辑子块是可擦除的。因此，只有逻辑子块的数据被擦除并重新编程，而另一个逻辑子块中的未修改数据避免了不必要的编程/擦除周期。要擦除的逻辑子块可在块内的大小和位置上动态配置。磨损均衡算法用于在存储器阵列的整个物理和逻辑子块中分布数据，以在编程和数据修改操作期间最大化物理块的寿命。

88. 发明申请

US20140264541A1 Structure and Method for Manufacture of Memory Device With Thin Silicon Body 有权
标题翻译：用于制造具有薄硅体的存储器件的结构和方法
公开(公告)号：US20140264541A1
公开(公告)日：2014-09-18
申请号：US13829392
申请日：2013-03-14
申请人： Conversant Intellectual Property Management Inc.
发明人： Hyoung Seub Rhie
IPC分类号： H01L29/792 , H01L21/3065
CPC分类号： H01L27/1157 , H01L21/28282 , H01L21/30604 , H01L27/11524 , H01L27/11551 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： Described herein is a structure and method of manufacturing for a memory device with a thin silicon body. The memory device may be a semiconductor comprising: a first dielectric of a first width; a second dielectric of a second width, the second width less than the first width; and a thin film polycrystalline silicon (poly-Si) on sidewalls of the second dielectric.
摘要翻译：这里描述了一种制造具有薄硅体的存储器件的结构和方法。存储器件可以是半导体，其包括：第一宽度的第一电介质; 第二宽度的第二电介质，所述第二宽度小于所述第一宽度; 以及在第二电介质的侧壁上的薄膜多晶硅（poly-Si）。

89. 发明申请

US20140257612A1 Method, Apparatus, Signals, and Medium for Managing Power in a Hybrid Vehicle 有权
标题翻译：用于管理混合动力车辆功率的方法，装置，信号和介质
公开(公告)号：US20140257612A1
公开(公告)日：2014-09-11
申请号：US14273305
申请日：2014-05-08
申请人： Conversant Intellectual Property Management Inc.
发明人： Wei Liu , Nicolas Louis Bouchon
IPC分类号： B60L15/20 , F02D29/02
CPC分类号： B60W20/10 , B60K6/48 , B60L7/18 , B60L11/005 , B60L11/14 , B60L11/1861 , B60L15/20 , B60L15/2009 , B60L15/2045 , B60L2240/12 , B60L2240/14 , B60L2240/421 , B60L2240/423 , B60L2240/425 , B60L2240/427 , B60L2240/429 , B60L2240/441 , B60L2240/443 , B60L2240/445 , B60L2240/486 , B60L2240/507 , B60L2240/545 , B60L2240/547 , B60L2240/549 , B60W10/06 , B60W10/08 , B60W10/26 , B60W20/00 , B60W20/11 , B60W2510/0623 , B60W2510/244 , B60W2520/10 , B60W2520/105 , F02D29/02 , Y02T10/56 , Y02T10/6221 , Y02T10/6286 , Y02T10/645 , Y02T10/70 , Y02T10/7005 , Y02T10/7022 , Y02T10/7044 , Y02T10/705 , Y02T10/7077 , Y02T10/72 , Y02T10/7258 , Y02T10/7283 , Y02T10/84 , Y10S903/903
摘要： A method and apparatus for managing power in a hybrid vehicle is disclosed. The vehicle includes an engine, an electric motor, and an energy storage element coupled to the motor. The method involves receiving a request to supply operating power to drive the vehicle and responding to the request by selecting an apportionment of operating power between the engine and the motor from among a plurality of apportionments having respective operating costs such that the selected apportionment is associated with a minimum operating cost, the operating cost including at least an engine fuel consumption cost and a storage element lifetime cost. The method further involves causing power to be supplied by at least one of the engine and the motor in accordance with the selected apportionment.
摘要翻译：公开了一种用于管理混合动力车辆中的动力的方法和装置。车辆包括发动机，电动机和联接到电动机的能量存储元件。该方法涉及通过从具有各自的运营成本的多个分配中选择发动机和电动机之间的操作功率的分配来响应该请求来提供操作电力的请求以使得所选择的分配与最低运行成本，运行成本至少包括发动机燃料消耗成本和存储元件寿命成本。该方法还包括根据所选择的分配使发动机和电动机中的至少一个供电。

90. 发明授权

US08767430B2 Configurable module and memory subsystem 有权
标题翻译：可配置模块和内存子系统
公开(公告)号：US08767430B2
公开(公告)日：2014-07-01
申请号：US13957713
申请日：2013-08-02
申请人： MOSAID Technologies Incorporated
发明人： Peter Gillingham , Roland Schuetz
IPC分类号： G11C5/02 , G11C5/00 , G11C5/06 , G11C8/00
CPC分类号： G11C5/025 , G06F13/1684 , G06F13/4022 , G06F13/4243 , G11C16/04
摘要： A configurable memory subsystem includes a memory module with a circuit board having a first and a second memory-containing device (MCD) pair mounted thereto. Each MCD pair has a first MCD in communication with a second MCD. Each MCD has an input port, an output port, and a memory each communicating with a bridge. In response to a command, the bridge transfers at least one of a portion of a data packet from the input port to the output port or to the memory, or transfers a portion of a memory packet from the memory to the output port. A loop-back device receives the command and the data packet form the first MCD pair and transmits the command and data packet to the second MCD pair.
摘要翻译：可配置存储器子系统包括具有电路板的存储器模块，该电路板具有安装在其上的第一和第二存储器容纳装置（MCD）对。每个MCD对具有与第二MCD通信的第一MCD。每个MCD都有一个输入端口，一个输出端口和一个与桥连通的存储器。响应于命令，桥将数据分组的一部分中的至少一个从输入端口传送到输出端口或存储器，或者将存储器分组的一部分从存储器传送到输出端口。环回装置从第一MCD对接收命令和数据包，并将命令和数据包发送到第二MCD对。

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