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81. 发明申请

US20110042640A1 METHOD OF FABRICATING PHASE CHANGE MEMORY CELL 失效
标题翻译：制备相变记忆细胞的方法
公开(公告)号：US20110042640A1
公开(公告)日：2011-02-24
申请号：US12917920
申请日：2010-11-02
申请人： Russell C. Zahorik
发明人： Russell C. Zahorik
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , H01L21/76816 , H01L45/1233 , H01L45/1253 , H01L45/144 , H01L45/16 , H01L45/1675 , Y10S438/947
摘要： A device with a memory array is disclosed. In one embodiment, the memory array includes a plurality of memory cells, each including an electrode and a phase change material. The electrode may be disposed on a substrate, the electrode having a sublithographic lateral dimension parallel to the substrate. The phase change material may be coupled to the electrode and include a lateral dimension parallel to the substrate and greater than the sublithographic lateral dimension of the electrode.
摘要翻译：公开了一种具有存储器阵列的器件。在一个实施例中，存储器阵列包括多个存储单元，每个存储单元包括电极和相变材料。电极可以设置在衬底上，电极具有平行于衬底的亚光刻横向尺寸。相变材料可以耦合到电极并且包括平行于衬底的横向尺寸并且大于电极的亚光刻横向尺寸。

82. 发明申请

US20110022873A1 SYSTEM WITH POWER SAVING DELAY LOCKED LOOP CONTROL 失效
标题翻译：具有节电延迟锁定环路控制的系统
公开(公告)号：US20110022873A1
公开(公告)日：2011-01-27
申请号：US12896151
申请日：2010-10-01
申请人： Adrian J. Drexler
发明人： Adrian J. Drexler
IPC分类号： G06F1/04
CPC分类号： G06F1/3228 , G06F1/3275 , G11C7/22 , G11C7/222 , G11C11/40615 , G11C11/4076 , Y02D10/14
摘要： The delay locked loop (“DLL”) delay interval can be locked to stop the DLL from wasting power in unnecessarily switching to synchronize the device with the DLL is associated to the system clock. This is achieved by adding logic sensing when a DRAM device will not imminently be called upon to output data and when the device has stabilized. Waiting for the DLL delay interval to stabilize before locking the delay interval still allows the DLL to immediately and effectively resume operations when the DLL is needed to synchronize the output of the DRAM device with the system clock. The DLL delay interval can be locked, together with the DLL clock, after the DRAM device is deselected by the chip select control line, after a number of no operation commands have been received, and/or after any command issued to the DRAM device has been completed.
摘要翻译：延迟锁定循环（“DLL”）延迟时间间隔可以被锁定，以阻止DLL浪费电源，不必要地切换，以使设备与与系统时钟相关联的DLL同步。这是通过在DRAM设备不会立即被要求输出数据和设备稳定时添加逻辑检测来实现的。在锁定延迟间隔之前等待DLL延迟时间间隔稳定，仍然允许DLL在需要DLL以使DRAM器件的输出与系统时钟同步时立即有效地恢复操作。在已经接收到多个无操作命令之后和/或在向DRAM设备发出任何命令之后，DLL延迟时间间隔可以与DLL时钟一起被锁定，在DRAM设备被芯片选择控制线取消选择之后已经完成

83. 发明申请

US20110013451A1 NON-VOLATILE MEMORY DEVICE WITH BOTH SINGLE AND MULTIPLE LEVEL CELLS 有权
标题翻译：具有多个单电平电池的非易失性存储器件
公开(公告)号：US20110013451A1
公开(公告)日：2011-01-20
申请号：US12893328
申请日：2010-09-29
申请人： Jin-Man Han
发明人： Jin-Man Han
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C2211/5641
摘要： A non-volatile memory array with both single level cells and multilevel cells. The single level and multilevel cells, in one embodiment, are alternated either along each bit line. An alternate embodiment alternates the single and multilevel cells along both the bit lines and the word lines so that no single level cell is adjacent to another single level cell in either the word line or the bit line directions.
摘要翻译：具有单级单元和多级单元的非易失性存储器阵列。在一个实施例中，单电平和多电平电池沿着每个位线交替。一个替代实施例沿着位线和字线交替单电层和多电平单元，使得没有单层单元与字线或位线方向上的另一单级单元相邻。

84. 发明申请

US20110006372A1 FORMATION OF STANDARD VOLTAGE THRESHOLD AND LOW VOLTAGE THRESHOLD MOSFET DEVICES 有权
标题翻译：形成标准电压阈值和低电压阈值MOSFET器件
公开(公告)号：US20110006372A1
公开(公告)日：2011-01-13
申请号：US12834231
申请日：2010-07-12
申请人： Mark Helm , Xianfeng Zhou
发明人： Mark Helm , Xianfeng Zhou
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823892 , H01L29/6659 , H01L29/7833
摘要： Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.
摘要翻译：孔形成在要制造第一和第二类型的标准Vt和低Vt装置的基板中。限定第一类型标准Vt器件的位置的阱被掩蔽，并且在限定第二类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个上执行第一电压阈值注入调整。限定第二类型标准Vt器件的位置的阱被屏蔽，并且对定义第一类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个执行第二电压阈值注入调整。然后在孔上形成掺杂的多晶硅栅极叠层。通过调节第一和第二电压阈值注入调整和多晶硅栅极堆叠掺杂中的至少一个来控制每个器件Vt的性能特征和控制。

85. 发明授权

US07869301B2 Apparatus for writing to multiple banks of a memory device 有权
标题翻译：用于写入存储器设备的多个组的装置
公开(公告)号：US07869301B2
公开(公告)日：2011-01-11
申请号：US12462433
申请日：2009-08-04
申请人： Timothy B. Cowles , Jeffrey P. Wright
发明人： Timothy B. Cowles , Jeffrey P. Wright
IPC分类号： G11C8/00
CPC分类号： G11C11/406 , G11C7/1015 , G11C7/1072 , G11C8/12 , G11C11/40611 , G11C11/40615 , G11C29/26 , G11C2029/2602
摘要： In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows for writing to any number of banks. More particularly, this method allows for writing to a selected number of banks between one and all banks. In addition, the method retains the discrete nature of the selected banks by allowing any row in each bank to be accessed regardless of the rows activated in other banks. As a result, rows of different memory banks that are intended to store similar data may be accessed simultaneously for purposes of writing the data in test and non-test modes. This allows for quicker writing to the SDRAM without the errors that may be created by other fast writing modes, such as data compression.
摘要翻译：在诸如同步动态随机存取存储器（SDRAM）的多存储体存储器系统中，提供了将数据写入存储体的方法。这种方法允许写入任意数量的银行。更具体地说，这种方法允许写入一个和所有银行之间的选定数量的银行。此外，该方法通过允许每个存储体中的任何行被访问而保留所选存储体的离散性质，而不管其他存储体中激活的行如何。因此，为了将数据写入测试和非测试模式的目的，可以同时访问旨在存储类似数据的不同存储体的行。这允许更快地写入SDRAM，而不会由其他快速写入模式（如数据压缩）创建的错误。

86. 发明授权

US07859408B2 Methods and systems of determining physical characteristics associated with objects tagged with RFID tags 有权
标题翻译：确定与RFID标签标签相关的物理特性的方法和系统
公开(公告)号：US07859408B2
公开(公告)日：2010-12-28
申请号：US11692538
申请日：2007-03-28
申请人： John R Tuttle
发明人： John R Tuttle
IPC分类号： G08B13/14
CPC分类号： G01S13/74 , G01S7/024 , G01S13/62 , G06K2017/0045
摘要： Methods and systems of determining physical characteristics associated with objects tagged with Radio Frequency Identification (RFID) tags. At least some of the illustrative embodiments are methods comprising making a first reading of a RFID tag coupled to an object (an electromagnetic signal received from the RFID tag having a first received signal strength indication (RSSI)), making a second reading of the RFID tag (an electromagnetic signal received from the RFID tag having a second RSSI), and a determining whether the object is moving using (at least in part) the first and second RSSI. Other illustrative embodiments, may determine (in addition to or in place of determining movement) orientation of the object based, at least in part, on the electromagnetic signals.
摘要翻译：确定与被标记有射频识别（RFID）标签的物体相关联的物理特性的方法和系统。至少一些示例性实施例是包括对耦合到对象的RFID标签（从具有第一接收信号强度指示（RSSI）的RFID标签接收的电磁信号）进行第一读取的方法，进行RFID的第二读取标签（从具有第二RSSI的RFID标签接收的电磁信号），以及使用（至少部分地）第一和第二RSSI来确定对象是否移动。其他说明性实施例可以至少部分地基于电磁信号来确定（除了或代替确定运动）对象的方向。

87. 发明授权

US07858429B2 Packaged microelectronic imagers and methods of packaging microelectronic imagers 有权
标题翻译：封装的微电子成像器和包装微电子成像器的方法
公开(公告)号：US07858429B2
公开(公告)日：2010-12-28
申请号：US11863087
申请日：2007-09-27
申请人： Salman Akram , Charles M. Watkins , Kyle K. Kirby , Alan G. Wood , William M. Hiatt
发明人： Salman Akram , Charles M. Watkins , Kyle K. Kirby , Alan G. Wood , William M. Hiatt
IPC分类号： H01L21/00 , G02F1/13
CPC分类号： H01L27/146 , H01L21/76898 , H01L27/14618 , H01L27/148 , H01L31/02016 , H01L2224/48227 , H01L2924/01046 , H01L2924/01066 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/00
摘要： Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrate, an integrated circuit, and an image sensor electrically coupled to the integrated circuit. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the substrate and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad, a dielectric liner deposited into the passage and in contact with the substrate, first and second conductive layers deposited onto at least a portion of the dielectric liner, and a conductive fill material deposited into the passage over at least a portion of the second conductive layer and electrically coupled to the bond-pad.
摘要翻译：本文公开了微电子成像器，用于封装微电子成像器的方法，以及用于在微电子成像器中形成导电晶片间互连的方法。在一个实施例中，微电子成像管芯可以包括微电子衬底，集成电路和电耦合到集成电路的图像传感器。接合焊盘由衬底承载并电耦合到集成电路。导电晶片互连延伸穿过衬底并与接合焊盘接触。互连可以包括完全延伸穿过衬底和接合焊盘的通道，沉积到通道中并与衬底接触的电介质衬垫，沉积在电介质衬垫的至少一部分上的第一和第二导电层以及导电在第二导电层的至少一部分上沉积到通道中并且电耦合到接合焊盘的填充材料。

88. 发明申请

US20100267226A1 Method of forming a structure over a semiconductor substrate 有权
标题翻译：在半导体衬底上形成结构的方法
公开(公告)号：US20100267226A1
公开(公告)日：2010-10-21
申请号：US12803296
申请日：2010-06-23
申请人： Kevin L. Beaman , John T. Moore
发明人： Kevin L. Beaman , John T. Moore
IPC分类号： H01L21/28
CPC分类号： H01L21/823842 , H01L21/823857 , H01L27/105 , H01L27/1052 , H01L27/11546 , Y10S257/90
摘要： The invention includes a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the silicon dioxide is at least 10 Å above the substrate. After the nitrogen is formed within the silicon dioxide layer, conductively doped silicon is formed on the silicon dioxide layer.
摘要翻译：本发明包括在半导体衬底上形成结构的方法。在至少一些基底上形成含二氧化硅层。在含二氧化硅层内形成氮。二氧化硅内的基本上所有的氮基本上都在基底上方至少10埃。在二氧化硅层内形成氮之后，在二氧化硅层上形成导电掺杂的硅。

89. 再颁专利

USRE41730E1 Method for operating a CMOS imager having a pipelined analog to digital converter 有权
标题翻译：用于操作具有流水线模数转换器的CMOS成像器的方法
公开(公告)号：USRE41730E1
公开(公告)日：2010-09-21
申请号：US11896442
申请日：2007-08-31
申请人： Eric R. Fossum , Sandor L. Barna
发明人： Eric R. Fossum , Sandor L. Barna
IPC分类号： H03M1/34
CPC分类号： H03M1/18 , H03M1/1215 , H03M1/46
摘要： An image sensor system using offset analog to digital converters. The analog to digital converters require a plurality of clock cycles to carry out the actual conversion. These conversions are offset in time from one another, so that at each clock cycle, new data is available.
摘要翻译：公开了一种方法，其中图像传感器使用流水线模数转换器将模拟信号转换为数字信号

90. 发明申请

US20100220103A1 MEMORY SYSTEM AND METHOD FOR IMPROVED UTILIZATION OF READ AND WRITE BANDWIDTH OF A GRAPHICS PROCESSING SYSTEM 有权
标题翻译：用于图形处理系统的读取和写入带宽的改进的存储器系统和方法
公开(公告)号：US20100220103A1
公开(公告)日：2010-09-02
申请号：US12775776
申请日：2010-05-07
申请人： William Radke
发明人： William Radke
IPC分类号： G06T1/20 , G06F12/02
CPC分类号： G09G5/39 , G09G2360/123
摘要： A system and method for processing graphics data which requires less read and write bandwidth. The graphics processing system includes an embedded memory array having at least three separate banks of single-ported memory in which graphics data are stored. A memory controller coupled to the banks of memory writes post-processed data to a first bank of memory while reading data from a second bank of memory. A synchronous graphics processing pipeline processes the data read from the second bank of memory and provides the post-processed graphics data to the memory controller to be written back to a bank of memory. The processing pipeline concurrently processes an amount of graphics data at least equal to that included in a page of memory. A third bank of memory is precharged concurrently with writing data to the first bank and reading data from the second bank in preparation for access when reading data from the second bank of memory is completed.
摘要翻译：用于处理需要较少读写带宽的图形数据的系统和方法。图形处理系统包括嵌入式存储器阵列，其具有存储图形数据的至少三个独立的单端口存储器组。耦合到存储体的存储器控制器将从第二存储器存储器读取数据的后处理数据写入第一存储体。同步图形处理流水线处理从第二存储体读出的数据，并将后处理的图形数据提供给存储器控制器以写回存储体。处理流水线同时处理至少等于包含在存储器页面中的数量的图形数据。当从第二存储器存储器读取数据完成时，第三存储器组同时对第一存储体写入数据并从第二存储体读取数据以准备访问。

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