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81. 发明授权

US07259588B2 Tri-state detection circuit for use in devices associated with an imaging system 有权
标题翻译：用于与成像系统相关的装置的三态检测电路
公开(公告)号：US07259588B2
公开(公告)日：2007-08-21
申请号：US10629008
申请日：2003-07-29
申请人： Adam Jude Ahne
发明人： Adam Jude Ahne
IPC分类号： H03K19/02
CPC分类号： G06K15/00 , H03M7/06
摘要： A tri-state detection circuit includes a first input port for receiving a tri-state input signal, a clock input port for receiving a clocking signal, a first output port, a second output port coupled to the first input port, a D-flip-flop and a buffer. The D-flip-flop has a D input, a clock input CLK, and a Q output. The D input is tied high. The clock input CLK is coupled to the first input port. The Q output is coupled to the first output port. The buffer has a buffer input and a buffer output. The buffer input is coupled to the clock input port. The buffer output is coupled to the clock input CLK of the D-flip-flop.
摘要翻译：三态检测电路包括用于接收三态输入信号的第一输入端口，用于接收时钟信号的时钟输入端口，第一输出端口，耦合到第一输入端口的第二输出端口，D触发器 -flop和缓冲区。 D触发器具有D输入，时钟输入CLK和Q输出。 D输入为高电平。时钟输入CLK耦合到第一输入端口。 Q输出耦合到第一输出端口。缓冲区具有缓冲区输入和缓冲区输出。缓冲器输入端连接到时钟输入端口。缓冲器输出耦合到D触发器的时钟输入CLK。

82. 发明申请

US20050091624A1 Molecular logic gates 失效
标题翻译：分子逻辑门
公开(公告)号：US20050091624A1
公开(公告)日：2005-04-28
申请号：US10693150
申请日：2003-10-23
申请人： Richard Baugh , Yong Chen
发明人： Richard Baugh , Yong Chen
IPC分类号： G06F17/50 , H03K19/02
CPC分类号： H03K19/02 , Y10S977/94
摘要： Various nanoscale logic gates are disclosed. An alternating current (“AC”) source is superimposed on a direct-current (“DC”), largely resistor-based nanoscale logic circuit in order to provide distinguishable, AC current or voltage logical output signals despite potentially narrow DC-voltage or DC-current ranges produced by the resistor-based nanoscale logic circuit. AC-enhanced AND, OR, NAND, and NOR nanoscale logic gates are provided as four specific embodiments of the present invention.
摘要翻译：公开了各种纳米级逻辑门。交流（“AC”）源叠加在直流（“DC”）上，基本上是基于电阻的纳米尺度逻辑电路，以便提供可区分的交流电流或电压逻辑输出信号，尽管潜在的直流电压或直流 - 由电阻器型纳米尺度逻辑电路产生的电流范围。 AC增强型AND，OR，NAND和NOR纳米级逻辑门作为本发明的四个具体实施例提供。

83. 发明授权

US06867988B2 Magnetic logic elements 有权
标题翻译：磁逻辑元件
公开(公告)号：US06867988B2
公开(公告)日：2005-03-15
申请号：US10432007
申请日：2001-11-19
申请人： Russell Paul Cowburn
发明人： Russell Paul Cowburn
IPC分类号： B82B1/00 , G06N99/00 , G11C11/14 , G11C13/02 , G11C19/08 , H03K19/02 , H03K19/18
CPC分类号： H03K19/18 , B82Y10/00 , G06N99/002 , G11C11/14 , G11C19/0816 , G11C2213/81
摘要： A magnetic logic element for a logic device is described formed by at least one conduit capable of sustaining and propagating a magnetic soliton, the conduit being adapted by the provision of nodes and/or directional changes giving rise to discontinuities in soliton propagation energy as a result of which logical functions may be processed. Magnetic logic devices such as interconnects and gates, and magnetic logic circuits incorporating such devices and suitable operational fields, are also described.
摘要翻译：描述了用于逻辑器件的磁逻辑元件，其由能够维持和传播磁孤子的至少一个导管形成，该导管通过提供节点和/或导致孤子传播能量不连续性的方向变化来适应，结果可以处理哪些逻辑功能。还描述了诸如互连和门的磁逻辑器件以及并入这种器件的磁逻辑电路和合适的操作领域。

84. 发明授权

US5900744A Method and apparatus for providing a high speed tristate buffer 失效
标题翻译：用于提供高速三态缓冲器的方法和装置
公开(公告)号：US5900744A
公开(公告)日：1999-05-04
申请号：US774431
申请日：1996-12-30
申请人： Bharat K. Bisen , Sudarshan Kumar
发明人： Bharat K. Bisen , Sudarshan Kumar
IPC分类号： H03K19/094 , H03K19/02 , H03K19/096
CPC分类号： H03K19/09429
摘要： A method and apparatus for providing a high speed tristate buffer. The buffer includes a p-channel pull-up transistor and a transfer gate. The source of the transistor is coupled to a voltage supply. The drain of the transistor is coupled to the buffer output. The gate of the transfer gate is coupled to a first clock source. The input to the transfer gate is a second clock source, and the output of the transfer gate is coupled to the gate of the p-channel transistor.
摘要翻译：一种用于提供高速三态缓冲器的方法和装置。该缓冲器包括一个p沟道上拉晶体管和一个传输门。晶体管的源极耦合到电压源。晶体管的漏极耦合到缓冲器输出端。传输门的栅极耦合到第一时钟源。传输门的输入是第二个时钟源，传输门的输出耦合到p沟道晶体管的栅极。

85. 发明授权

US5754061A Bi-CMOS circuits with enhanced power supply noise suppression and enhanced speed 失效
标题翻译：双CMOS电路具有增强的电源噪声抑制和增强的速度
公开(公告)号：US5754061A
公开(公告)日：1998-05-19
申请号：US718015
申请日：1996-09-03
申请人： Shinzou Satou , Kou Ebihara , Akiyoshi Suzuki , Keisuke Ishiwata , Kouji Miki , Hitoshi Ohmichi , Tamio Miyamura , Masamichi Kamiyama
发明人： Shinzou Satou , Kou Ebihara , Akiyoshi Suzuki , Keisuke Ishiwata , Kouji Miki , Hitoshi Ohmichi , Tamio Miyamura , Masamichi Kamiyama
IPC分类号： H03K19/08 , H03K19/00 , H03K19/003 , H03K19/013 , H03K19/02 , H03K17/04
CPC分类号： H03K19/00353 , H03K19/001 , H03K19/0136
摘要： A Bi-CMOS circuit includes a first bipolar, a second bipolar transistor and a CMOS control unit for performing switching controls of the first and second bipolar transistors on the basis of an input signal applied to an input terminal and for controlling an output signal output via the output terminal on the basis of the input signal. A turn-OFF unit temporality couples the base of the first bipolar transistor to a low-potential side power supply line on the basis of a current flowing in said control means when the first bipolar transistor is turned OFF, so that the first bipolar transistor can be rapidly turned OFF.
摘要翻译：一种双CMOS电路包括第一双极型，第二双极晶体管和CMOS控制单元，用于根据施加到输入端的输入信号执行第一和第二双极晶体管的开关控制，并用于控制输出信号经由输出端基于输入信号。基于在第一双极晶体管截止时流过所述控制装置的电流，关断单元暂时性将第一双极晶体管的基极连接到低电位侧电源线，使得第一双极晶体管可快速关闭。

86. 发明授权

US5524088A Multi-functional operating circuit providing capability of freely combining operating functions 失效
标题翻译：多功能操作电路提供自由组合操作功能的功能
公开(公告)号：US5524088A
公开(公告)日：1996-06-04
申请号：US224654
申请日：1994-04-06
申请人： Yukihiro Yoshida
发明人： Yukihiro Yoshida
IPC分类号： G06F7/49 , G06F7/57 , H03K19/02 , G06F7/00 , G06F7/38
CPC分类号： G06F7/57 , G06F7/49 , H03K19/02 , G06F2207/382
摘要： A multi-functional operating circuit provides a flexible architecture for dynamically or statically changing plural operating functions in a manner to complex the operating units needing the fastest speed, prevent an electric delay of a signal or be integrated at higher density. The multi-functional operating circuit includes plural operating circuit units having any-valued adding unit, subtracting unit, multiplying unit, squaring unit and logical operating unit, and plural instruction decoders for dynamically or statically selecting plural operating units for controlling a selected combination of these operating units in response to micro orders derived from external instructions in a manner to apply to the necessary operating function.
摘要翻译：多功能操作电路提供了一种灵活的架构，用于动态或静态地改变多个操作功能，以便使需要最快速度的操作单元复杂化，防止信号的电延迟或以更高的密度集成。多功能操作电路包括具有任何值的加法单元，减法单元，乘法单元，平方单元和逻辑运算单元的多个运算电路单元，以及用于动态或静态选择多个运算单元的多个指令解码器，用于控制这些运算单元操作单元响应来自外部指令的微指令以适用于必要操作功能的方式。

87. 发明授权

US5467313A Level shifter and data output buffer having same 失效
标题翻译：电平移位器和数据输出缓冲器具有相同的功能
公开(公告)号：US5467313A
公开(公告)日：1995-11-14
申请号：US273746
申请日：1994-07-12
申请人： Chul-min Jung , Jeong-hee Lee , Kee-sik Ahn , Hee-chul Park
发明人： Chul-min Jung , Jeong-hee Lee , Kee-sik Ahn , Hee-chul Park
IPC分类号： B28B11/14 , G11C7/10 , H03K19/00 , H03K19/0175 , G11C7/00 , H03K19/02
CPC分类号： G11C7/1057 , G11C7/1051 , H03K19/0013 , H03K19/017527
摘要： A level shifter and a data output buffer adapted for use in a semiconductor memory device including a memory cell for storing data, a sense amplifier for amplifying data read from the memory cell and generating an ECL-level output signal, and a level shifter for converting the ECL-level output signals into a CMOS-level signal, wherein the level shifter has a level shifting means receiving the ECL-level data signals, converting the input data to CMOS-levels, and outputting a result, and a delay for delaying the result so as to control its current consumption of the level shifter.
摘要翻译：适用于包括存储数据的存储单元的半导体存储器件的电平移位器和数据输出缓冲器，用于放大从存储单元读取的数据并产生ECL电平输出信号的读出放大器，以及用于转换的电平转换器 ECL电平输出信号为CMOS电平信号，其中电平移位器具有接收ECL电平数据信号的电平移位装置，将输入数据转换为CMOS电平，并输出结果，以及延迟延迟结果是为了控制其电平移位器的电流消耗。

88. 发明授权

US5444397A All-CMOS high-impedance output buffer for a bus driven by multiple power-supply voltages 失效
标题翻译：全CMOS高阻抗输出缓冲器，用于由多个电源电压驱动的总线
公开(公告)号：US5444397A
公开(公告)日：1995-08-22
申请号：US318238
申请日：1994-10-05
申请人： Anthony Y. Wong , David Kwong , Lee Yang , Charles Hsiao
发明人： Anthony Y. Wong , David Kwong , Lee Yang , Charles Hsiao
IPC分类号： H03K19/00 , H01L27/02 , H01L27/118 , H03K19/003 , H03K19/0175 , H03K19/0948 , H03K19/02
CPC分类号： H03K19/00315 , H01L27/0218 , H01L27/11898 , H03K2217/0018
摘要： An all-CMOS output buffer drives a bus that can operate at 3 volts and 5 volts. When in a high-impedance state, the output buffer draws little or no current. If the bus is driven to 5 volts by an external device, the high impedance output buffer is in danger of latch-up and distortion of the bus logic level since it only has a 3-volt power supply and does not use a charge pump or an extra 5-volt supply. A biasing circuit couples an N-well that contains p-channel transistors and a driver transistor to the bus driven to 5 volts. Thus the N-well is also driven to 5 volts, the voltage on the bus. The gate of the p-channel driver transistor in the high-impedance output buffer is also coupled to the N-well by another p-channel transistor, raising the gate potential to 5 volts. Thus the gate and body of the p-channel driver transistor is at 5 volts, eliminating reversing current and latch-up problems. A transmission gate isolates the gate of the p-channel driver transistor from the rest of the device's circuitry. The p-channel transistors of the transmission gate, bias circuitry, and driver transistor are located in the N-well, which is biased up to 5 volts only when necessary. Thus during normal operation, the N-well of the driver transistor is at 3 volts, eliminating a performance loss from the body effect. A logic gate increases the well bias and isolates the driver's gate only when necessary, when the bus is high and driven by a 5-volt device, and the output buffer is in high-impedance.
摘要翻译：全CMOS输出缓冲器驱动可在3伏和5伏电压下工作的总线。当处于高阻抗状态时，输出缓冲器很少或没有电流。如果总线通过外部设备驱动到5伏特，则高阻抗输出缓冲器可能会因总线逻辑电平而产生闩锁和失真，因为它只有3伏电源，不使用电荷泵或额外的5伏电源。偏置电路将包含p沟道晶体管的N阱和驱动晶体管耦合到被驱动到5伏特的总线。因此，N阱也被驱动到5伏，即总线上的电压。高阻抗输出缓冲器中的p沟道驱动晶体管的栅极也通过另一个p沟道晶体管耦合到N阱，将栅极电位提高到5伏。因此，p沟道驱动晶体管的栅极和体是5伏特，消除了反向电流和闭锁问题。传输门将p沟道驱动晶体管的栅极与器件电路的其余部分隔离。传输门，偏置电路和驱动晶体管的p沟道晶体管位于N阱中，仅在必要时才被偏置到5伏特。因此，在正常工作期间，驱动晶体管的N阱处于3伏特，消除了体内效应的性能损失。逻辑门增加了阱偏压，只有当必要时才能将驱动器门隔离，当总线为高电平并由5伏器件驱动时，输出缓冲器处于高阻态。

89. 发明授权

US5434519A Self-resetting CMOS off-chip driver 失效
标题翻译：自复位CMOS片外驱动器
公开(公告)号：US5434519A
公开(公告)日：1995-07-18
申请号：US321641
申请日：1994-10-11
申请人： Thanh D. Trinh , Satyajit Dutta , Stanley E. Schuster , Tai A. Cao , Thai Q. Nguyen
发明人： Thanh D. Trinh , Satyajit Dutta , Stanley E. Schuster , Tai A. Cao , Thai Q. Nguyen
IPC分类号： H03K19/094 , H03K19/02
CPC分类号： H03K19/09429
摘要： A self-resetting CMOS off-chip diver includes a first pair of complementary FETs connected in series to receive first and second complementary drive signals from an on-chip source. A latch is connected to an output of the first pair of complementary FETs for latching said drive signals. The first pair of complementary FETs in combination with the latch form a unique "pulse catcher" circuit capable of catching and latching short duration pulses characteristic of the self-resetting (SR) mode, providing the transfer between the SR mode and the output static mode. A low power three state static driver circuit is comprised of first and second pass gates connected to pass an output of the latch and a second pair of complementary FETs respectively connected to receive outputs of the first and second pass gates to generate a static output for driving a transmission line. Pull-up and pull-down devices are connected to respective inputs of the second pair of complementary FETs and controlled by the control means to provide a three state function output. The three state static circuit provides high speed data transfer with a high drive capability full swing signal output. An enable circuit implementing four enable functions, including a testability function, is connected to the first and second pass gates to inhibit an output to the second pair of complementary FETs in the test mode. Pull-up and pull-down devices are connected to respective inputs of the second pair of complementary FETs and controlled by the enable circuit to provide the three state function output, including a high impedance state.
摘要翻译：自复位CMOS片外潜水员包括串联连接的第一对互补FET，以从芯片上的源接收第一和第二补偿驱动信号。锁存器连接到第一对互补FET的输出端，用于锁存所述驱动信号。第一对互补FET与锁存器组合形成一个独特的“脉冲捕获器”电路，能够捕获和锁存特性为自复位（SR）模式的短持续时间脉冲，提供SR模式和输出静态模式之间的传输。低功率三态静态驱动器电路包括连接以通过锁存器的输出的第一和第二通过门，以及分别连接以接收第一和第二通过门的输出的第二对互补FET，以产生用于驱动的静态输出传输线。上拉和下拉器件连接到第二对互补FET的相应输入，并由控制装置控制以提供三态功能输出。三态静态电路提供具有高驱动能力的全速信号输出的高速数据传输。实现四个使能功能（包括可测试性功能）的使能电路连接到第一和第二传递门，以在测试模式中禁止输出到第二对互补FET。上拉和下拉器件连接到第二对互补FET的相应输入，并由使能电路控制，以提供包括高阻态的三态功能输出。

90. 发明授权

US5422496A Interband single-electron tunnel transistor and integrated circuit 失效
标题翻译：带间单电子隧道晶体管和集成电路
公开(公告)号：US5422496A
公开(公告)日：1995-06-06
申请号：US117801
申请日：1993-09-08
申请人： Shiroo Kamohara , Toru Toyabe , Kozo Katayama , Shuichi Yamamoto , Sigeo Ihara
发明人： Shiroo Kamohara , Toru Toyabe , Kozo Katayama , Shuichi Yamamoto , Sigeo Ihara
IPC分类号： H01L21/82 , H01L21/8232 , H01L21/8244 , H01L27/06 , H01L27/095 , H01L27/10 , H01L27/11 , H01L27/118 , H01L29/66 , H01L29/68 , H01L29/72 , H01L29/762 , H01L29/80 , H01L29/88 , H03K19/02
CPC分类号： B82Y10/00 , B82Y30/00 , H01L27/118 , H01L29/72 , H01L29/762 , H01L29/88 , H03K19/02 , Y10S977/937
摘要： An interband single-electron tunnel/transistor utilizes an interband single-electron tunneling phenomenon between a valence band and a conduction band through a p-n junction. The transistor includes the combination of microcapacities as fundamental constituent elements each formed by joining a p-type semiconductor material doped with an impurity in the degree of concentration with which a Fermi level overlaps a valence band and an n-type semiconductor material doped with an impurity in the degree of concentration with which the Fermi level overlaps a conduction band. The microcapacity includes a p-n junction having a junction area with which interband electron tunneling is inhibited due to Coulomb blockade.
摘要翻译：带间单电子隧道/晶体管利用通过p-n结的价带和导带之间的带间单电子隧道现象。晶体管包括作为基本构成元件的微电容的组合，其通过将掺杂有杂质的p型半导体材料以费米能级与价带重叠的浓度与掺杂有杂质的n型半导体材料接合而形成在费米能级与导带重叠的浓度下。微容量包括具有结区的p-n结，由于库仑阻挡，带间电子隧穿被阻止。

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