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1. 发明授权

US08700981B2 Low latency enumeration endec 有权
标题翻译：低延迟枚举endec
公开(公告)号：US08700981B2
公开(公告)日：2014-04-15
申请号：US13296022
申请日：2011-11-14
申请人： Victor Krachkovsky , Wu Chang , Razmik Karabed , Shaohua Yang
发明人： Victor Krachkovsky , Wu Chang , Razmik Karabed , Shaohua Yang
IPC分类号： H03M13/00
CPC分类号： H03M13/1102 , G11B2020/1287 , G11B2020/1476 , G11B2220/2516 , H03M13/33 , H03M13/6331
摘要： Various embodiments of the present invention provide apparatuses and methods for encoding and decoding data.
摘要翻译：本发明的各种实施例提供用于对数据进行编码和解码的装置和方法。

2. 发明授权

US08634250B2 Methods and apparatus for programming multiple program values per signal level in flash memories 有权
标题翻译：闪存中每个信号电平编程多个程序值的方法和装置
公开(公告)号：US08634250B2
公开(公告)日：2014-01-21
申请号：US13001295
申请日：2009-07-21
申请人： Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Nenad Miladinovic , Andrei Vityaev , Johnson Yen
发明人： Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Nenad Miladinovic , Andrei Vityaev , Johnson Yen
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427 , G11C16/3454 , G11C2211/5621
摘要： Methods and apparatus are provided for programming multiple program values per signal level in flash memories. A flash memory device having a plurality of program values is programmed by programming the flash memory device for a given signal level, wherein the programming step comprises a programming phase and a plurality of verify phases. In another variation, a flash memory device having a plurality of program values is programmed, and the programming step comprises a programming phase and a plurality of verify phases, wherein at least one signal level comprises a plurality of the program values. The signal levels or the program values (or both) can be represented using one or more of a voltage, a current and a resistance.
摘要翻译：提供了用于在闪速存储器中编程每个信号电平的多个程序值的方法和装置。具有多个编程值的闪速存储器件通过针对给定的信号电平对闪速存储器件进行编程来编程，其中编程步骤包括编程阶段和多个验证阶段。在另一个实施例中，编程具有多个编程值的闪速存储器件，并且编程步骤包括编程阶段和多个验证阶段，其中至少一个信号电平包括多个程序值。可以使用电压，电流和电阻中的一个或多个来表示信号电平或程序值（或两者）。

3. 发明授权

US08526230B2 Methods and apparatus for write-side intercell interference mitigation in flash memories 失效
标题翻译： Flash存储器中写入侧小区间干扰减轻的方法和装置
公开(公告)号：US08526230B2
公开(公告)日：2013-09-03
申请号：US13001286
申请日：2009-06-30
申请人： Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Nenad Miladinovic , Andrei Vityaev , Johnson Yen
发明人： Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Nenad Miladinovic , Andrei Vityaev , Johnson Yen
IPC分类号： G11C16/04
CPC分类号： G11C16/3427 , G06F11/1072 , G11C5/00 , G11C7/02 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/3418
摘要： Methods and apparatus are provided for write-side intercell interference mitigation in flash memories. A flash memory device is written by obtaining program data to be written to at least one target cell in the flash memory; obtaining one or more bits of program data for at least one aggressor cell to be programmed later than the target cell: and precompensating for intercell interference for the target cell by generating precompensated program values. The aggressor cells comprise one or more cells adjacent to the target cell, such as adjacent cells in a same wordline as the target cell and/or cells in an upper or lower adjacent wordline to the target cell. The precompensated program values for the target cell are optionally provided to the flash memory.
摘要翻译：提供了用于闪存中的写侧小区间干扰减轻的方法和装置。通过获得写入到闪速存储器中的至少一个目标单元的程序数据来写入闪速存储器件; 为至少一个侵略者单元获得待编程的比目标小区晚的一个或多个程序数据位;并且通过产生预补偿的程序值来预补偿目标小区的小区间干扰。侵略者细胞包括与靶细胞相邻的一个或多个细胞，例如与靶细胞相同的字线中的相邻细胞和/或与靶细胞的上或下相邻字线中的细胞。目标单元的预补偿程序值可选地提供给闪存。

4. 发明授权

US09026572B2 Systems and methods for anti-causal noise predictive filtering in a data channel 有权
标题翻译：数据通道中反因果噪声预测滤波的系统和方法
公开(公告)号：US09026572B2
公开(公告)日：2015-05-05
申请号：US13220142
申请日：2011-08-29
申请人： Wu Chang , Victor Krachkovsky , Fan Zhang , Shaohua Yang
发明人： Wu Chang , Victor Krachkovsky , Fan Zhang , Shaohua Yang
IPC分类号： G06F17/10 , H04L25/06 , H04L25/03
CPC分类号： H04L25/067 , G06F17/10 , H04L25/03038
摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit. The data detector circuit includes an anti-causal noise predictive filter circuit and a data detection circuit. In some cases, the anti-causal noise predictive filter circuit is operable to apply noise predictive filtering to a detector input to yield a filtered output, and the data detection circuit is operable to apply a data detection algorithm to the filtered output derived from the anti-causal noise predictive filter circuit.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。作为示例，公开了包括数据检测器电路的数据处理电路。数据检测电路包括反因果噪声预测滤波器电路和数据检测电路。在一些情况下，反因果噪声预测滤波器电路可操作以将噪声预测滤波应用于检测器输入以产生滤波输出，并且数据检测电路可操作以将数据检测算法应用于从反向 - 因果噪声预测滤波电路。

5. 发明授权

US08892966B2 Methods and apparatus for soft data generation for memory devices using decoder performance feedback 有权
标题翻译：用于使用解码器性能反馈的存储器件的软数据生成的方法和装置
公开(公告)号：US08892966B2
公开(公告)日：2014-11-18
申请号：US13063899
申请日：2009-09-30
申请人： Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Nenad Miladinovic , Andrei Vityaev , Clifton Williamson , Johnson Yen
发明人： Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Nenad Miladinovic , Andrei Vityaev , Clifton Williamson , Johnson Yen
IPC分类号： G06F11/00 , G11C29/00 , G11C7/04 , G11C16/04 , G11C16/26 , G11C7/02 , G11C16/34 , G11C11/56
CPC分类号： G11C16/26 , G06F11/1012 , G06F11/1068 , G06F12/0246 , G06F2212/1032 , G06F2212/2022 , G11C7/02 , G11C7/04 , G11C11/16 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C2211/5634
摘要： Methods and apparatus for soft data generation for memory devices using decoder performance feedback. At least one soft data value is generated in a memory device, by obtaining performance feedback from a decoder; obtaining an error statistic based on the performance feedback; and generating the at least one soft data value based on the obtained error statistic. The performance feedback comprises one or more of decoded bits, a number of erroneous bits based on data decoded by the decoder and a number of unsatisfied parity checks.
摘要翻译：用于使用解码器性能反馈的存储器件的软数据生成的方法和装置。通过从解码器获得性能反馈，在存储器件中产生至少一个软数据值; 基于性能反馈获得误差统计; 以及基于所获得的误差统计量生成所述至少一个软数据值。性能反馈包括解码比特中的一个或多个，基于由解码器解码的数据的多个错误比特和多个不满足的奇偶校验。

6. 发明申请

US20130124950A1 Low Latency Enumeration Endec 有权
标题翻译：低延迟枚举Endec
公开(公告)号：US20130124950A1
公开(公告)日：2013-05-16
申请号：US13296022
申请日：2011-11-14
申请人： Victor Krachkovsky , Wu Chang , Razmik Karabed , Shaohua Yang
发明人： Victor Krachkovsky , Wu Chang , Razmik Karabed , Shaohua Yang
IPC分类号： G06F11/07
CPC分类号： H03M13/1102 , G11B2020/1287 , G11B2020/1476 , G11B2220/2516 , H03M13/33 , H03M13/6331
摘要： Various embodiments of the present invention provide apparatuses and methods for encoding and decoding data.
摘要翻译：本发明的各种实施例提供用于对数据进行编码和解码的装置和方法。

7. 发明申请

US20110216586A1 Methods And Apparatus For Intercell Interference Mitigation Using Modulation Coding 有权
标题翻译：使用调制编码的小区间干扰减轻的方法和装置
公开(公告)号：US20110216586A1
公开(公告)日：2011-09-08
申请号：US13001310
申请日：2009-06-30
申请人： Nils Graef , Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Andrei Vityaev , Johnson Yen
发明人： Nils Graef , Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Andrei Vityaev , Johnson Yen
IPC分类号： G11C16/12 , G11C16/04 , G11C16/26
CPC分类号： G11C16/3427 , G06F11/1072 , G11C5/00 , G11C7/02 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/3418
摘要： Methods and apparatus are provided for intercell interference mitigation using modulation coding. During programming of a flash memory, a modulation encoding is performed that selects one or more levels for programming the flash memory such that a reduced number of cells in the flash memory are programmed with a value that violates one or more predefined criteria. During a reading of a flash memory, a modulation decoding is performed that assigns one or more levels to cells in the flash memory such that a reduced number of cells in the flash memory are read with a value that violates one or more predefined criteria. The predefined criteria can be based, for example, on one or more of an amount of disturbance caused by the programmed cell; a voltage shift of a programmed cell: a voltage stored by a programmed cell; an amount of change in current through a programmed cell; and an amount of current through a programmed cell.
摘要翻译：提供了使用调制编码的小区间干扰减轻的方法和装置。在闪速存储器的编程期间，执行调制编码，其选择用于编程闪速存储器的一个或多个级别，使得闪存中的减少数量的单元被编程为具有违反一个或多个预定标准的值。在读取闪速存储器期间，执行调制解码，其向闪存中的单元分配一个或多个电平，使得闪存中的单元数目减少，其值违反一个或多个预定准则。预定义的标准可以例如基于由编程的小区引起的干扰量的一个或多个; 编程单元的电压偏移：由编程单元存储的电压; 通过编程单元的电流变化量; 以及通过编程单元的电流量。

8. 发明授权

US07734993B2 Method and apparatus for encoding and precoding digital data within modulation code constraints 失效
标题翻译：用于在调制码约束内对数字数据进行编码和预编码的方法和装置
公开(公告)号：US07734993B2
公开(公告)日：2010-06-08
申请号：US12103860
申请日：2008-04-16
申请人： Victor Krachkovsky , Xiaotong Lin
发明人： Victor Krachkovsky , Xiaotong Lin
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： G11B20/1426 , G11B20/10009
摘要： Embodiments of the invention include a method and apparatus for encoding data and a system for transmitting and/or storing data, in which the data is encoded and precoded in a manner that does not violate previously established data constraints, such as modulation encoding constraints. The method includes the steps of modulation encoding the data using a modulation code defined by at least one modulation constraint, parity encoding the modulation encoded information, and preceding the encoded information. The preceding step either partially precodes information bits and precodes parity bits, precodes information bits but not parity bits, or precodes both information bits and parity bits in such a manner that does not violate modulation constraints. Also, the parity encoding step can be performed in such a manner that does not violate modulation code constraints.
摘要翻译：本发明的实施例包括用于对数据进行编码的方法和装置以及用于发送和/或存储数据的系统，其中以不违反先前建立的数据约束（诸如调制编码约束）的方式对数据进行编码和预编码。该方法包括以下步骤：使用由至少一个调制约束定义的调制码，对调制编码信息进行奇偶校验，以及编码信息之前对数据进行调制编码。上述步骤部分地预编码信息比特，并且以不违反调制约束的方式预编码奇偶校验位，预编码信息比特，而不是奇偶校验位，或者对信息比特和奇偶校验比特进行预编码。此外，奇偶校验编码步骤可以以不违反调制码约束的方式执行。

9. 发明授权

US09378835B2 Methods and apparatus for soft data generation for memory devices based using reference cells 有权
标题翻译：用于基于参考单元的存储器件软数据生成的方法和装置
公开(公告)号：US09378835B2
公开(公告)日：2016-06-28
申请号：US13063895
申请日：2009-09-30
申请人： Harley F. Burger, Jr. , Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Nenad Miladinovic , Andrei Vityaev , Johnson Yen
发明人： Harley F. Burger, Jr. , Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Nenad Miladinovic , Andrei Vityaev , Johnson Yen
IPC分类号： G11C11/409 , G11C11/16 , G06F12/02 , G11C16/26 , G11C7/02 , G11C7/04 , G11C11/56 , G11C16/04 , G11C16/34 , G06F11/10
CPC分类号： G11C16/26 , G06F11/1012 , G06F11/1068 , G06F12/0246 , G06F2212/1032 , G06F2212/2022 , G11C7/02 , G11C7/04 , G11C11/16 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C2211/5634
摘要： Methods and apparatus are provided for soft data generation for memory devices using reference cells. At least one soft data value is generated in a memory device by writing a known data to one or more reference cells; reading one or more of the reference cells; obtaining a read statistic based on the read one or more reference cells; and obtaining the at least one soft data value based on the obtained read statistic. The read statistics can optionally be obtained for one or more desired locations of a memory array; or for a given pattern, PATT, in one or more aggressor cells. The read statistic can optionally comprise asymmetric statistics obtained for a plurality of possible values.
摘要翻译：提供了用于使用参考单元的存储器件的软数据生成的方法和装置。通过将已知数据写入一个或多个参考单元，在存储器件中产生至少一个软数据值; 读取一个或多个参考细胞; 基于读取的一个或多个参考单元获得读取统计量; 以及基于获得的读取统计量获得所述至少一个软数据值。可以可选地为存储器阵列的一个或多个所需位置获得读取统计; 或者对于一个或多个侵略者细胞中的给定模式PATT。读取统计可以可选地包括为多个可能值获得的不对称统计量。

10. 发明授权

US08797795B2 Methods and apparatus for intercell interference mitigation using modulation coding 有权
标题翻译：使用调制编码的小区间干扰减轻的方法和装置
公开(公告)号：US08797795B2
公开(公告)日：2014-08-05
申请号：US13001310
申请日：2009-06-30
申请人： Nils Graef , Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Andrei Vityaev , Johnson Yen
发明人： Nils Graef , Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Andrei Vityaev , Johnson Yen
IPC分类号： G11C16/04
CPC分类号： G11C16/3427 , G06F11/1072 , G11C5/00 , G11C7/02 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/3418
摘要： Methods and apparatus are provided for intercell interference mitigation using modulation coding. During programming of a flash memory, a modulation encoding is performed that selects one or more levels for programming the flash memory such that a reduced number of cells in the flash memory are programmed with a value that violates one or more predefined criteria. During a reading of a flash memory, a modulation decoding is performed that assigns one or more levels to cells in the flash memory such that a reduced number of cells in the flash memory are read with a value that violates one or more predefined criteria. The predefined criteria can be based, for example, on one or more of an amount of disturbance caused by the programmed cell; a voltage shift of a programmed cell: a voltage stored by a programmed cell; an amount of change in current through a programmed cell; and an amount of current through a programmed cell.
摘要翻译：提供了使用调制编码的小区间干扰减轻的方法和装置。在闪速存储器的编程期间，执行调制编码，其选择用于编程闪速存储器的一个或多个级别，使得闪存中的减少数量的单元被编程为具有违反一个或多个预定标准的值。在读取闪速存储器期间，执行调制解码，其将一个或多个级别分配给闪速存储器中的单元，使得闪存中的小数量的单元以违反一个或多个预定准则的值被读取。预定义的标准可以例如基于由编程的小区引起的干扰量的一个或多个; 编程单元的电压偏移：由编程单元存储的电压; 通过编程单元的电流变化量; 以及通过编程单元的电流量。

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