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1. 发明申请

US20120187484A1 LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：横向双重扩散金属氧化物半导体器件
公开(公告)号：US20120187484A1
公开(公告)日：2012-07-26
申请号：US13216963
申请日：2011-08-24
申请人： Cheol-Ho CHO , Choul-Joo Ko
发明人： Cheol-Ho CHO , Choul-Joo Ko
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L29/0847 , H01L29/086 , H01L29/0873 , H01L29/1083 , H01L29/1087 , H01L29/42368 , H01L29/7835
摘要： A lateral double diffused metal oxide semiconductor (LDMOS) device includes a first buried layer having a second conduction type formed in an epitaxial layer having a first conduction type, a first high-voltage well having the second conduction type formed above one region of the first buried layer, a first drain diffusion region having the first conduction type formed above another region of the first buried layer, a second drain diffusion region having the second conduction type formed in a partial region of the first drain diffusion region, the second drain diffusion region including a gate pattern and a drain region, and a first body having the first conduction type including a source region and having a surface in contact with the second drain diffusion region.
摘要翻译：横向双扩散金属氧化物半导体（LDMOS）器件包括具有形成在具有第一导电类型的外延层中的第二导电类型的第一掩埋层，具有第二导电类型的第一高电压阱形成在第一第一漏极扩散区，形成在第一掩埋层的另一区域上方的具有第一导电类型的第一漏极扩散区域，形成在第一漏极扩散区域的部分区域中的具有第二导电类型的第二漏极扩散区域，第二漏极扩散区域包括栅极图案和漏极区域，以及具有包括源极区域并且具有与第二漏极扩散区域接触的表面的第一导电类型的第一主体。

2. 发明授权

US08089124B2 Lateral DMOS device and method for fabricating the same 有权
标题翻译：侧面DMOS装置及其制造方法
公开(公告)号：US08089124B2
公开(公告)日：2012-01-03
申请号：US12141961
申请日：2008-06-19
申请人： Choul-Joo Ko
发明人： Choul-Joo Ko
IPC分类号： H01L29/66 , H01L21/336
CPC分类号： H01L29/0878 , H01L29/0847 , H01L29/086 , H01L29/1079 , H01L29/1083 , H01L29/42368 , H01L29/66659 , H01L29/66689 , H01L29/7816 , H01L29/7835
摘要： An LDMOS device and a method for fabricating the same that may include a first conductivity-type semiconductor substrate having an active area and a field area; a second conductivity-type deep well formed on the first conductivity-type semiconductor substrate; a second conductivity-type adjusting layer located in the second conductivity-type deep well; a first conductivity-type body formed in the second conductivity-type deep well; an insulating layer formed on the first conductivity-type semiconductor substrate in the active area and the field area; a gate area formed on the first conductivity-type semiconductor substrate in the active area; a second conductivity-type source area formed in the first conductivity-type body; a second conductivity-type drain area formed in the second conductivity-type deep well. Accordingly, such an LDMOS device has a high breakdown voltage without an increase in on-resistance.
摘要翻译：一种LDMOS器件及其制造方法，其可以包括具有有源区和场区的第一导电型半导体衬底; 在第一导电型半导体衬底上形成的第二导电型深阱; 位于第二导电型深井中的第二导电型调节层; 形成在第二导电型深井中的第一导电型体; 形成在所述有源区域和所述场区域中的所述第一导电型半导体基板上的绝缘层; 形成在所述有源区域中的所述第一导电型半导体基板上的栅极区域; 形成在第一导电型体中的第二导电型源区; 在第二导电型深井中形成的第二导电型漏极区。因此，这种LDMOS器件具有高的击穿电压而不增加导通电阻。

3. 发明授权

US07944002B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07944002B2
公开(公告)日：2011-05-17
申请号：US12248141
申请日：2008-10-09
申请人： Choul-Joo Ko
发明人： Choul-Joo Ko
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L29/41766 , H01L29/42368 , H01L29/66689 , H01L29/66696
摘要： Embodiments relate to a semiconductor device having a minimized on-resistance. According to embodiments, a semiconductor device may include at least one of the following: a first conductive type well formed on and/or over a semiconductor substrate, a second conductive type body region formed within the first conductive type well a first conductive type source region formed on and/or over the surface of the body region, a first conductive type drain region formed on and/or over the surface of the first conductive type well. Further, according to embodiments, a semiconductor device may include a field insulation layer positioned between the first conductive type source region and the first conductive type drain region and a gate electrode formed on and/or over the field insulation layer. The source region may be formed at a lower position than the drain region.
摘要翻译：实施例涉及具有最小导通电阻的半导体器件。根据实施例，半导体器件可以包括以下中的至少一个：在半导体衬底上和/或之上形成的第一导电类型阱，形成在第一导电类型阱内的第二导电类型体区域，第一导电类型源极区域形成在主体区域的表面上和/或上方，形成在第一导电类型孔的表面上和/或上方的第一导电类型漏极区域。此外，根据实施例，半导体器件可以包括位于第一导电型源极区域和第一导电型漏极区域之间的场绝缘层以及形成在场绝缘层上和/或上部的栅电极。源极区域可以形成在比漏极区域更低的位置处。

4. 发明申请

US20100163990A1 Lateral Double Diffused Metal Oxide Semiconductor Device 审中-公开
标题翻译：横向双扩散金属氧化物半导体器件
公开(公告)号：US20100163990A1
公开(公告)日：2010-07-01
申请号：US12646218
申请日：2009-12-23
申请人： Choul Joo KO
发明人： Choul Joo KO
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/0619 , H01L29/0878 , H01L29/42368
摘要： Disclosed is a lateral double diffused metal oxide semiconductor (LDMOS) device and methods of making the same. The LDMOS device may include a semiconductor substrate comprising a buried region and a first well region, a gate on the semiconductor substrate, a body region in the first well region and a source region in the body region on one side of the gate, a drift region and a drain region in the drift region on an opposite side of the gate relative to the body region, a second well region, a first deep sink region and a third well region in the first well region, and a second deep sink region in the first well region.
摘要翻译：公开了一种横向双扩散金属氧化物半导体（LDMOS）器件及其制造方法。 LDMOS器件可以包括半导体衬底，其包括掩埋区域和第一阱区域，半导体衬底上的栅极，第一阱区域中的主体区域和栅极一侧的体区域中的源极区域，漂移区域和位于栅极相对于体区相对侧的漂移区域中的漏极区域，第一阱区域中的第二阱区域，第一深阱区域和第三阱区域以及第一阱区域中的第二深阱区域第一个井区。

5. 发明授权

US07601600B2 Power semiconductor device and method for manufacturing the same 失效
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US07601600B2
公开(公告)日：2009-10-13
申请号：US11590373
申请日：2006-10-30
申请人： Choul Joo Ko , Nam Joo Kim
发明人： Choul Joo Ko , Nam Joo Kim
IPC分类号： H01L29/76
CPC分类号： H01L27/0629 , H01L29/1083 , H01L29/404 , H01L29/42368 , H01L29/7831 , H01L29/7835
摘要： Disclosed are a power semiconductor device and a method for manufacturing the same. The power semiconductor device has a PIP capacitor and an LDMOS transistor, the LDMOS transistor having second and third gate electrodes separate from a first gate electrode, which may be formed in the process of forming the upper electrode of the PIP capacitor, so it is possible to realize an LDMOS having a higher breakdown voltage and lower Ron and Rsp without additional processing. A drain voltage, which may be different from a voltage applied to the first gate electrode, may be applied to the third gate electrode, so it is possible to realize an LDMOS having a high breakdown voltage and low Ron and Rsp.
摘要翻译：公开了功率半导体器件及其制造方法。功率半导体器件具有PIP电容器和LDMOS晶体管，LDMOS晶体管具有与形成PIP电容器的上电极的过程中形成的第二和第三栅电极分离的第一和第三栅电极，因此可能实现具有更高击穿电压的LDMOS和较低的Ron和Rsp，而无需额外的处理。可以将不同于施加到第一栅电极的电压的漏极电压施加到第三栅电极，因此可以实现具有高击穿电压和低Ron和Rsp的LDMOS。

6. 发明授权

US07563667B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07563667B2
公开(公告)日：2009-07-21
申请号：US12002241
申请日：2007-12-13
申请人： Choul Joo Ko , Yong Jun Lee
发明人： Choul Joo Ko , Yong Jun Lee
IPC分类号： H01L21/8234 , H01L21/8244 , H01L21/8242 , H01L21/336
CPC分类号： H01L27/0629 , H01L28/40
摘要： In a method for forming a semiconductor device, a device isolation layer is formed in a capacitor region of a silicon substrate, and a bottom electrode and a dielectric layer are formed on the device isolation layer. Insulation sidewalls are formed on both sides of the bottom electrode. A top electrode is formed on the dielectric layer, and simultaneously a gate electrode is formed in a transistor region of the silicon substrate. Source/drain impurity regions are formed in the silicon substrate at both sides of the gate electrode.
摘要翻译：在形成半导体器件的方法中，在硅衬底的电容器区域中形成器件隔离层，并且在器件隔离层上形成底电极和电介质层。绝缘侧壁形成在底部电极的两侧。在电介质层上形成顶部电极，同时在硅衬底的晶体管区域形成栅电极。源极/漏极杂质区域形成在栅极电极两侧的硅衬底中。

7. 发明申请

US20080176370A1 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20080176370A1
公开(公告)日：2008-07-24
申请号：US12002241
申请日：2007-12-13
申请人： Choul Joo Ko , Yong Jun Lee
发明人： Choul Joo Ko , Yong Jun Lee
IPC分类号： H01L21/76
CPC分类号： H01L27/0629 , H01L28/40
摘要： In a method for forming a semiconductor device, a device isolation layer is formed in a capacitor region of a silicon substrate, and a bottom electrode and a dielectric layer are formed on the device isolation layer. Insulation sidewalls are formed on both sides of the bottom electrode. A top electrode is formed on the dielectric layer, and simultaneously a gate electrode is formed in a transistor region of the silicon substrate. Source/drain impurity regions are formed in the silicon substrate at both sides of the gate electrode.
摘要翻译：在形成半导体器件的方法中，在硅衬底的电容器区域中形成器件隔离层，在器件隔离层上形成底部电极和电介质层。绝缘侧壁形成在底部电极的两侧。在电介质层上形成顶部电极，同时在硅衬底的晶体管区域中形成栅电极。源极/漏极杂质区域形成在栅极电极两侧的硅衬底中。

8. 发明申请

US20130082327A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20130082327A1
公开(公告)日：2013-04-04
申请号：US13252284
申请日：2011-10-04
申请人： Cheol Ho CHO , Choul Joo Ko
发明人： Cheol Ho CHO , Choul Joo Ko
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L29/1083 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device including a first conductive epitaxial layer, a second conductive type first well provided in the first conductive epitaxial layer, a first conductive body provided in the first conductive epitaxial layer, a second conductive type drain extension region provided in the first conductive epitaxial layer and interposed between the first conductive body and the second conductive type first well, a second conductive type second well provided in the second conductive type first well, and a gate provided in the first conductive epitaxial layer.
摘要翻译：一种半导体器件，包括第一导电外延层，设置在第一导电外延层中的第二导电类型第一阱，设置在第一导电外延层中的第一导电体，设置在第一导电外延层中的第二导电型漏极延伸区并且介于所述第一导电体和所述第二导电型第一阱之间，设置在所述第二导电型第一阱中的第二导电型第二阱以及设置在所述第一导电外延层中的栅极。

9. 发明授权

US08227871B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08227871B2
公开(公告)日：2012-07-24
申请号：US12631308
申请日：2009-12-04
申请人： Choul Joo Ko
发明人： Choul Joo Ko
IPC分类号： H01L27/092 , H01L29/76
CPC分类号： H01L29/7816 , H01L29/0619 , H01L29/0878 , H01L29/42368 , H01L29/66681 , H01L29/7817 , H01L29/7818
摘要： A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device includes a substrate having a first conductor-type, a buried layer of a second conductor-type on the substrate, a drain, and a first guard-ring on one side of the drain, a second guard-ring on one side of the first guard-ring, and a third guard-ring on one side of the second guard-ring.
摘要翻译：公开了一种半导体器件及其制造方法。半导体器件包括：衬底，其具有第一导体类型，衬底上第二导体类型的掩埋层，漏极和漏极一侧的第一保护环，一侧上的第二保护环并且在第二保护环的一侧具有第三保护环。

10. 发明授权

US07687363B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07687363B2
公开(公告)日：2010-03-30
申请号：US11639928
申请日：2006-12-15
申请人： Choul Joo Ko
发明人： Choul Joo Ko
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L29/665 , H01L29/6659 , H01L29/7836
摘要： Disclosed is a method of manufacturing a semiconductor device, which includes the steps of: forming a high-voltage well region (e.g., by implanting impurity ions into a semiconductor substrate and then annealing); forming an isolation layer on the semiconductor substrate; implanting impurity ions into the high-voltage well region, thereby forming a low-voltage well region within the high-voltage well region; forming a gate electrode on the semiconductor substrate; and implanting impurity ions using the gate electrode as a mask, thereby forming source/drain regions within the low-voltage well region.
摘要翻译：公开了一种制造半导体器件的方法，其包括以下步骤：形成高电压阱区（例如，通过将杂质离子注入到半导体衬底中然后退火）; 在所述半导体衬底上形成隔离层; 将杂质离子注入高电压阱区，从而在高电压阱区内形成低电压阱区; 在半导体衬底上形成栅电极; 以及使用栅极电极作为掩模注入杂质离子，从而在低电压阱区域内形成源极/漏极区域。

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