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1. 发明申请

US20140040681A1 DEVICE BASED WEAR LEVELING 有权
标题翻译：基于设备的磨损水平
公开(公告)号：US20140040681A1
公开(公告)日：2014-02-06
申请号：US13565650
申请日：2012-08-02
申请人： Jonathan Wolfman , Dana Lee , Jonathan Hsu
发明人： Jonathan Wolfman , Dana Lee , Jonathan Hsu
IPC分类号： G06F12/02 , G06F11/00
CPC分类号： G06F11/1048 , G01R31/3171 , G06F11/07 , G06F11/076 , G06F11/30 , G06F12/02 , G06F12/0246 , G06F12/06 , G06F12/16 , G06F2212/7211 , G11C16/04 , G11C16/34 , G11C16/349 , G11C2029/0409 , H04L1/0061
摘要： A system for improving the management and usage of blocks based on intrinsic endurance may be used to improve memory usage for flash memory, such as a memory card. The overall card endurance may be extended by cycling blocks with higher intrinsic endurance over the lowest endurance target of the worst block. This may be accomplished by managing blocks with different intrinsic endurance values internally or by partitioning the blocks with different intrinsic endurance values externally for different usage.
摘要翻译：可以使用用于改善基于固有耐力的块的管理和使用的系统来改善诸如存储卡的闪存的存储器使用。整体卡耐力可以通过在最差块的最低耐力目标下具有较高内在耐力的循环块来延长。这可以通过内部管理具有不同内在耐力值的块来实现，或者通过外部对不同的内在耐力值进行分区，以实现不同的使用。

2. 发明申请

US20140029357A1 Non-Volatile Memory and Method with Peak Current Control 有权
标题翻译：非易失性存储器和峰值电流控制方法
公开(公告)号：US20140029357A1
公开(公告)日：2014-01-30
申请号：US13559377
申请日：2012-07-26
申请人： Dana Lee , Yi-Chieh Chen , Farookh Moogat
发明人： Dana Lee , Yi-Chieh Chen , Farookh Moogat
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C16/30
摘要： A non-volatile memory with multiple memory dice manages simultaneous operations so as to not exceed a system power capacity. A load signal bus is pulled up with a strength proportional to the system power capacity. Each die has a driver to pull down the bus by an amount corresponding to its degree of power need as estimated by a state machine of the die. The bus therefore provides a load signal that serves as arbitration between the system power capacity and the cumulative loads of the individual dice. The load signal is therefore at a high state when the system power capacity is not exceeded; otherwise it is at a low state. When a die wishes to perform an operation and requests a certain amount of power, it drives the bus accordingly and its state machine either proceeds with the operation or not, depending on the load signal.
摘要翻译：具有多个存储器骰子的非易失性存储器管理同时操作，以便不超过系统功率容量。负载信号总线以与系统功率容量成比例的强度被拉高。每个模具具有一个驱动器，用于将总线的数量下降一定量，与模具状态机所估计的功率需求量相对应。因此，总线提供负载信号，用作系统功率容量和单个骰子的累积负载之间的仲裁。因此，当不超过系统功率容量时，负载信号处于高电平状态; 否则处于低状态。当模具希望执行操作并请求一定量的电力时，它相应地驱动总线，并且其状态机根据负载信号进行操作。

3. 发明申请

US20130346805A1 FLASH MEMORY WITH TARGETED READ SCRUB ALGORITHM 有权
标题翻译：具有指定读取SCRUB算法的闪存
公开(公告)号：US20130346805A1
公开(公告)日：2013-12-26
申请号：US13529522
申请日：2012-06-21
申请人： Steven T. Sprouse , Alexandra Bauche , Yichao Huang , Jian Chen , Jianmin Huang , Dana Lee
发明人： Steven T. Sprouse , Alexandra Bauche , Yichao Huang , Jian Chen , Jianmin Huang , Dana Lee
IPC分类号： G06F11/28
CPC分类号： G11C16/3418 , G11B20/18 , G11B20/1883 , G11C16/3427 , G11C16/3431
摘要： A method and system have been described for counteracting and correcting for read disturb effects in blocks of flash memory. The method may include the step of a controller of the memory system performing a read scrub scan on only a portion of one targeted word line in a block at desired intervals. The controller may calculate whether a read scrub scan is necessary based on a probabilistic determination that is calculated in response to each received host read command. The controller may then place a block associated with the targeted word line into a refresh queue if a number of errors are detected in the targeted word line that meets or exceeds a predetermined threshold. The block refresh process may include copying the data from the block into a new block during a background operation.
摘要翻译：已经描述了用于抵消和校正闪速存储器块中的读取干扰效应的方法和系统。该方法可以包括存储器系统的控制器的步骤，其以期望的间隔仅在块中的一个目标字线的一部分上执行读取擦除扫描。控制器可以基于响应于每个接收的主机读取命令而计算的概率确定来计算是否需要读取擦除扫描。然后，如果在满足或超过预定阈值的目标字线中检测到多个错误，则控制器然后可以将与目标字线相关联的块放置到刷新队列中。块刷新过程可以包括在后台操作期间将数据从块复制到新块中。

4. 发明申请

US20130336059A1 BLOCK LEVEL GRADING FOR RELIABILITY AND YIELD IMPROVEMENT 有权
标题翻译：阻塞等级可靠性和成本提升
公开(公告)号：US20130336059A1
公开(公告)日：2013-12-19
申请号：US13527199
申请日：2012-06-19
申请人： Dana Lee , Jianmin Huang , Mrinal Kochar , Ashish Ghai
发明人： Dana Lee , Jianmin Huang , Mrinal Kochar , Ashish Ghai
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/349 , G11C29/56008 , G11C29/82 , G11C2029/4402
摘要： A system for grading blocks may be used to improve memory usage. Blocks of memory, such as on a flash card, may be graded on a sliding scale that may identify a level of “goodness” or a level of “badness” for each block rather than a binary good or bad identification. This grading system may utilize at least three tiers of grades which may improve efficiency by better utilizing each block based on the individual grades for each block. The block leveling grading system may be used for optimizing the competing needs of minimizing yield loss while minimizing testing defect escapes.
摘要翻译：可以使用用于分级块的系统来改善存储器使用。诸如闪存卡之类的存储器块可以在可以标识每个块的“良好”级别或“坏”级别的滑动标度上分级，而不是二进制好或坏标识。该分级系统可以利用至少三个等级的等级，其可以通过基于每个块的各个等级更好地利用每个块来提高效率。块调平分级系统可用于优化最小化产量损失的竞争需求，同时最小化测试缺陷逃逸。

5. 发明授权

US08546214B2 P-type control gate in non-volatile storage and methods for forming same 有权
标题翻译：非易失性存储中的P型控制门及其形成方法
公开(公告)号：US08546214B2
公开(公告)日：2013-10-01
申请号：US12887328
申请日：2010-09-21
申请人： Takashi Whitney Orimoto , Atsushi Suyama , Ming Tian , Henry Chin , Henry Chien , Vinod Robert Purayath , Dana Lee
发明人： Takashi Whitney Orimoto , Atsushi Suyama , Ming Tian , Henry Chin , Henry Chien , Vinod Robert Purayath , Dana Lee
IPC分类号： H01L21/8242
CPC分类号： H01L21/28291 , H01L21/28273 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/788
摘要： Non-voltage storage and techniques for fabricating non-volatile storage are disclosed. In some embodiments, at least a portion of the control gates of non-volatile storage elements are formed from p-type polysilicon. In one embodiment, a lower portion of the control gate is p-type polysilicon. The upper portion of the control gate could be p-type polysilicon, n-type polysilicon, metal, metal nitride, etc. P-type polysilicon in the control gate may not deplete even at high Vpgm. Therefore, a number of problems that could occur if the control gate depleted are mitigated. For example, a memory cell having a control gate that is at least partially p-type polysilicon might be programmed with a lower Vpgm than a memory cell formed from n-type polysilicon.
摘要翻译：公开了非电压存储和用于制造非易失性存储器的技术。在一些实施例中，非易失性存储元件的控制栅极的至少一部分由p型多晶硅形成。在一个实施例中，控制栅极的下部是p型多晶硅。控制栅极的上部可以是p型多晶硅，n型多晶硅，金属，金属氮化物等。即使在高Vpgm下，控制栅中的P型多晶硅也可能不会消耗。因此，如果控制门耗尽，可能会发生的一些问题得到缓解。例如，具有至少部分p型多晶硅的控制栅极的存储单元可以用比由n型多晶硅形成的存储单元低的Vpgm来编程。

6. 发明授权

US08462547B2 Offset non-volatile storage 有权
公开(公告)号：US08462547B2
公开(公告)日：2013-06-11
申请号：US12822568
申请日：2010-06-24
申请人： Jeffrey W. Lutze , Dana Lee
发明人： Jeffrey W. Lutze , Dana Lee
IPC分类号： G11C11/34
CPC分类号： H01L27/1158 , H01L27/11524 , H01L27/11553 , H01L27/11568 , H01L27/1157
摘要： A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce interference from neighbor non-volatile storage elements. A method of manufacture is also described for fabricating the offset non-volatile storage elements.

7. 发明授权

US08406053B1 On chip dynamic read for non-volatile storage 有权
标题翻译：用于非易失性存储的片上动态读取
公开(公告)号：US08406053B1
公开(公告)日：2013-03-26
申请号：US13239194
申请日：2011-09-21
申请人： Deepanshu Dutta , Dana Lee , Jeffrey Lutze
发明人： Deepanshu Dutta , Dana Lee , Jeffrey Lutze
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/04 , G11C11/5642 , G11C16/26 , G11C16/3418 , G11C16/3495 , G11C2211/5644
摘要： Dynamically determining read levels on chip (e.g., memory die) is disclosed herein. One method comprises reading a group of non-volatile storage elements on a memory die at a first set of read levels. Results of the two most recent of the read levels are stored on the memory die. A count of how many of the non-volatile storage elements in the group showed a different result between the reads for the two most recent read levels is determined. The determining is performed on the memory die using the results stored on the memory die. A dynamic read level is determined for distinguishing between a first pair of adjacent data states of the plurality of data states based on the read level when the count reaches a pre-determined criterion. Note that the read level may be dynamically determined on the memory die.
摘要翻译：本文公开了动态地确定芯片上的读取电平（例如，存储器管芯）。一种方法包括以第一组读取级别在存储器管芯上读取一组非易失性存储元件。两个最新的读取电平的结果存储在存储器管芯上。确定组中有多少非易失性存储元件在两个最新读取级别的读取之间显示不同的结果。使用存储在存储器管芯上的结果在存储器管芯上进行确定。当计数达到预定标准时，基于读取级别来确定动态读取级别以区分多个数据状态的第一对相邻数据状态。注意，读取电平可以在存储器管芯上动态地确定。

8. 发明授权

US08321727B2 System and method responsive to a rate of change of a performance parameter of a memory 有权
标题翻译：响应于存储器的性能参数的变化率的系统和方法
公开(公告)号：US08321727B2
公开(公告)日：2012-11-27
申请号：US12494222
申请日：2009-06-29
申请人： Manuel Antonio D'Abreu , Stephen Skala , Dana Lee
发明人： Manuel Antonio D'Abreu , Stephen Skala , Dana Lee
IPC分类号： G11C29/00
CPC分类号： G11C16/349 , G06F11/1068 , G11C29/76 , G11C2029/0411 , G11C2029/4402
摘要： Systems and methods are disclosed that are responsive to a rate of change of a performance parameter of a memory. In a particular embodiment, a rate of change of a performance parameter of a non-volatile memory is determined. The rate of change is compared to a threshold, and an action is performed in response to determining that the rate of change satisfies the threshold.
摘要翻译：公开了响应于存储器的性能参数的变化率的系统和方法。在特定实施例中，确定非易失性存储器的性能参数的变化率。将变化率与阈值进行比较，并且响应于确定变化率满足阈值来执行动作。

9. 发明授权

US08094492B2 Reducing the impact of interference during programming 有权
标题翻译：减少编程过程中的干扰影响
公开(公告)号：US08094492B2
公开(公告)日：2012-01-10
申请号：US12962902
申请日：2010-12-08
申请人： Dana Lee , Emilio Yero
发明人： Dana Lee , Emilio Yero
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C2211/5621
摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.
摘要翻译：提出了一种用于编程非易失性存储器的系统，其减少了来自邻居增强的干扰的影响。存储单元分为两个或更多个组。在一个示例中，存储器单元被分成奇数和偶数存储器单元; 然而，也可以使用其他组。在第一触发之前，第一组存储器单元与第二组存储器单元一起编程。在第一触发之后和在第二触发之前，第一组存储器单元与第二组存储器单元分开编程。在第二触发之后，第一组存储器单元与第二组存储器单元一起被编程。在两个触发之前和之后，第一组存储器单元与第二组存储器单元一起被验证。

10. 发明申请

US20110075477A1 REDUCING THE IMPACT OF INTERFERENCE DURING PROGRAMMING 有权
标题翻译：减少编程过程中干扰的影响
公开(公告)号：US20110075477A1
公开(公告)日：2011-03-31
申请号：US12962902
申请日：2010-12-08
申请人： Dana Lee , Emilio Yero
发明人： Dana Lee , Emilio Yero
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C2211/5621
摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.
摘要翻译：提出了一种用于编程非易失性存储器的系统，其减少了来自邻居增强的干扰的影响。存储单元分为两个或更多个组。在一个示例中，存储器单元被分成奇数和偶数存储器单元; 然而，也可以使用其他组。在第一触发之前，第一组存储器单元与第二组存储器单元一起编程。在第一触发之后和在第二触发之前，第一组存储器单元与第二组存储器单元分开编程。在第二触发之后，第一组存储器单元与第二组存储器单元一起被编程。在两个触发之前和之后，第一组存储器单元与第二组存储器单元一起被验证。

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