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1. 发明授权

US08190861B2 Micro-sequence based security model 有权
标题翻译：基于微序列的安全模型
公开(公告)号：US08190861B2
公开(公告)日：2012-05-29
申请号：US11677367
申请日：2007-02-21
申请人： Gerard Chauvel , Gilbert Cabillic , Jean-Philippe Lesot , Dominique D'Inverno , Eric Badi , Serge Lasserre
发明人： Gerard Chauvel , Gilbert Cabillic , Jean-Philippe Lesot , Dominique D'Inverno , Eric Badi , Serge Lasserre
IPC分类号： G06F9/00
CPC分类号： G06F9/4812
摘要： A method and system for implementing a micro-sequence based security model in a processor. More particularly, micro-sequences and JSM hardware resources are employed to construct a security model invisible to applications, and when memory constraints are in place, extend a complex security model in JSM code by implementing a micro-sequence security trigger. The method includes micro-sequence based security policy that determines whether an instruction accesses a privileged resource associated with a processor and when not already in privilege mode and not executing a micro-sequence, the micro-sequence based security policy is applied to the instruction to control access to the privileged resource according to the security policy.
摘要翻译：一种用于在处理器中实现基于微序列的安全模型的方法和系统。更具体地，使用微序列和JSM硬件资源来构建对应用不可见的安全模型，并且当存储器约束到位时，通过实现微序列安全触发来扩展JSM代码中的复杂安全模型。该方法包括基于微序列的安全策略，其确定指令是否访问与处理器相关联的特权资源，以及当尚未处于特权模式且不执行微序列时，将基于微序列的安全策略应用于根据安全策略控制对特权资源的访问。

2. 发明授权

US06742104B2 Master/slave processing system with shared translation lookaside buffer 有权
标题翻译：具有共享翻译后备缓冲器的主/从处理系统
公开(公告)号：US06742104B2
公开(公告)日：2004-05-25
申请号：US09932607
申请日：2001-08-17
申请人： Gerard Chauvel , Dominique D'Inverno , Serge Lasserre
发明人： Gerard Chauvel , Dominique D'Inverno , Serge Lasserre
IPC分类号： G06F1208
CPC分类号： G06F9/30043 , G06F12/1027 , G06F12/1081 , G06F2212/681 , G06F2212/684 , Y02D10/13
摘要： A multiprocessor system (20, 102, 110) uses multiple operating systems or a single operating system uses &mgr;TLBs (36) and a shared TLB subsystem (48) to provide efficient and flexible translation of virtual addresses to physical addresses. Upon misses in the &mgr;TLB and shared TLB, access to a translation table in external memory (54) can be made using either a hardware mechanism (100) or a software function. The translation can be flexibly based on a number of criteria, such as a resource identifier and a task identifier. Slave processors, such as coprocessors (34) and DMA processors (24) can access the shared TLB 48 without master processor interaction for more efficient operation.
摘要翻译：多处理器系统（20,102,110）使用多个操作系统，或者单个操作系统使用muTLB（36）和共享TLB子系统（48）来提供虚拟地址到物理地址的有效和灵活的转换。在muTLB和共享TLB中缺失时，可以使用硬件机制（100）或软件功能来访问外部存储器（54）中的翻译表。可以基于诸如资源标识符和任务标识符的多个标准来灵活地进行翻译。诸如协处理器（34）和DMA处理器（24）之类的从属处理器可以在没有主处理器交互的情况下访问共享的TLB 48，以便更有效的操作。

3. 发明授权

US06742103B2 Processing system with shared translation lookaside buffer 有权
标题翻译：具有共享翻译后备缓冲器的处理系统
公开(公告)号：US06742103B2
公开(公告)日：2004-05-25
申请号：US09932362
申请日：2001-08-17
申请人： Gerard Chauvel , Dominique D'Inverno , Serge Lasserre
发明人： Gerard Chauvel , Dominique D'Inverno , Serge Lasserre
IPC分类号： G06F1208
CPC分类号： G06F12/1036 , G06F1/206 , G06F1/3203 , G06F1/329 , G06F9/30043 , G06F9/5011 , G06F12/1081 , G06F2212/681 , Y02D10/24
摘要： A multiprocessor system (20, 102, 110) uses multiple operating systems or a single operating system uses &mgr;TLBs (36) and a shared TLB subsystem (48) to provide efficient and flexible translation of virtual addresses to physical addresses. Upon misses in the &mgr;TLB and shared TLB, access to a translation table in external memory (54) can be made using either a hardware mechanism (100) or a software function. The translation can be flexibly based on a number of criteria, such as a resource identifier and a task identifier. Slave processors, such as coprocessors (34) and DMA processors (24) can access the shared TLB 48 without master processor interaction for more efficient operation.
摘要翻译：多处理器系统（20,102,110）使用多个操作系统，或者单个操作系统使用muTLB（36）和共享TLB子系统（48）来提供虚拟地址到物理地址的有效和灵活的转换。在muTLB和共享TLB中缺失时，可以使用硬件机制（100）或软件功能来访问外部存储器（54）中的翻译表。可以基于诸如资源标识符和任务标识符的多个标准来灵活地进行翻译。诸如协处理器（34）和DMA处理器（24）之类的从属处理器可以在没有主处理器交互的情况下访问共享的TLB 48，以便更有效的操作。

4. 发明授权

US08429383B2 Multi-processor computing system having a JAVA stack machine and a RISC-based processor 有权
标题翻译：具有JAVA堆栈机和基于RISC处理器的多处理器计算系统
公开(公告)号：US08429383B2
公开(公告)日：2013-04-23
申请号：US10631939
申请日：2003-07-31
申请人： Gerard Chauvel , Serge Lasserre , Maija Kuusela , Dominique D'Inverno
发明人： Gerard Chauvel , Serge Lasserre , Maija Kuusela , Dominique D'Inverno
IPC分类号： G06F15/76
CPC分类号： G06F12/0253 , G06F9/30101 , G06F9/30174 , G06F9/3879 , G06F12/0804 , G06F12/0875 , G06F12/0891 , G06F12/1036 , G06F12/126 , G06F2212/502 , G06F2212/681
摘要： A system comprises a first processor, a second processor coupled to the first processor, memory coupled to, and shared by, the first and second processors, and a synchronization unit coupled to the first and second processors. The second processor preferably comprises stack storage that resides in the core of the second processor. Further, the second processor executes stack-based instructions while the first processor executes one or more tasks including, for example, managing the memory via an operating system that executes only on the first processor. Associated methods are also disclosed.
摘要翻译：系统包括第一处理器，耦合到第一处理器的第二处理器，耦合到第一和第二处理器并由其共享的存储器，以及耦合到第一和第二处理器的同步单元。第二处理器优选地包括位于第二处理器的核心中的堆栈存储器。此外，第二处理器执行基于堆栈的指令，而第一处理器执行一个或多个任务，包括例如经由只在第一处理器上执行的操作系统来管理存储器。还公开了相关方法。

5. 发明授权

US07565385B2 Embedded garbage collection 有权
标题翻译：嵌入式垃圾收集
公开(公告)号：US07565385B2
公开(公告)日：2009-07-21
申请号：US10831387
申请日：2004-04-22
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
IPC分类号： G06F17/00
CPC分类号： G06F12/0269 , Y02D10/13 , Y10S707/99957
摘要： An electronic system comprises a processor, memory coupled to the processor, and an application programming interface that causes an embedded garbage collection object to be active. The memory stores one or more objects that selectively have references from root objects. The embedded garbage collection object preferably uses control data to cause objects to be removed from said memory, the removed objects comprise those objects that were created while an embedded garbage collection object was active and that do not have references from root objects.
摘要翻译：电子系统包括处理器，耦合到处理器的存储器以及使嵌入式垃圾回收对象活动的应用编程接口。存储器存储一个或多个选择性地具有来自根对象的引用的对象。嵌入式垃圾回收对象优选地使用控制数据来使对象从所述存储器中移除，所移除的对象包括当嵌入式垃圾回收对象是活动的并且没有来自根对象的引用时创建的对象。

6. 发明授权

US07434021B2 Memory allocation in a multi-processor system 有权
标题翻译：多处理器系统中的内存分配
公开(公告)号：US07434021B2
公开(公告)日：2008-10-07
申请号：US10831388
申请日：2004-04-22
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F9/5016 , Y02D10/22
摘要： A process and associated system comprise pre-allocating a portion of memory in a first processor based upon a control input and determining in a second processor if the portion of the pre-allocated memory can satisfy a memory allocation request. Further, if a portion of pre-allocated memory can satisfy a memory allocation request, the technique includes assigning the pre-allocated portion of memory to the allocation request. However, if a portion of pre-allocated memory cannot satisfy a memory allocation request, the technique includes allocating a portion of memory in the first processor to the allocation request.
摘要翻译：过程和相关系统包括基于控制输入在第一处理器中预分配存储器的一部分，并且在第二处理器中确定预分配存储器的部分是否可以满足存储器分配请求。此外，如果预先分配的存储器的一部分可以满足存储器分配请求，则该技术包括将存储器的预分配部分分配给分配请求。然而，如果预分配存储器的一部分不能满足存储器分配请求，则该技术包括将第一处理器中的存储器的一部分分配给分配请求。

7. 发明授权

US07062304B2 Task based adaptative profiling and debugging 有权
标题翻译：基于任务的适应性剖析和调试
公开(公告)号：US07062304B2
公开(公告)日：2006-06-13
申请号：US09932136
申请日：2001-08-17
申请人： Gerard Chauvel , Dominique D'Inverno
发明人： Gerard Chauvel , Dominique D'Inverno
IPC分类号： G06F1/26 , G06F1/32 , G06F12/00
CPC分类号： G06F12/1027 , G06F1/206 , G06F1/3203 , G06F1/329 , G06F9/30043 , G06F9/4893 , G06F11/3013 , G06F11/3017 , G06F11/3062 , G06F11/3466 , G06F11/3636 , G06F12/0891 , G06F12/1081 , G06F2201/81 , G06F2201/88 , G06F2201/885 , G06F2212/1028 , Y02D10/13 , Y02D10/16 , Y02D10/24 , Y02D10/34
摘要： A multiprocessor system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power management software (38) in conjunction with profiles (36) for the various processing modules and the tasks to executed are used to build scenarios which meet predetermined power objectives, such as providing maximum operation within package thermal constraints or using minimum energy. Actual activities associated with the tasks are monitored during operation to ensure compatibility with the objectives. The allocation of tasks may be changed dynamically to accommodate changes in environmental conditions and changes in the task list. Temperatures may be computed at various points in the multiprocessor system by monitoring activity information associated with various subsystems. The activity measurements may be used to compute a current power dissipation distribution over the die. If necessary, the tasks in a scenario may be adjusted to reduce power dissipation. Further, activity counters may be selectively enabled for specific tasks in order to obtain more accurate profile information.
摘要翻译：多处理器系统（10）包括多个处理模块，例如MPU（12），DSP（14）和协处理器/ DMA通道（16）。电力管理软件（38）结合用于各种处理模块的简档（36）和执行的任务被用于构建满足预定功率目标的场景，例如在封装热约束内提供最大操作或使用最小能量。在操作过程中监视与任务相关的实际活动，以确保与目标的兼容性。可以动态地改变任务的分配，以适应环境条件的变化和任务列表的变化。可以通过监视与各种子系统相关联的活动信息来在多处理器系统中的各个点计算温度。活动测量可用于计算模具上的当前功耗分布。如果需要，可以调整场景中的任务以减少功耗。此外，可以为特定任务选择性地启用活动计数器，以便获得更准确的简档信息。

8. 发明授权

US06996683B2 Cache coherency in a multi-processor system 有权
标题翻译：多处理器系统中的高速缓存一致性
公开(公告)号：US06996683B2
公开(公告)日：2006-02-07
申请号：US10632229
申请日：2003-07-31
申请人： Gerard Chauvel , Serge Lasserre , Maija Kuusela , Dominique D'Inverno
发明人： Gerard Chauvel , Serge Lasserre , Maija Kuusela , Dominique D'Inverno
IPC分类号： G06F12/02
CPC分类号： G06F9/30134 , G06F9/30101 , G06F9/30174 , G06F9/3834 , G06F12/0253 , G06F12/0804 , G06F12/0891 , G06F12/126 , G06F2212/502
摘要： A system comprises a first processor having cache memory, a second processor having cache memory and a coherence buffer that can be enabled and disabled by the first processor. The system also comprises a memory subsystem coupled to the first and second processors. For a write transaction originating from the first processor, the first processor enables the second processor's coherence buffer, and information associated with the first processor's write transaction is stored in the second processor's coherence buffer to maintain data coherency between the first and second processors.
摘要翻译：一种系统包括具有高速缓冲存储器的第一处理器，具有高速缓冲存储器的第二处理器和可由第一处理器启用和禁用的相干缓冲器。该系统还包括耦合到第一和第二处理器的存储器子系统。对于来自第一处理器的写入事务，第一处理器启用第二处理器的相干缓冲器，并且与第一处理器的写入事务相关联的信息被存储在第二处理器的相干缓冲器中以维持第一和第二处理器之间的数据一致性。

9. 发明授权

US06681297B2 Software controlled cache configuration based on average miss rate 有权
标题翻译：基于平均失误率的软件控制缓存配置
公开(公告)号：US06681297B2
公开(公告)日：2004-01-20
申请号：US09932222
申请日：2001-08-17
申请人： Gerard Chauvel , Dominique D'Inverno , Serge Lasserre
发明人： Gerard Chauvel , Dominique D'Inverno , Serge Lasserre
IPC分类号： G06F1208
CPC分类号： G06F12/1027 , G06F1/206 , G06F1/3203 , G06F1/329 , G06F9/30047 , G06F11/3409 , G06F12/0802 , G06F12/0842 , G06F12/0879 , G06F12/0891 , G06F2201/81 , G06F2201/88 , G06F2201/885 , G06F2212/1028 , G06F2212/601 , G06F2212/681 , Y02D10/13 , Y02D10/16 , Y02D10/24 , Y02D10/34
摘要： A digital system is provided with a several processors (1302), a shared level two (L2) cache (1300) having several segments per entry with associated tags, and a level three (L3) physical memory. Each tag entry includes a task-ID qualifier field and a resource ID qualifier field. Data is loaded into various lines in the cache in response to cache access requests when a given cache access request misses. After loading data into the cache in response to a miss, a tag associated with the data line is set to a valid state. In addition to setting a tag to a valid state, qualifier values are stored in qualifier fields in the tag. Each qualifier value specifies a usage characteristic of data stored in an associated data line of the cache, such as a task ID. A miss counter (532) counts each miss and a monitoring task (1311) determines a miss rate for memory requests. If a selected miss rate threshold value is exceeded, the digital system is reconfigured in order to reduce the miss rate. The cache is reconfigured in response to an operation command (1314), such that each tag in the array of tags that contains a specified qualifier value is modified in accordance with the operation command. Other types of reconfiguration can be performed, such as remapping a selected program portion to operate in a different address range, locking a portion of the data entries within the cache, or defining addresses corresponding to a selected program task as uncacheable, for example.
摘要翻译：数字系统具有数个处理器（1302），共享二级（L2）高速缓存（1300），具有每个条目具有相关标签的几个段以及三级（L3）物理存储器。每个标签条目包括任务ID限定符字段和资源ID限定符字段。当给定的高速缓存访问请求未命中时，响应于高速缓存访问请求，将数据加载到高速缓存中的各行中。在将错误数据加载到缓存中之后，将与数据行相关联的标签设置为有效状态。除了将标签设置为有效状态之外，限定符值存储在标签中的限定符字段中。每个限定符值指定存储在高速缓存的关联数据行中的数据的使用特性，例如任务ID。未命中计数器（532）计算每个未命中，并且监视任务（1311）确定存储器请求的未命中率。如果超过选择的错失率阈值，则重新配置数字系统以减少错过率。响应于操作命令（1314）重新配置高速缓存，使得根据操作命令修改包含指定的限定符值的标签阵列中的每个标签。可以执行其他类型的重新配置，例如重新映射所选择的节目部分以在不同的地址范围内操作，将数据条目的一部分锁定在高速缓存内，或者将对应于所选择的节目任务的地址定义为不可缓存的。

10. 发明授权

US07496930B2 Accessing device driver memory in programming language representation 有权
标题翻译：以编程语言表示访问设备驱动程序内存
公开(公告)号：US07496930B2
公开(公告)日：2009-02-24
申请号：US10831575
申请日：2004-04-22
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
IPC分类号： G06F13/00
CPC分类号： G09G5/39 , G06F3/14 , G09G5/393
摘要： In some embodiments, a storage medium comprises application software that performs one or more operations and that directly manages a device. The application software comprises instructions that initialize an application data structure (e.g., an object or array) usable by the application software to manage the device and also comprises instructions that map the application data structure to a memory associated with the device without the use of a device driver. In other embodiments, a method comprises initializing an application data structure to manage a hardware device and mapping the application data structure to a memory associated with the hardware device without the use of a device driver. The application data structure may store a single dimensional data structure or a multi-dimensional data structure. In some embodiments, the device being managed by the application software may comprise a display and the application software may comprise Java code.
摘要翻译：在一些实施例中，存储介质包括执行一个或多个操作并直接管理设备的应用软件。应用软件包括初始化应用软件可用于管理设备的应用数据结构（例如，对象或阵列）的指令，还包括将应用数据结构映射到与设备相关联的存储器而不使用设备驱动。在其他实施例中，一种方法包括初始化应用数据结构以管理硬件设备，并将应用数据结构映射到与硬件设备相关联的存储器，而不使用设备驱动程序。应用数据结构可以存储单维数据结构或多维数据结构。在一些实施例中，由应用软件管理的设备可以包括显示器，并且应用软件可以包括Java代码。

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