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1. 发明授权

US08489860B1 Mobile electronic device having a host processor system capable of dynamically canging tasks performed by a coprocessor in the device 失效
标题翻译：移动电子设备具有能够动态地改变由设备中的协处理器执行的任务的主机处理器系统
公开(公告)号：US08489860B1
公开(公告)日：2013-07-16
申请号：US08995606
申请日：1997-12-22
申请人： Michael McMahon , Marion C. Lineberry , Matthew A. Woolsey , Gerard Chauvel
发明人： Michael McMahon , Marion C. Lineberry , Matthew A. Woolsey , Gerard Chauvel
IPC分类号： G06F9/30
CPC分类号： G06F9/3879 , G06F9/54 , G06F21/00
摘要： A wireless data platform comprises a plurality of processors. Channels of communication are set up between processors such that they may communicate information as tasks are performed. A dynamic cross compiler executed on one processor compiles code into native processing code for another processor. A dynamic cross linker links the compiled code for other processor. Native code may also be downloaded to the platform through use of a JAVA Bean (or other language type) which encapsulates the native code. The JAVA Bean can be encrypted and digitally signed for security purposes.
摘要翻译：无线数据平台包括多个处理器。在处理器之间设置通信通道，使得它们可以在执行任务时传送信息。在一个处理器上执行的动态交叉编译器将代码编译成另一个处理器的本机处理代码。动态交叉链接器链接其他处理器的编译代码。本地代码也可以通过使用封装本地代码的JAVA Bean（或其他语言类型）下载到平台。为了安全起见，JAVA Bean可以被加密和数字签名。

2. 发明授权

US07757067B2 Pre-decoding bytecode prefixes selectively incrementing stack machine program counter 有权
标题翻译：预解码字节码前缀选择性地递增堆栈机器程序计数器
公开(公告)号：US07757067B2
公开(公告)日：2010-07-13
申请号：US10632222
申请日：2003-07-31
申请人： Gerard Chauvel , Serge Lasserre , Maija Kuusela
发明人： Gerard Chauvel , Serge Lasserre , Maija Kuusela
IPC分类号： G06F9/30 , G06F9/40
CPC分类号： G06F9/30149 , G06F9/30076 , G06F9/30181 , G06F9/30185 , G06F9/382 , G06F9/3879 , G06F12/0253 , G06F12/0804 , G06F12/0891 , G06F12/126 , G06F2212/502
摘要： A processor (e.g., a co-processor) comprising a decoder coupled to a pre-decoder, in which the decoder decodes a current instruction in parallel with the pre-decoder pre-decoding a subsequent instruction. In particular, the pre-decoder examines at least five Bytecodes in parallel with the decoder decoding a current instruction. The pre-decoder determines if a subsequent instruction contains a prefix. If a prefix is detected in at least one of the five Bytecodes, a program counter skips the prefix and changes the behavior of the decoder during the decoding of the subsequent instruction.
摘要翻译：包括耦合到预解码器的解码器的处理器（例如，协处理器），其中解码器与预解码器并行地解码当前指令，以对后续指令进行解码。特别地，预解码器与解码器解码当前指令并行地检查至少五个字节码。预解码器确定后续指令是否包含前缀。如果在五个字节码中的至少一个中检测到前缀，则程序计数器跳过前缀，并且在后续指令的解码期间改变解码器的行为。

3. 发明授权

US07500085B2 Identifying code for compilation 有权
标题翻译：识别编译代码
公开(公告)号：US07500085B2
公开(公告)日：2009-03-03
申请号：US11188504
申请日：2005-07-25
申请人： Gerard Chauvel
发明人： Gerard Chauvel
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： A processor comprising fetch logic adapted to fetch a set of instructions from memory, the set comprising a subset of instructions. The processor further comprises decode logic coupled to the fetch logic and adapted to process the set of instructions, and a clock coupled to the decode logic. When processed, an instruction from the set causes the clock to increment a counter external to the processor while the subset is processed. A status of the counter is manipulated to determine an efficiency level pertaining to the subset of instructions.
摘要翻译：一种包括提取逻辑的处理器，适于从存储器获取一组指令，该组包括指令的子集。处理器还包括耦合到提取逻辑并且适于处理该组指令的解码逻辑以及耦合到解码逻辑的时钟。当处理时，来自该集合的指令使得时钟在处理子集时递增处理器外部的计数器。控制计数器的状态来确定与指令子集有关的效率水平。

4. 发明授权

US07496930B2 Accessing device driver memory in programming language representation 有权
标题翻译：以编程语言表示访问设备驱动程序内存
公开(公告)号：US07496930B2
公开(公告)日：2009-02-24
申请号：US10831575
申请日：2004-04-22
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
IPC分类号： G06F13/00
CPC分类号： G09G5/39 , G06F3/14 , G09G5/393
摘要： In some embodiments, a storage medium comprises application software that performs one or more operations and that directly manages a device. The application software comprises instructions that initialize an application data structure (e.g., an object or array) usable by the application software to manage the device and also comprises instructions that map the application data structure to a memory associated with the device without the use of a device driver. In other embodiments, a method comprises initializing an application data structure to manage a hardware device and mapping the application data structure to a memory associated with the hardware device without the use of a device driver. The application data structure may store a single dimensional data structure or a multi-dimensional data structure. In some embodiments, the device being managed by the application software may comprise a display and the application software may comprise Java code.
摘要翻译：在一些实施例中，存储介质包括执行一个或多个操作并直接管理设备的应用软件。应用软件包括初始化应用软件可用于管理设备的应用数据结构（例如，对象或阵列）的指令，还包括将应用数据结构映射到与设备相关联的存储器而不使用设备驱动。在其他实施例中，一种方法包括初始化应用数据结构以管理硬件设备，并将应用数据结构映射到与硬件设备相关联的存储器，而不使用设备驱动程序。应用数据结构可以存储单维数据结构或多维数据结构。在一些实施例中，由应用软件管理的设备可以包括显示器，并且应用软件可以包括Java代码。

5. 发明授权

US07392269B2 Conditional garbage based on monitoring to improve real time performance 有权
标题翻译：基于监控的条件垃圾提高实时性能
公开(公告)号：US07392269B2
公开(公告)日：2008-06-24
申请号：US10631195
申请日：2003-07-31
申请人： Gerard Chauvel
发明人： Gerard Chauvel
IPC分类号： G06F17/30
CPC分类号： G06F12/126 , G06F9/30134 , G06F9/30174 , G06F12/0253 , G06F12/0804 , G06F12/0891 , G06F2212/502 , Y02D10/13 , Y10S707/99957
摘要： A system comprising a counter adapted to monitor the memory consumption of the allocated memory resources. Upon reaching or surpassing the memory resource threshold provided, the counter may indicate the need for garbage collection. The garbage collector assesses the memory and releases memory resources that are consumed by the programs but are not needed anymore. The recycled memory resources are thus provided to the programs and the counter is updated accordingly. In addition, the system may also include instructions requesting memory resources. After detecting such instructions, the memory usage counter is updated either by the exact amount of memory allocated or the estimated amount of memory allocated. The counter may be implemented in hardware or in software.
摘要翻译：一种系统，包括适于监视所分配的存储器资源的存储器消耗的计数器。达到或超过提供的内存资源阈值时，计数器可能表示需要进行垃圾收集。垃圾收集器评估内存并释放程序使用的内存资源，但不再需要。因此，将再循环的存储器资源提供给程序，并相应地更新计数器。另外，系统还可以包括请求存储器资源的指令。在检测到这样的指令之后，存储器使用计数器被分配的存储器的精确量或估计的分配的内存量更新。计数器可以硬件或软件来实现。

6. 发明授权

US07295576B2 Transport packet parser 有权
标题翻译：传输数据包解析器
公开(公告)号：US07295576B2
公开(公告)日：2007-11-13
申请号：US10404854
申请日：2003-04-01
申请人： Gerard Chauvel
发明人： Gerard Chauvel
IPC分类号： H04J3/24 , H04N7/167
CPC分类号： H04L49/3009 , H04L49/20
摘要： A transport packet parser (42) includes a transport packet header decoder (50) for identifying a packet identifier (PID) and continuity counter (CC) associated with a current packet. The PID along with an enable (En) bit is input to an PID associative memory (52) in search mode to identify an address associated with the PID. The address is used to access a CC associated with a previous packet for the same PID in a random access memory (62). The previous continuity counter is used along with other header information to determine whether the current packet satisfies predetermined criteria. If so, the packet is passed to a transport packet buffer for further processing.
摘要翻译：传输分组解析器（42）包括用于识别与当前分组相关联的分组标识符（PID）和连续性计数器（CC）的传输分组报头解码器（50）。在搜索模式下，将PID与使能（En）位一起输入到PID关联存储器（52），以识别与PID相关联的地址。地址用于在随机存取存储器（62）中访问与先前分组相关联的用于相同PID的CC。先前的连续性计数器与其他标题信息一起使用以确定当前分组是否满足预定标准。如果是这样，则将分组传递到传输分组缓冲器以进一步处理。

7. 发明授权

US07266824B2 Address space priority arbitration 有权
标题翻译：地址空间优先仲裁
公开(公告)号：US07266824B2
公开(公告)日：2007-09-04
申请号：US09932556
申请日：2001-08-17
申请人： Gerard Chauvel
发明人： Gerard Chauvel
IPC分类号： G06F3/00
CPC分类号： G06F9/30043 , G06F1/206 , G06F1/3203 , G06F1/329 , G06F12/0292 , G06F12/0879 , G06F12/0891 , G06F12/1027 , G06F12/1081 , G06F2201/81 , G06F2201/885 , G06F2212/1028 , Y02D10/13 , Y02D10/24
摘要： A digital system and method of operation is provided in which several processors (400[]) are connected to a shared resource (432). Each processor has a translation lookaside buffer (TLB) (310[]) that contains recently used page entries that each includes an access priority value. Access priority values are assigned to regions of address space, typically pages, according to the program or data that is stored on a given page. Access priority values are maintained in page tables with address translations, such that when a translated page address is loaded into a TLB, the access priority associated with that page is included in the TLB page entry. Arbitration circuitry (430) is connected to receive a request signal from each processor along with an access priority value (353[]) from each TLB in response to the requested address. The arbitration circuitry is operable to schedule access to the shared resource according to the access priority values provided by the TLBs.
摘要翻译：提供了一种数字系统和操作方法，其中几个处理器（400 []）连接到共享资源（432）。每个处理器具有翻译后备缓冲器（TLB）（310 []），其包含最近使用的页面条目，每个页面条目包括访问优先级值。根据存储在给定页面上的程序或数据，将访问优先级值分配给地址空间区域（通常是页面）。在具有地址转换的页面表中维护访问优先级值，使得当翻译的页面地址被加载到TLB中时，与该页面相关联的访问优先级被包括在TLB页面条目中。连接仲裁电路（430）以响应于所请求的地址从每个TLB接收来自每个处理器的请求信号以及来自每个TLB的访问优先级值（353 []）。仲裁电路可操作以根据由TLB提供的访问优先级值来调度对共享资源的访问。

8. 发明授权

US07174194B2 Temperature field controlled scheduling for processing systems 有权
标题翻译：温度场控制调度处理系统
公开(公告)号：US07174194B2
公开(公告)日：2007-02-06
申请号：US09932361
申请日：2001-08-17
申请人： Gerard Chauvel , Dominique D'Inverno , Darvin R. Edwards
发明人： Gerard Chauvel , Dominique D'Inverno , Darvin R. Edwards
IPC分类号： H04B1/38 , G06F1/32 , G06F9/46
CPC分类号： G06F9/4893 , G06F1/206 , G06F1/3203 , G06F1/329 , G06F11/0724 , Y02D10/16 , Y02D10/24
摘要： A multiprocessor system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power management software (38) in conjunction with profiles (36) for the various processing modules and the tasks to executed are used to build scenarios which meet predetermined power objectives, such as providing maximum operation within package thermal constraints or using minimum energy. Actual activities associated with the tasks are monitored during operation to ensure compatibility with the objectives. The allocation of tasks may be changed dynamically to accommodate changes in environmental conditions and changes in the task list. Temperatures may be computed at various points in the multiprocessor system by monitoring activity information associated with various subsystems. The activity measurements may be used to compute a current power dissipation distribution over the die. If necessary, the tasks in a scenario may be adjusted to reduce power dissipation. Further, activity counters may be selectively enabled for specific tasks in order to obtain more accurate profile information.
摘要翻译：多处理器系统（10）包括多个处理模块，例如MPU（12），DSP（14）和协处理器/ DMA通道（16）。电力管理软件（38）结合用于各种处理模块的简档（36）和执行的任务被用于构建满足预定功率目标的场景，例如在封装热约束内提供最大操作或使用最小能量。在操作过程中监视与任务相关的实际活动，以确保与目标的兼容性。可以动态地改变任务的分配，以适应环境条件的变化和任务列表的变化。可以通过监视与各种子系统相关联的活动信息来在多处理器系统中的各个点计算温度。活动测量可用于计算模具上的当前功耗分布。如果需要，可以调整场景中的任务以减少功耗。此外，可以为特定任务选择性地启用活动计数器，以便获得更准确的简档信息。

9. 发明申请

US20060026404A1 Method and system to construct a data-flow analyzer for a bytecode verfier 有权
标题翻译：构建一个字节码verfier的数据流分析器的方法和系统
公开(公告)号：US20060026404A1
公开(公告)日：2006-02-02
申请号：US11188502
申请日：2005-07-25
申请人： Gilbert Cabillic , Jean-Philippe Lesot , Mikael Peltier , Gerard Chauvel
发明人： Gilbert Cabillic , Jean-Philippe Lesot , Mikael Peltier , Gerard Chauvel
IPC分类号： G06F9/44
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： The problems noted above are solved in large part by a method and system to construct a data-flow analyzer for a bytecode verifier using existing hardware resources and software. Specifically, micro-sequences and JSM hardware resources may be employed fetch a first instruction, apply the first instruction to a decode logic of a processor, trigger execution of a first series of instructions by the decode logic that pops a first value off of a data structure, such as a stack or local variable map, the first value indicative of a parameter type pushed on the stack or local variable map by a previously decoded instruction; and verify that the first value is a parameter type expected by the first instruction.
摘要翻译：上述问题在很大程度上是由现有硬件资源和软件构成用于字节码验证器的数据流分析器的方法和系统。具体来说，可以采用微序列和JSM硬件资源来取得第一指令，将第一指令应用于处理器的解码逻辑，由解码逻辑触发第一系列指令的执行，该解码逻辑从数据中弹出第一值结构，例如堆栈或局部变量映射，指示通过先前解码的指令来推送在堆栈上的参数类型的第一值或局部变量映射; 并验证第一个值是第一个指令预期的参数类型。

10. 发明申请

US20060026397A1 Pack instruction 审中-公开
标题翻译：包装说明
公开(公告)号：US20060026397A1
公开(公告)日：2006-02-02
申请号：US11116897
申请日：2005-04-28
申请人： Gilbert Cabillic , Jean-Philippe Lesot , Gerard Chauvel , Dominique D'Inverno , Jaques Mequin
发明人： Gilbert Cabillic , Jean-Philippe Lesot , Gerard Chauvel , Dominique D'Inverno , Jaques Mequin
IPC分类号： G06F9/00
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012 , Y02D10/13
摘要： A processor executes an instruction that causes a source data field from a first source register to be copied to a destination register at a programmable position within the destination register. The instruction is particularly useful for generating media-based bitstreams (e.g., audio, video). In some embodiments, a system (e.g., a communication device such as cellular telephone) includes a processor capable of executing the instruction as described above.
摘要翻译：处理器执行指令，其使来自第一源寄存器的源数据字段被复制到目的地寄存器中的可编程位置处的目的地寄存器。该指令对于生成基于媒体的比特流（例如，音频，视频）特别有用。在一些实施例中，系统（例如，诸如蜂窝电话的通信设备）包括能够执行如上所述的指令的处理器。

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